JPH09101380A - Electronic time piece - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a solar electronic time piece having an alarm function and chrono metric function capable of a high speed revolution and reverse revolution even under fluctuating voltage by determining the selective conditions of abnormal pulse selection circuit with using a load compensation control circuit. SOLUTION: Electricity generated by a solar cell 45 is stored in an electric dual layer capacitor 70 and a time piece circuit 100 is driven by the power source Vc of the capacitor 70. For example, a third high speed pulse generation circuit 107 makes up high speed pulses Pc1 to Pc8 (abnormal pulse) based on the signal of frequency divider circuit 102 and supplies it to the third high speed pulse selection circuit 112. The selection circuit 112 is controlled by a first load compensation control circuit 114, determined for selection condition, selects one of high speed pulses of Pc1 to Pc8, and supplies to a chrono hand control circuit 118. The control circuit 118 supplies the high speed pulse Pc to a third drive circuit 123 according to the time measurement of a time piece control circuit 113. The drive circuit 123 drives a third step motor 30 and progress the chrono metic hand.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic timepiece having a step motor capable of high speed rotation and reverse rotation under various driving conditions such as voltage.

[0002]

2. Description of the Related Art Conventionally, a solar cell is used for a dial,
Electronic timepieces have been commercialized in combination with electric storage means such as electric double layer capacitors instead of batteries. (Hereinafter, this electronic timepiece is called a solar timepiece.) The output voltage of the electric double layer capacitor is not constant, so the method of driving the step motor of the solar timepiece is to prepare multiple normal pulses with different driving force for driving. By providing a detecting means for detecting rotation and non-rotation, and selecting and outputting the normal pulse that can be driven with the lowest current consumption from the plurality of normal pulses and driving the step motor, the voltage can be changed. It corresponded.

A conventional solar timepiece will be described with reference to the drawings. FIG. 5 is a block diagram of a conventional solar clock,
FIG. 3 is a waveform diagram of the normal pulse Ps of the solar timepiece shown in FIG. In FIG. 5, 45 is a solar cell that generates electricity by light, 70 is an electric double layer capacitor that stores electric power,
Reference numeral 10 is a first step motor, and reference numeral 150 is a clock circuit that operates by the electric power of the electric double layer capacitor 70. 1
Reference numeral 01 is an oscillator circuit that creates a reference clock required for circuit operation, 102 is a frequency divider circuit that divides the reference clock created by the oscillator circuit 101, and 103 is the first step motor 10
, A first normal pulse generation circuit for generating normal pulses Ps1 to Ps8 for normally driving and a correction pulse Psh for correction driving, and 108 is the first normal pulse generation circuit 1
A first normal pulse selection circuit for selecting one of the normal pulses Ps1 to Ps8 created by 03.
133 is a timepiece control circuit that measures time based on the signal of the frequency dividing circuit 102, and 120 is the first step motor 10
A first drive circuit for driving the first normal pulse selection circuit 108, which is controlled by the timepiece control circuit 133.
Of the normal pulse Ps output by the first drive circuit 12 every second.
The second hand control circuit 119 for supplying 0, the first detection circuit 119 for detecting the rotation and non-rotation of the first step motor 10, 11
Reference numeral 4 is a first load compensation control circuit that controls the first normal pulse selection circuit 108 based on the determination result of the first detection circuit 119.

Next, the circuit operation will be described. The electric energy generated by the solar cell 45 is stored in the electric double layer capacitor 70. The clock circuit 150 uses the electric double layer capacitor 70 as a power source and is driven by the power source voltage Vc. The first normal pulse generating circuit 103 is the frequency dividing circuit 10
The first normal pulse selection circuit 1 generates normal pulses Ps1 to Ps8 and a correction pulse Psh which will be described later based on the signal 2
08. The first normal pulse selection circuit 108 is controlled by the first load compensation control circuit 114, selects one normal pulse Ps from the normal pulses Ps1 to Ps8 by the method described later, supplies it to the second hand control circuit 115, and is currently selected. The magnitude of the normal pulse Ps is transmitted to the first load compensation control circuit 114 by the signal S. The second hand control circuit 115 sets 1 according to the time measured by the clock control circuit 133.
The normal pulse Ps is supplied to the first drive circuit 120 every second. The first drive circuit 120 drives the first step motor 10 with the normal pulse Ps. First detection circuit 119
Detects whether the first step motor 10 has rotated by the normal pulse Ps. First load compensation control circuit 1
Reference numeral 14 controls the first normal pulse selection circuit 108 according to the determination result of the first detection circuit 119. If the first normal pulse selection circuit 108 is rotated, the same normal pulse Ps is output next time, and if it is not rotated, the correction pulse Psh is output and next time. The normal pulse Ps is switched to the larger normal pulse Ps and output.

Next, the pulse shape will be described. FIG.
(A) to (c) are eight prepared normal pulses Ps1 to Ps
It is a wave form diagram of normal pulse Ps1, Ps4, Ps8 in s8. The normal pulses Ps1 to Ps8 have a pulse width of 4 ms, but have different pulse pause parts by 0.05 ms. The normal pulse Ps1 has a pulse pause portion Ks1 of 0.35 ms every 1 ms as shown in FIG. 3A, and Ps4 has a pulse pause Ks1 of 0.25 every 1 ms as shown in FIG. 3B.
The pulse pause part Ks4 of ms is provided, and as shown in FIG. 3C, Ps8 does not have the pulse pause part. Also, although not shown, normal pulses Ps2, Ps3, Ps5, Ps6, P
s7 is 0.3ms for every 1ms, 0.25ms,
It has pulse pause parts of 0.15 ms, 0.1 ms, and 0.05 ms. FIG. 3D shows the correction pulse P that is output when it is determined that the normal pulse Ps could not be driven.
It is sh. The correction pulse Psh is 3 from the normal pulse Ps.
It is output 2 ms later, and the latter half 6 ms with a pulse width of 12 ms
Has a pulse pause of 0.5 ms every 1 ms.

[0006]

[Table 1]

As described above, since the normal pulses Ps1 to Ps8 have different pulse pause portions, the lowest drivable voltage value, that is, the lowest drivable voltage is different. Table 1 is a table showing the pulse pause part of the normal pulse Ps and the minimum drivable voltage. Since the normal pulse Ps8 has no rest portion, it has the largest driving force among the normal pulses Ps1 to Ps8 and can be driven even when the power supply voltage Vc is 1.0V. The normal pulse Ps1 has a large resting portion of 0.35 ms and the smallest driving force. Therefore, low power supply voltage V
c cannot be driven, and can be driven only when the power supply voltage Vc is 2.6 V or more. However, when the power supply voltage Vc is high, the normal pulse Ps8 has an unnecessarily high driving power and consumes a large amount of current. On the other hand, the normal pulse Ps1 has a power supply voltage Vc of 2.
At 6 V or higher, the current consumption can be smaller than that of any of the normal pulses Ps2 to Ps8. Normal pulse Ps2 to Ps
7 has the lowest drivable voltage as shown in Table 1 according to each pulse pause part. The solar timepiece corresponds to the power supply voltage Vc of the electric double layer capacitor 70 and is driven by the optimum normal pulse Ps that consumes the least current.

The method for selecting the optimum normal pulse Ps will be described in more detail. In the conventional load compensation operation control method, when a certain normal pulse Ps (n) cannot be output and driven, the next output normal pulse Ps is changed to a normal pulse Ps (n + 1) one rank higher. If the normal pulse Ps
(N) is output, but the same normal pulse Ps (n) is output a fixed number of times, for example, 100 times in succession, and then the next normal pulse Ps outputs a normal pulse Ps (n-1) that is one rank smaller. doing. An optimum normal pulse can be selected by always performing the above operation. For example, when the power supply voltage Vc is 1.7 V and the normal pulse Ps
The operation when 3 is output will be described. From Table 1, the minimum normal pulse Ps that can be driven at the power supply voltage Vc of 1.7V is the normal pulse P whose minimum operable voltage is 1.6V.
s5, and the normal pulse Ps5 is the power supply voltage Vc1.7V
The optimum normal pulse Ps at the time. The lowest drive voltage of the normal pulse Ps3 is 2.0 V, and the power supply voltage Vc
Cannot be driven at 1.7V. Therefore, it is determined that the first step motor 10 cannot rotate and the first detection circuit 119 cannot rotate. Based on this determination result, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to output the correction pulse Psh, and switches the next normal pulse Ps to the one larger normal pulse Ps4 for selective output. Therefore, the first step motor 10 is surely corrected and driven again by the correction pulse Psh, and the next normal pulse Ps outputs the normal pulse Ps4 which is one larger. However, from Table 1, the normal pulse Ps4 has a minimum drivable voltage of 1.8 V, so that the power supply voltage Vc is 1.
After all, it cannot be driven at 7V. Therefore, it is determined that the first step motor 10 cannot rotate and the first detection circuit 119 cannot rotate. Based on this determination result, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to output the correction pulse Psh and also to switch the next normal pulse Ps to the one larger normal pulse Ps5 for selective output. Therefore, the first step motor 10 is surely corrected and driven again by the correction pulse Psh, and the next normal pulse Ps outputs the normal pulse Ps5 which is one larger. The normal pulse Ps5 has a minimum drivable voltage of 1.6V and can be driven even when the power supply voltage Vc is 1.7V. Therefore, it is determined that the first detection circuit 119 can rotate. Based on this determination result, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 so that the correction pulse Psh is not output and the next normal pulse also outputs the same normal pulse Ps5 as the previous one. Therefore, the next normal pulse Ps also outputs the normal pulse Ps5. Further, when the power supply voltage Vc continues to be 1.7 V, when the normal pulse Ps5 is continuously output 100 times, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to control the next normal pulse. Ps is switched to one smaller normal pulse Ps4 and selectively output. However, the normal pulse Ps4
Then, when the power supply voltage Vc is 1.7 V, the driving cannot be performed and the correction pulse Psh is output to perform the correction driving, and the next normal pulse is again output by one larger normal pulse Ps5. As described above, when the power supply voltage Vc is 1.7 V, the drive is continued by the optimum normal pulse Ps5 except that the drive cannot be performed by the normal pulse Ps4 once every 100 times and the correction drive is performed by the correction pulse Psh. Although the current consumption of the correction pulse Psh is larger than that of the normal pulse Ps, it is once in 100 times, which is very small on average and is not a problem.

Next, the power supply voltage Vc is 1.7V to 2.1V.
The case of going up to will be described. Power supply voltage V from Table 1
When c is 2.1 V, the normal pulse Ps3 whose minimum drivable voltage is 2.0 V is the optimum normal pulse Ps, and with the normal pulse Ps5, the driving force is too large and the current consumption becomes unnecessarily large. By the way, as described above, the normal pulse Ps4 is output once each while the normal pulse Ps5 is output 100 times. The normal pulse Ps4 has a minimum drivable voltage of 1.8 V and cannot be driven when the power supply voltage Vc is 1.7 V, but can be driven when the power supply voltage Vc is 2.1 V. Therefore, if the power supply voltage Vc is 2.1 V when the normal pulse Ps4 is output, the first step motor 1
0 is driven by the normal pulse Ps4, and the first detection circuit 119
Determines that it was able to rotate. First load compensation control circuit 114
The first normal pulse selection circuit 108 is determined by this determination result.
Is controlled so that the correction pulse Psh is not output, and the same normal pulse Ps4 as the previous time is selectively output as the next normal pulse. Then, the next normal pulse Ps is also output as the normal pulse Ps4. When the normal pulse Ps4 is output 100 times in succession, the first load compensation control circuit 114
Controls the first normal pulse selection circuit 108 to switch the next normal pulse Ps to one smaller normal pulse Ps3 for selective output. The normal pulse Ps3 has a low drivable voltage of 2.0 V and can be driven even when the power supply voltage Vc is 2.1 V, and the normal pulse Ps3 is output as the next normal pulse Ps. With the above operation, the power supply voltage Vc is 2.1V
At this time, the optimum normal pulse Ps3 is selected and output. After outputting the normal pulse Ps3 100 times, one smaller normal pulse Ps2 is output, but with the normal pulse Ps2, the power supply voltage Vc cannot be driven at 2.1 V, and after the correction drive with the correction pulse Psh, the next normal pulse is the normal pulse. Ps3 is output again. In this way, it is possible to select and output an optimum normal pulse for the power supply voltage Vc that fluctuates. This operation works not only for voltage fluctuations but also for a driving load such as a calendar, and an optimum normal pulse can always be selected and output. Hereinafter, the above operation will be referred to as a multi-stage load compensation operation.

Recently, electronic timepieces are required to have various functions such as an alarm function and a chronograph function in addition to a normal time display. (Hereinafter, the chronograph is called chronograph)
Driving ability by unusual pulse such as high-speed rotation and reverse rotation is required when switching from normal time to alarm time and when displaying chronograph, and solar clock is no exception. However, with a solar clock, the power supply voltage fluctuates greatly, but with an unusual pulse such as a high-speed pulse or a reverse pulse with a fixed fixed pulse width, sufficient energy to drive the motor is obtained when the voltage is low. It is known that the rotor cannot be driven well because the rotor overruns when the voltage becomes high, and thus the rotor can be driven only in a narrow voltage range. Therefore, it cannot support the power supply voltage that fluctuates greatly like a solar clock. And as a driving means effective for voltage fluctuation, there is the above-mentioned multi-stage load compensation operation,
It is conceivable to perform high-speed rotation or reverse rotation by this method. However, in the multi-stage load compensating operation, since there is a period for detection and an output period for the correction pulse, there is a problem that the period until the output of the next pulse becomes long and it cannot be driven at high speed. For example, even if the pulse width of the normal pulse is as short as about 4 ms, it has a detection period of about 20 ms, and if it cannot rotate, a correction pulse having a width of 32 ms to 12 ms is output. Therefore, the time until the driving with the correction pulse ends, that is, the time until the correction pulse is output 32 ms and the pulse width of the correction pulse 12 ms
The next normal pulse cannot be output during 50 ms, which is the total of about 8 ms of stabilization time. Therefore, the multi-stage load compensating operation cannot be driven with a pulse interval of 50 ms or less. That is, it cannot be driven at a high speed of 20 Hz or higher. Therefore, it was difficult for the conventional solar clock to rotate at high speed or reverse. As one means for solving the above problem, there is a method of detecting a power supply voltage and outputting a high-speed pulse or a reverse pulse having a pulse width corresponding to the voltage at that time.
As an example of detecting the voltage and changing the pulse width of the reverse pulse, a step motor for an electronic timepiece is proposed in JP-A-55-59375.

[0011]

However, in the case of performing high-speed rotation or reverse rotation in a wide voltage range of about 1 to 3 V as in a solar timepiece, a plurality of high-speed pulses and reverse rotation pulses are prepared and these pulses are driven. It is necessary to detect a plurality of voltages corresponding to the possible voltage range. For example, 1
1.3V, 1.3 to 1.7V, 1.7 to 2.3V, 2.
It is divided into four voltage ranges of 3 to 3V, and when trying to output a high-speed pulse and a reverse pulse corresponding to each voltage range, 1V, 1.3V, 1.7V, 2.3V and 3V are obtained.
Point voltage detection is required. In addition, considering the environment such as the variation of the parts used and the temperature used, the voltage detection requires a considerable accuracy in order to ensure the operation. It is very difficult to accurately detect such a large number of voltages in a small system such as an electronic timepiece.

The present invention solves the above problems and enables an alarm function by enabling high-speed rotation or reverse rotation by a high-speed pulse or reverse rotation pulse which is an abnormal pulse without performing voltage detection even under varying voltage. The purpose of the present invention is to provide a solar electronic timepiece having a chrono function.

[0013]

In order to achieve the above object, an electronic timepiece according to the present invention comprises a power supply means, a first step motor, and a driving force for driving the first step motor. Normal pulse generation means for generating a plurality of different normal pulses, a normal pulse selection circuit for selectively outputting one of the plurality of normal pulses, detection means for detecting rotation / non-rotation of the first step motor, and the detection In an electronic timepiece having a load compensation control circuit that determines the selection condition of the normal pulse selection circuit according to the detection signal of the means, a second step motor and a plurality of different driving forces for driving the second step motor are provided. The non-normal pulse generating means for generating a non-normal pulse and the non-normal pulse selection circuit for selectively outputting one of the plurality of non-normal pulses are provided. Pulse selection circuit is characterized in that it is determined the selected condition by the load compensation control circuit.

The first step motor and the second step motor are the same step motor.

The non-normal pulse generating means is a high speed pulse generating means.

The non-normal pulse generating means is a reverse pulse generating means.

The power supply means is a rechargeable power supply means.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION An electronic timepiece according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a plan view of the electronic timepiece according to the embodiment of the present invention. In the figure, 1 is an electronic timepiece, 10 is a first step motor, 14 is a second wheel train, and 15
Is the second hand. The first step motor 10 is the second wheel train 14
The second hand 15 is moved via the. 20 is a second step motor, 24 is an hour / minute wheel train, 25 is a minute hand, and 26 is an hour hand. The step motor 20 moves the minute hand 25 and the hour hand 26 via the hour / minute train wheel 24. Reference numeral 30 is a third step motor, 34 is a chrono wheel train, and 35 is a chrono hand. The third step motor 30 drives the chrono hands 35 via the chrono train wheel 34. Reference numeral 40 is a character plate composed of a solar cell, and an hour character 41, a chronograph 43, a time mode mark 61, an alarm mode mark 62, and a chrono mode mark 63 are printed. 53 is an M button for switching between time mode, alarm mode and chrono mode, 5
1 is the S button for starting and stopping Chrono, 5
2 is an R button for resetting the chronograph, and 50 is a correction button for time adjustment. Reference numeral 60 denotes a mode hand that is mechanically driven by the M button and indicates any one of the time mode mark 61, the alarm mode mark 62, and the chrono mode mark 63. Reference numeral 80 denotes a calendar display unit, which displays the date by rotating the date dial 81 from the hour hand 26 through the train wheel.

First, the function of the electronic timepiece 1 and its operating method will be described. The electronic timepiece 1 has functions of an alarm mode and a chrono mode in addition to the normal time mode. Each time the M button 53 is pressed, the mode hand 60 sequentially switches and points the time mode mark 61, the alarm mode mark 62, and the chrono mode mark 63, and the electronic timepiece 1 performs the function corresponding to the mode pointed to. The electronic timepiece 1 of FIG. 2 shows the state of the normal time mode, the mode hand 60 indicates the time mode mark 61, and the second hand 1
5, the minute hand 25 and the hour hand 26 display the normal time 10:10:35, and further the date plate 8 of the calendar display section 80.
15 indicates the 15th of the date. In the normal time mode, the mode hand 60 points to the time mode mark 61, the second hand 15 is moved every second by the first step motor 10 to display the second of the normal time, and the minute hand 25,
The hour hand 26 and the date plate 81 are moved by the second step motor 20 every 20 seconds, and the hour and minute of the normal time and the date are displayed. Note that the date plate 81 meshes with the gears at 0:00 and is fed for one day in a short time. At this time, however, the driving load becomes larger than usual and the second step motor 20 becomes difficult to rotate. The control of the pulse in the variation of the load will be described later.

When the M button 53 is pressed in the normal time mode, the mode hand 60 switches from the time mode mark 61 to the alarm mode mark 62 to point to it, and the alarm mode is entered. Then, the second step motor 20 rotates at high speed at 64 Hz, and the minute hand 25 and the hour hand 26 move clockwise to shift to the display of the hour and minute of the set alarm time.
Further, if the correction button 50 is kept pressed in the alarm mode, the second step motor 20 rotates at high speed at 64 Hz,
The minute hand 25 and the hour hand 26 are moved clockwise to correct the alarm time. When the correction button 50 is released, the second step motor 20 stops, and the time pointed by the minute hand 25 and the hour hand 26 at that time becomes the newly set alarm time. The alarm time can be corrected by the above operation. The second hand 15 also displays the second at the normal time even in the alarm mode, and is moved by the first step motor 10 every second.

When the M button 53 is pressed again, the mode hand 60 switches from the alarm mode mark 62 to the chrono mode mark 63 to point to the chrono mode. The second step motor 20 reverses at 32 Hz,
The minute hand 25 and the hour hand 26 move counterclockwise to shift from the hour / minute display of the alarm time to the hour / minute display of the normal time.
The chronograph hand 35 is stopped at the 12 o'clock position as shown in FIG. When the S button 51 is pressed in the chrono mode, a start operation is performed, the third step motor 30 rotates at high speed at 100 Hz, and the chrono hand 35 starts chrono hand movement.
Then, when the S button 51 is pressed again, the stop operation is performed, the third step motor 30 is stopped, and the chronograph hand 35 displays the stop position. Then, when the R button 52 is pressed, the reset operation is performed, and the third step motor 30 rotates forward 10
It rotates at high speed at 0 Hz, and the chronograph hand 35 moves to the 12 o'clock position and stops there. The second hand 15 also displays the second at the normal time even in the chrono mode, and is moved by the first step motor 10 every second.

Next, the circuit operation will be described. FIG. 1 is a block diagram showing a system of the electronic timepiece 1 shown in FIG. In FIG. 1, the same components as those in FIG. 5 are the same components. In FIG. 1, reference numeral 45 is a solar cell that generates light, 70 is an electric double layer capacitor that stores electric power, and 100 is a clock circuit that operates by the electric power of the electric double layer capacitor 70. Reference numeral 101 is an oscillator circuit that creates a reference clock necessary for circuit operation, 102 is a frequency divider circuit that divides the reference clock created by the oscillator circuit 101, and 103 is a normal pulse Ps1 to normally drive the first step motor 10. Ps8 and a first normal pulse generation circuit that creates a correction pulse Psh for correction driving, and 104 creates normal pulses Pm1 to Pm8 for normally driving the second step motor 20 and correction pulses Pmh for correction driving. A second normal pulse generation circuit, 105 is a second high speed pulse generation circuit that creates high speed pulses Pf1 to Pf4 for rotating the second step motor 20 at high speed at 64 Hz, and 106 is a reverse rotation of the second step motor 20 at 32 Hz. A second reverse pulse generating circuit for generating reverse pulses Pb1 to Pb4 for
Reference numeral 07 is a third high-speed pulse generation circuit for generating high-speed pulses Pc1 to Pc8 for rotating the third step motor 30 at high speed at 100 Hz, and reference numeral 108 is one of the normal pulses Ps1 to Ps8 generated by the first normal pulse generation circuit 103. A normal pulse selecting circuit for selecting one normal pulse Ps, and a second normal pulse selecting circuit for selecting one normal pulse Pm among the normal pulses Pm1 to Pm8 created by the second normal pulse generating circuit 104. , 110 are high-speed pulses Pf1 generated by the second high-speed pulse generation circuit 105.
A second high-speed pulse selection circuit that selects one high-speed pulse Pf from among Pf4 to Pf4, and a second 111 that selects one reverse pulse Pb from among the reverse pulses Pb1 to Pb4 created by the second reverse pulse generation circuit 106. The reverse pulse selection circuit 112 is one of the high speed pulses Pc1 to Pc8 generated by the third high speed pulse generation circuit 107.
A third high-speed pulse selection circuit for selecting c, 113 is a clock control circuit for controlling time counting, alarms, and chrono function based on the signal of the frequency dividing circuit 102, and 120 is for driving the first step motor 10. First drive circuit of 115
Is a second hand control circuit 119 that is controlled by the timepiece control circuit 113 to supply the normal pulse Ps output from the first normal pulse selection circuit 108 to the first drive circuit 120 every second, and 119 is the rotation and non-rotation of the first step motor 10. 122 is a first detection circuit for detecting, and 114 is a first load compensation control circuit for controlling the first normal pulse selection circuit 108 and the third high-speed pulse selection circuit 112 based on the determination result of the first detection circuit 119.
Is a second drive circuit for driving the second step motor 20, 117 is a normal pulse Pm output from the second normal pulse selection circuit 109 controlled by the timepiece control circuit 113.
And a minute hand control circuit for selecting and outputting a necessary pulse from the normal pulse Pf output from the second high speed pulse selection circuit 110 and the reverse pulse Pb output from the second reverse pulse selection circuit 111 and supplying it to the second drive circuit 122. , 121 is a second detection circuit for detecting rotation and non-rotation of the second step motor 20, 116 is a second normal pulse selection circuit 109 and a second high-speed pulse selection circuit 110 based on the determination result of the second detection circuit 121. And a second load compensation control circuit for controlling the second reverse rotation pulse selection circuit 111, and 123 is the third step motor 3
The third drive circuit for driving 0, 118 is controlled by the timepiece control circuit 113, and the third high speed pulse selection circuit 11
A chronograph needle control circuit that supplies the high-speed pulse Pc output by 2 to the third drive circuit 123 in response to the start of the chronograph.
24 is a malfunction prevention circuit for preventing malfunctions due to inappropriate high-speed pulse Pf and reverse rotation pulse Pb, and 50a, 51a, 5
2a and 53a are a correction button 50 and an S button 5, respectively.
1, a correction switch, an S switch, an R switch, and an M switch which are operated by the R button 52 and the M button 53.

Next, the circuit operation will be described in detail. Second hand 15
And a first normal pulse generation circuit 103 for supplying a normal pulse Ps to the first step motor 10 and a first normal pulse selection circuit 1
08, first load compensation control circuit 114, second hand control circuit 11
5, the first driving circuit 120, and the first driving circuit 120 have the same operation as described in FIG. Electricity generated by the solar cell 45 is stored in the electric double layer capacitor 70. The clock circuit 100 uses the electric double layer capacitor 70 as a power source and is driven by the power source voltage Vc at that time. The electric double layer capacitor 70
When the withstand voltage of 3.0 V is reached, a discharge circuit (not shown) works to prevent the voltage from rising above 3.0 V. Further, when the electric double layer capacitor 70 becomes 1.0 V or less, it is determined that charging is insufficient, and the clock is stopped to notify that charging is insufficient. The first step motor 10, the second step motor 20, and the third step motor 30 are driven within the voltage range of the power supply voltage Vc of 1V to 3V.

First, the circuit operation relating to the driving of the third step motor 30 which moves the chronograph hand 35 will be described. The third high-speed pulse generation circuit 107 uses high-speed pulses Pc1 to Pc8, which will be described later, based on the signal from the frequency dividing circuit 102.
Is generated and supplied to the third high speed pulse selection circuit 112. The third high-speed pulse selection circuit 112 is the first load compensation control circuit 1
The high-speed pulse P controlled by
One of the high speed pulses Pc among c1 to Pc8 is selected and supplied to the chronograph needle control circuit 118. Chrono needle control circuit 11
Reference numeral 8 supplies a high-speed pulse Pc to the third drive circuit 123 in accordance with the chronograph information of the clock control circuit 113. The third drive circuit 123 drives the third step motor 30 by the high speed pulse Pc. The shape and selection method of the high-speed pulse Pc will be described in detail below.

[0025]

[Table 2]

Table 2 shows the pulse width of the high-speed pulse Pc created by the third high-speed pulse generator 107 and its high-speed pulse Pc.
6 is a table showing a drivable voltage range that is a range of a voltage that can be normally driven by. The high-speed pulses Pc1 to Pc8 each have the drivable voltage range shown in Table 2,
When the power supply voltage Vc is out of this voltage range, the third step motor 30 cannot be driven at high speed.
For example, the high speed pulse Pc4 has a pulse width of 3.6 ms and the drivable voltage range is 1.4V to 2.5V. Therefore, if the power supply voltage Vc is in the range of 1.4 to 2.5 V, the third step motor 30 can be rotated at high speed with the high speed pulse Pc4, but if the power supply voltage Vc is less than 1.4 V, the voltage is too low and the high speed pulse Pc4 is used. The third step motor 30 cannot be driven, and the timepiece goes wrong. Even if the power supply voltage Vc exceeds 2.5V, the third step motor 30 overruns and the high-speed pulse Pc4
Then, the third step motor 30 cannot be driven, and the clock goes wrong. That is, in order to drive the third step motor 30, it is necessary to select an appropriate high speed pulse Pc corresponding to the power supply voltage Vc. The high-speed pulse Pc (n) is set to be an appropriate high-speed pulse Pc corresponding to the normal pulse Ps (n), and the voltage value at the center of the drivable operating range of the high-speed pulse Pc (n) is usually It is set to be the lowest drivable voltage of the pulse Ps (n). For example, the drivable voltage range of the high-speed pulse Pc6 is the lowest drivable voltage of the normal pulse Ps6 of 1.4V.
Is set to 1.0 to 1.9V, which is almost the center.

By the way, the first step motor 10 is a motor for driving the second hand 15, and as described above, displays the second of the normal time in any mode. That is, it is always driven by the normal pulse Ps every one second, and the multistage load compensation operation is performed. Therefore, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 so as to select the minimum normal pulse Ps that can drive the first step motor 10. Therefore, the approximate value of the power supply voltage Vc can be known from the type of the normal pulse Ps output at that time. Then, the high-speed pulse Pc having a drivable voltage range that can be driven even with the lowest drivable voltage of the normal pulse Ps may be selected. For example, from Table 1, the minimum driveable range of the normal pulse Ps8 is 1.0V, and the minimum driveable voltage of the normal pulse Ps7 is 1.2V. Therefore, it is understood that the power supply voltage Vc is 1.0 V to 1.2 V when the normal pulse Ps8 is output. Further, from Table 2, the drivable voltage range of the high speed pulse Pc8 is 0.8 to 1.4V. Therefore, if the third step motor 30 is driven by the high-speed pulse Pc8 while the first step motor 10 is being driven by the normal pulse Ps8, the third step motor 30 can be sufficiently driven even in consideration of variations in parts. Further, from Table 1, the normal pulse Ps7 has a minimum drivable range of 1.2V, and the normal pulse Ps6 has a minimum drivable voltage of 1.4V. Therefore, the normal pulse Ps7
Is output, the power supply voltage Vc is 1.2 V
It can be seen that it is 1.4V. Therefore, from Table 2, the third step motor 30 may be driven by the high-speed pulse Pc7 having a drivable voltage range of 0.9 to 1.6V. Similarly, for the normal pulse Ps6, the high-speed pulse Pc6 and the normal pulse P
At s5, high-speed pulse Pc5, ... Normal pulse Ps
When the value is 1, the third step motor 30 should be driven by the high speed pulse Pc1.

On the other hand, in the first normal pulse selection circuit 108, the normal pulse Ps currently output is the normal pulses Ps1 to Ps.
Which pulse of s8 is output from the signal S to the first load compensation control circuit 114. Therefore, the first load compensation control circuit 114 recognizes the normal pulse Ps (n) currently output by the first normal pulse selection circuit 108. Then, the first load compensation control circuit 114 outputs the normal pulse Ps.
The high speed pulse Pc (n) corresponding to (n) may be controlled to be selected by the third high speed pulse selection circuit 112. For example, if the first normal pulse selection circuit 108 selects and outputs the normal pulse Ps2, the third high speed pulse selection circuit 112 is controlled to select the high speed pulse Pc2. Next, switching of the high speed pulse Pc will be described.
When the power supply voltage Vc decreases and the first step motor 10 cannot be driven by the normal pulse Ps (n), the first detection circuit 1
No. 19 determines that the rotation cannot be performed, and the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to output the correction pulse Psh based on the result of this determination, and outputs the next normal pulse Ps by one larger normal pulse Ps.
Switch to (n + 1). Further, the first load compensation control circuit 114 receives from the first detection circuit 119 the determination result that the rotation has failed, and at the same time, the third high speed pulse selection circuit 1
12 to control the high-speed pulse Pc to the high-speed pulse Pc (n)
To one larger high-speed pulse Pc (n + 1). When the normal pulse Ps (n) is continuously output 100 times, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to decrease the normal pulse Ps by one.
Output (n-1). However, there is a case where the driving force is too small to drive the first step motor 10 with one small normal pulse Ps (n-1). At that time, even if the high-speed pulse Pc (n) is switched to the high-speed pulse Pc (n-1), the driving force may be small and the third step motor 30 may not be driven. In consideration of this case, the high-speed pulse Pc output from the third high-speed pulse selection circuit 112 is a small high-speed pulse Pc (n
-1) is switched to one small normal pulse Ps
The switching is performed only after the first step motor 10 can be driven at (n-1).

The above operation will be described in more detail with reference to the drawings.
FIG. 6 is a block diagram of the first load compensation control circuit 114 and its surroundings. In FIG. 6, 114a is a 100-ary counter, 114b is a first rank-up circuit, 114c is a first rank-down circuit, 114d is a third rank-down control circuit, and 114e is a third rank determination circuit. In FIG. 6, components having the same numbers as in FIG. 1 are the same components. The first detection circuit 119 is the first step motor 1
It is determined whether 0 can be driven by the normal pulse Ps, and if it can be driven, the signal Y1 is output to the first load compensation control circuit 114, and if not, the signal N1 is output to the first load compensation control circuit 114. The signal Y1 is a 100-base counter 114a in the first load compensation control circuit 114.
Is input to The 100-ary counter 114a is a counter that counts whether or not the same normal pulse Ps could be driven 100 times in succession. When the signal Y1 is input 100 times in succession, the signal CU is input.
To the first rank down circuit 114c. The first rank down circuit 114c is the first normal pulse selection circuit 1
The signal S for transmitting the magnitude of the normal pulse Ps output from 08 is input. Then, when the signal CU is input, the first rank down circuit 114c outputs the signal D1 to control the first normal pulse selection circuit 108 to switch the normal pulse Ps to one smaller normal pulse Ps for selection. However, if the signal N1 is input to the R terminal of the 100-base counter 114a before the signal Y1 reaches 100 times, 10
The zero-base counter 114a is reset on the way and counts the signal Y1 again from the beginning. The signal N1 is also input to the first rank-up circuit 114b. The first rank-up circuit 114b receives the signal S for transmitting the magnitude of the normal pulse Ps output from the first normal pulse selection circuit 108. When the signal N1 is input, the first rank-up circuit 114b outputs the signal U1 to control the first normal pulse selection circuit 108 to switch the normal pulse Ps to one larger normal pulse Ps for selection.

When the signal CU is not input to the third rank down control circuit 114d, the third rank down control circuit 114d controls the third high speed pulse selection circuit 112,
The high-speed pulse Pc corresponding to the signal S transmitting the magnitude of the normal pulse Ps output from the first normal pulse selection circuit 108 is selected. In this case, the high-speed pulse Pc (n) corresponds to the normal pulse Ps (n) selected at that time.
Select For example, when the first step motor 10 can rotate with the normal pulse Ps (n), the first detection circuit 119 outputs the signal Y1. As described above, the first normal pulse selection circuit 108 selects the normal pulse Ps (n) by the signal Y1. Further, the signal Y1 is the third rank down control circuit 1
14d, but if it is not the 100th time, 1
The CU counter 114a does not output the signal CU. At this time, the third rank-down control circuit 114d selects the high-speed pulse Pc (n) corresponding to the signal S transmitting the magnitude of the normal pulse Ps (n) output from the first normal pulse selection circuit 108. Controls the high-speed pulse selection circuit 112. Therefore, the normal pulse Ps (n) and the fast pulse Pc (n) are selected correspondingly. If the first step motor 10 cannot rotate due to the normal pulse Ps (n), the first detection circuit 119 outputs the signal N1. The signal N1 causes the first normal pulse selection circuit 108 to select one larger normal pulse Ps (n + 1) as described above. Further, the first normal pulse selection circuit 108 informs the third rank down control circuit 114d by the signal S that it has switched to the larger normal pulse Ps (n + 1). At this time, the third rank down control circuit 114d selects the high-speed pulse Pc (n + 1) corresponding to the signal S transmitting the magnitude of the normal pulse Ps (n + 1) output from the first normal pulse selection circuit 108. Controls the high-speed pulse selection circuit 112. Therefore, the normal pulse Ps
(N + 1) and the fast pulse Pc (n + 1) are selected correspondingly.

However, when the signal CU is output from the 100-base counter 114a, the third rank down control circuit 114
d is the third high-speed pulse so that the same high-speed pulse Pc as the previous time is selected without switching the high-speed pulse Pc regardless of the signal S transmitting the magnitude of the normal pulse Ps output from the first normal pulse selection circuit 108. Selection circuit 112
Control. For example, when the first normal pulse selection circuit 108 selects the normal pulse Ps (n), the first normal pulse selection circuit 108 outputs the signal S so that the normal pulse Ps selected is the normal pulse Ps (n). ). The third rank determination circuit 114e outputs the signal S
The high speed pulse Pc (n) is selected by. Successively 100 times with normal pulse Ps (n) 1st step motor 1
When 0 can be driven, the signal Y1 is continuously output 100 times from the first detection circuit 119. Then, the signal CU is output from the 100-ary counter 114a. With this signal CU, the first rank-down circuit 114c outputs the signal D1 and controls the first normal pulse selection circuit 108 to control the normal pulse Ps.
Select (n-1). Then, the first normal pulse selection circuit 108 outputs the signal S to notify that the selected normal pulse Ps is the normal pulse Ps (n-1). This signal S is transmitted to the third rank determination circuit 114e, but the signal CU is output from the 100-base counter 114a.
Is output, and the third rank down control circuit 114d is output.
Controls the third rank determination circuit 114e so as to select the same high-speed pulse Pc (n) as the previous one regardless of the signal S. Therefore, even if the same normal pulse Ps (n) is output 100 times and then switched to the smaller normal pulse Ps (n-1), the high-speed pulse Pc selected by the third high-speed pulse selection circuit 112 is still the high-speed pulse Pc. (N) is selected. Next time, the first step motor 10 is driven by the normal pulse Ps (n-1).
When it can be driven with s (n-1), the first detection circuit 119 outputs the signal Y1. Third rank down control circuit 1
When this signal Y1 is input, 14d controls the third rank determining circuit 114e to switch the high-speed pulse Pc corresponding to the signal S output at this time to the high-speed pulse Pc (n-1) for selection. Also, the normal pulse Ps (n-1)
If it is not possible to drive with, the signal N1 is output from the first detection circuit 119 and input to the first rank-up circuit 114b. The first rank-up circuit 114b controls the first normal pulse selection circuit 108 to output the normal pulse Ps (n-1).
Is switched to one larger normal pulse Ps (n) for selection. Then, the signal S informs that the normal pulse Ps (n) is selected. By the way, the third rank up control circuit 114d controls the third rank determination circuit 114e while the high speed pulse Pc (n) is selected because the signal Y1 is not input. Then, from the next time, the operation of selecting the high-speed pulse Pc by the signal S is performed again. By the above operation, even when the same normal pulse Ps is continuously switched to the smaller normal pulse Ps 100 times, the high speed pulse Pc can select an appropriate high speed pulse Pc.

Next, an example will be described. When the power supply voltage Vc is 1.7 V, the first normal pulse selection circuit 10 is shown in Table 1
8 is a normal pulse Ps whose minimum drivable voltage is 1.6V
5 is selectively output. And the first load compensation selection circuit 1
14 is a high-speed pulse Pc for the third high-speed pulse selection circuit 112.
5 is selected. Therefore, when the chronograph is started here, the third step motor 30 is rotated at high speed by the high speed pulse Pc5. From Table 2, high-speed pulse Pc5
Driveable voltage range is 1.2 to 2.2V, 1.7V
The third step motor 30 can be sufficiently driven by the power supply voltage Vc. When the normal pulse Ps5 is output 100 times, the first load compensation control circuit 114 controls the first normal pulse selection circuit 108 to decrease the normal pulse P by one.
Select and output s4. When the power supply voltage Vc is 1.7 V with the normal pulse Ps4, the first step motor 10 cannot be driven, and the normal pulse Ps5 is output again from the next time. However, the switching of the high-speed pulse Pc of the third high-speed pulse selection circuit 112 is performed only when the normal pulse Ps4 can be driven. Therefore, even if the normal pulse Ps5 is switched to the normal pulse Ps4 as described above, the drive cannot be performed by the normal pulse Ps4, and therefore the third high speed pulse selection circuit 112 continues to select the high speed pulse Pc5. Therefore, when the chronograph is started with the power supply voltage Vc of 1.7 V, the third step motor 30 is always rotated at high speed by the appropriate high speed pulse Pc5.

Next, a case where the power supply voltage Vc fluctuates will be described. First, the case where the power supply voltage Vc drops from 1.7V will be described. The first step motor 10 is driven by the normal pulse Ps5 at 1.7V as described above. When the power supply voltage Vc gradually decreases from here, the driving force becomes weak with the normal pulse Ps5. Then, the power supply voltage Vc is the lowest drivable voltage 1.6 of the normal pulse Ps5.
When it becomes lower than V, the first step motor 10 cannot be driven by the normal pulse Ps5, and it is determined that the first detection circuit 119 cannot rotate. First load compensation selection circuit 11
4 is the first normal pulse selection circuit 108 based on this determination result.
To output the correction pulse Psh to drive the first step motor 10 for correction, and from the next time, the normal pulse Ps6
Is selected and output. At the same time, the first load compensation selection circuit 1
Reference numeral 14 controls the third high-speed pulse selection circuit 112 to switch the high-speed pulse Pc from the high-speed pulse Pc5 to the high-speed pulse Pc6 for selective output. Therefore, when the chronograph is started here, the third step motor 30 causes the high-speed pulse Pc6.
Rotated at high speed by. From Table 2, high-speed pulse Pc
The drivable voltage range of No. 6 is 1.0 to 1.9 V, which is 1.7.
The third step motor 30 can be sufficiently driven by the power source voltage Vc of V. In addition, the power supply voltage Vc drops gradually as the solar watch consumes the power stored in the electric double layer capacitor, and a sudden voltage drop does not occur, so the above operation can be sufficiently dealt with. is there.

Next, the case where the power supply voltage Vc rises from 1.7 V will be described. The first step motor 10 is driven by a normal pulse Ps5 at 1.7V. When the power supply voltage Vc gradually rises from here, the normal pulse Ps
At 5, the driving force increases. On the other hand, the first load compensation selection circuit 114 controls the first normal pulse selection circuit 108 to selectively output the normal pulse Ps4, which is one smaller than the normal pulse Ps5, once every 100 times. Then, the power supply voltage Vc becomes a voltage equal to or higher than the minimum drivable voltage 1.8 V of the normal pulse Ps4, and when the normal pulse Ps4 is selectively output at that time, the first step motor 10 causes the normal pulse Ps4
Will be driven by. Then, it is determined that the first detection circuit 119 can rotate, and the first load compensation selection circuit 114 causes the third high-speed pulse selection circuit 112 to apply the high-speed pulse Pc to the high-speed pulse Pc4 based on the determination result.
Switch to and select. Therefore, if the chronograph is started here, the third step motor 30 will generate a high-speed pulse Pc.
It is rotated at a high speed by 4. Fast pulse P from Table 2
The drivable voltage range of c4 is 1.4 to 2.5V.
The third step motor 30 can be sufficiently driven by the power supply voltage Vc of 8V. Even if the power supply voltage Vc becomes a voltage that can be driven by the normal pulse Ps4, the high speed pulse Pc5 must be waited for 100 seconds (normal pulse Ps100 times) at worst.
From the high speed pulse Pc4. However, the drivable voltage range of the high-speed pulse Pc (n) is set such that the upper limit voltage of each pulse is higher than the lowest drivable voltage of the normal pulse Ps (n-1) which is one smaller than the normal pulse Ps (n). The pulse Pc5 is 2.2V, which is higher than the minimum drivable voltage 1.8V of the normal pulse Ps4.
Can be driven up to. Furthermore, the electric double layer capacitor 70
Since the charging is performed by the solar cell 45, which does not have a large power generation capacity, the voltage does not rise rapidly in a short period of time, so that no problem occurs because the high-speed pulse Pc cannot be switched immediately. An appropriate high-speed pulse Pc for driving the third step motor 30 as described above
Can be selected.

Next, the circuit operation relating to the driving of the second step motor 20 for moving the minute hand 25 and the hour hand 26 will be described. The second normal pulse generation circuit 104 uses a signal from the frequency dividing circuit 102 to generate a normal pulse Pm as described later.
1 to Pm8 and the correction pulse Pmh are created and supplied to the second normal pulse selection circuit 109. The second normal pulse selection circuit 109 is controlled by the second load compensation control circuit 116 and is one of the normal pulses Pm1 to Pm8.
Is supplied to the minute hand control circuit 117. The second high-speed pulse generation circuit 105 creates high-speed pulses Pf1 to Pf4, which will be described later, based on the signal from the frequency dividing circuit 102 and supplies the high-speed pulses Pf1 to Pf4 to the second high-speed pulse selection circuit 110. The second high-speed pulse selection circuit 110 is controlled by the second load compensation control circuit 116, selects one high-speed pulse Pf from the high-speed pulses Pf1 to Pf4, and supplies it to the minute hand control circuit 117. The second reverse rotation pulse generation circuit 106 creates reverse rotation pulses Pb1 to Pb4, which will be described later, based on the signal from the frequency dividing circuit 102 and supplies the reverse rotation pulses Pb1 to Pb4 to the second reverse rotation pulse selection circuit 111. The second reverse rotation pulse selection circuit 111 is controlled by the second load compensation control circuit 116 and selects one of the reverse rotation pulses Pb1 to Pb4 and supplies it to the minute hand control circuit 117. The minute hand control circuit 117 selects the normal pulse Pm, the high-speed pulse Pf, or the reverse rotation pulse Pb as necessary according to the time, alarm, and chronograph information of the timepiece control circuit 113, and supplies it to the second drive circuit 122. The second drive circuit 122 drives the second step motor 20 by the normal pulse Pm, the high speed pulse Pf, and the reverse rotation pulse Pb supplied from the minute hand control circuit 117. The second detection circuit 121 uses the normal pulse P
It is determined by m whether the second step motor 20 has rotated. The second load compensation control circuit 116 determines the second normal pulse selection circuit 1 based on the determination result of the second detection circuit 121.
When 09 is controlled and rotated, the same normal pulse Pms as the previous time is output next time, and when it is not rotated, the correction pulse Pmh is output and the next normal pulse is increased by 1 and output. Further, the second load compensation control circuit 116 controls the second high speed pulse selection circuit 110 and the second reverse rotation pulse selection circuit 111 to respectively control the high speed pulse Pf1.
˜Pf4 and reverse rotation pulses Pb1 to Pb4, an appropriate high speed pulse Pf and reverse rotation pulse Pb are selected.

[0036]

[Table 3]

The shape of the normal pulse Pm for driving the second step motor 20 and the minimum drivable voltage will be described. The normal pulses Pm1 to Pm8 have exactly the same pulse shape as the above-mentioned normal pulses Ps1 to Ps8. Table 3 is a table showing the minimum drivable voltage in the case where there is no load due to the pulse pause part and the date plate 81 of the normal pulses Pm1 to Pm8 generated by the second normal pulse generation circuit 104. The minimum drivable voltage is about 0.1 V higher when the date plate is loaded than when it is not loaded. For example, the lowest drivable voltage of the normal pulse Pm3 when there is no load is 1.9V, but the lowest drivable voltage when there is a load is 2.0V. Further, the correction pulse Pm output when it is determined that the driving cannot be performed with the normal pulse Pm
h also has the same shape as the correction pulse Psh created by the above-described first normal pulse generation circuit 103. The correction pulse Pmh is output 32 ms after the normal pulse Pm,
With a pulse width of 12 ms, in the latter half 6 ms, 0.5 every 1 ms
It has a pulse pause of ms.

[0038]

[Table 4]

[0039]

[Table 5]

Next, the shapes of the high speed pulse Pf and the reverse pulse Pb and the drivable voltage range will be described. Table 4 shows the high speed pulse P created by the second high speed pulse generation circuit 105.
FIG. 5 is a table showing the pulse widths f1 to Pf4 and the drivable voltage range with and without the load by the date plate 81. Table 5 shows the pulses of the reverse rotation pulses Pb1 to Pb4 created by the second reverse rotation pulse generation circuit 106. 6 is a table showing a width and a drivable voltage range with and without a load by the date plate 81. FIG. 4 is a waveform diagram of the reverse pulse Pb according to the embodiment. The reverse pulse Pb is a positive phase pulse P as shown in FIG.
g1, a reverse phase pulse Pg2, and a positive phase pulse Pg3. Table 5 shows the positive phase pulse Pg1, the negative phase pulse Pg2, and the positive phase pulse Pg3.
The pulse width of is written. The high-speed pulses Pf1 to Pf4 each have the drivable voltage range shown in Table 4,
If the voltage is out of this driveable voltage range, the second step motor 20 cannot be driven at high speed. For example, from Table 4, the high-speed pulse Pf2 has a pulse width of 3.6 ms, and the drivable voltage range when there is no load due to the date plate is 1.4V to 2.8V. Therefore, the second step motor 20 is driven by the high-speed pulse Pf2 when there is no load due to the date plate.
To rotate at high speed, the power supply voltage Vc is 1.4 to 2.
Must be 8V. That is, in order to drive the second step motor 20, the power supply voltage Vc and the date dial 81
It is necessary to select the high-speed pulse Pf corresponding to the load. Similarly, the reverse rotation pulses Pb1 to Pb4 have the drivable voltage range shown in Table 5, and the second step motor 20 cannot be driven in the reverse rotation if the drivability voltage range deviates from the drivable voltage range. Then, in order to rotate the second step motor 20 in the reverse direction, it is necessary to select the reverse voltage Pb corresponding to the power supply voltage Vc and the load applied by the date plate 81.

The high speed pulse Pc for rotating the third step motor 30 at a high speed is driven at 100 Hz, whereas the high speed pulse Pf for rotating the second step motor 20 at a high speed is driven at 64 Hz. Therefore, even if the pulse width is the same, the high-speed pulse Pf can have a wider drivable voltage range than the high-speed pulse Pc. Therefore, high-speed pulse Pc
Drive the electronic timepiece in a voltage range of 1 to 3 V driven by eight types of high-speed pulses Pc1 to Pc8, while the high-speed pulse Pf includes four types of high-speed pulses Pf1 to Pf4.
Thus, the electronic timepiece can be driven by sharing the voltage range of 1 to 3 V driven. As shown in Table 4, when there is no load on the date plate 81, the drivable operating range of the high-speed pulse Pf1 is set so that it can be driven from the minimum drivable voltage 2.2V of the normal pulse Pm2 to the upper limit 3.0V of the power supply voltage Vc. 1.8
It is set to ~ 3.8V. Similarly, the drivable operating range of the high-speed pulse Pf2 can be driven from the minimum drivable voltage 1.7V of the normal pulse Pm4 to the upper limit of the voltage that is selectively output of the normal pulse Pm3, that is, the minimum operating voltage voltage 2.3V of the normal pulse Pm2. Is set to 1.4 to 2.8 V, and the drivable operating range of the high-speed pulse Pf3 is from the minimum drivable voltage 1.3 V of the normal pulse Pm6 to the normal pulse P
The upper limit of the voltage to be selectively output of m5, that is, the normal pulse P
The operating range of the high speed pulse Pf1 is set to 1.0 to 2.2V so that the electronic watch 1 can be driven at a minimum operating voltage of 1.7V up to 1.7V. The voltage is set to 0.8 to 1.7 V so that the voltage can be driven up to the upper limit of the selectively output voltage, that is, the lowest operating voltage voltage 1.3 V of the normal pulse Pm6. Note that this also applies to the reverse rotation pulse Pb, and the reverse rotation pulses Pb1 to Pb4 are set in substantially the same drivable voltage range as the high speed pulses Pf1 to Pf4.

The circuit operation of the method for selecting the high speed pulse Pf will be described in detail below. Second step motor 2
0 is driven every 20 seconds in the normal time mode, the minute hand 25,
The hour hand 26 is moved to display the hour and minute of the normal time, and the date dial 81 is also driven. That is, the second step motor 20 is normally driven by the pulse Pm and performs the multi-stage load compensating operation. The driving condition at that time is not only the fluctuation of the power source voltage Vc but also the fluctuation of the load due to the driving of the date plate 81. I also have. That is, the second load compensation control circuit 1
Reference numeral 16 controls the second normal pulse selection circuit 109 so as to select the minimum normal pulse Pm that can drive the second step motor 20 in accordance with the voltage and the load. Therefore, it is possible to know the comprehensive drive condition by the power supply voltage Vc and the load of the date plate 81 from the pulse width of the normal pulse Pm output at that time. Then, the high-speed pulse Pf having a drivable voltage range that can be driven even with the lowest drivable voltage of the output normal pulse Pm may be selected. By the way, due to the load on the date plate 81
The minimum drivable voltage increases about 0.1V, but the driveable operating range of the high speed pulse Pf also increases by about 0.1V due to the load on the date dial 81. Therefore, regardless of whether the date dial 81 is loaded or not, the high-speed pulse Pf may be selected under the same conditions as when the date dial 81 is not loaded. For example, from Table 3, when there is no load, the minimum driveable range of the normal pulse Pm8 is 0.9V, and the minimum driveable voltage of the normal pulse Pm6 is 1.3V. Therefore, when the normal pulse Pm8 or the normal pulse Pm7 is output, the power supply voltage V
It can be seen that c is 0.9V to 1.3V. Table 4
It can be seen that the drivable voltage range when there is no load of the higher speed pulse Pf4 is 0.8 to 1.6V. Therefore, when the second step motor 20 is being driven by the normal pulse Pm8 or the normal pulse Pm7, the second step motor 20 can be driven at a high speed by driving with the high speed pulse Pf4 in order to drive the second step motor 20 at a high speed even if variations in parts are taken into consideration. is there. When there is a load, Table 3 shows the normal pulse Pm
8 has a minimum drivable range of 1.0 V and a normal pulse Pm
6 has a minimum drivable voltage of 1.4V. Therefore, it is understood that the power supply voltage Vc is 1.0 V to 1.4 V when the normal pulse Pm8 or the normal pulse Pm7 is output. Further, from Table 4, the drivable voltage range when there is a load of the high-speed pulse Pf4 is 0.9 to 1.7V. Therefore, it is sufficient to drive with the high speed pulse Pf4. As described above, since the normal pulse Pm and the high-speed pulse Pf are pulses for driving the same second step motor 20, the voltage that can drive both the normal pulse Pm and the high-speed pulse Pf uniformly increases when there is a load. . Therefore, the normal pulse Pm
Since the relative voltage relationship between the high speed pulse Pf and the high speed pulse Pf does not change, the high speed pulse Pf may be selected with respect to the normal pulse Pm under the same conditions as when there is no load regardless of the presence or absence of a load.

[0043]

[Table 6]

Table 6 is a table showing the normal pulses Pm1 to Pm8, the high speed pulse Pf and the reverse pulse Pb selected at that time. A method of selecting the normal pulse Pm and the high-speed pulse Pf selected at that time will be described. The second normal pulse selection circuit 109 outputs from the signal M to the second load compensation control circuit 116 which of the normal pulses Pm1 to Pm8 the currently output normal pulse Pm is.
Therefore, the second load compensation control circuit 116 recognizes the normal pulse Pm currently output by the second normal pulse selection circuit 109. Then, the second load compensation control circuit 116 controls the second high-speed pulse selection circuit 110 to select the high-speed pulse Pf corresponding to the normal pulse Pm, which is shown in Table 6 and is the normal pulse Pm1. , Pm2
If so, the high-speed pulse Pf1 is changed to the normal pulses Pm3 and Pm.
If it is 4, the high-speed pulse Pf2 is used and the normal pulses Pm5, P
If m6, the high-speed pulse Pf3, the normal pulse Pm7,
If it is Pm8, the high speed pulse Pf4 is selectively output to the second high speed pulse selection circuit 110. Next, when the power supply voltage Vc decreases and the first step motor 10 cannot be driven with the normal pulse Pm (n), it is determined that the second detection circuit 121 cannot rotate, and the second load compensation control circuit 116 determines the second load compensation control circuit 116 based on this determination result. (2) The normal pulse selection circuit 109 is controlled to output the correction pulse Pmh, and the next normal pulse Pm is switched to the next larger normal pulse Pm (n + 1). The normal pulse Pm is the normal pulses Pm1 and Pm.
In the case of 3 and Pm7, the second load compensation control circuit 116 causes the second high-speed pulse selection circuit 110 to select the same high-speed pulse Pf as the previous one as it is, even if the second detection circuit 121 determines that the rotation cannot be performed. Also, the normal pulse Pm
Is a normal pulse Pm2, Pm4, Pm6, the second load compensation control circuit 116 receives a determination result from the second detection circuit 121 that the second load compensation control circuit 116 cannot rotate, and at the same time controls the second high speed pulse selection circuit 110 to control the high speed pulse Pf. To one larger high-speed pulse Pf. That is, even when non-rotation is detected by the normal pulses Pm1, Pm3, Pm5, and Pm7, the high-speed pulse Pf remains the high-speed pulses Pf1 and Pf.
2, Pf3, Pf4 are maintained, but normal pulse Pm2,
When non-rotation is detected in Pm4 and Pm6, the high speed pulse Pf is the high speed pulse Pf1 to the high speed pulse Pf, respectively.
The selection is changed to f2, from the high speed pulse Pf2 to the high speed pulse Pf3, and from the high speed pulse Pf3 to the high speed pulse Pf4.

When the same normal pulse Pm (n) is continuously output 100 times, the second load compensation control circuit 116 controls the second normal pulse selection circuit 109 to output the normal pulse Pm.
Is switched to one smaller normal pulse Pm (n-1). Normal pulse Pm (n) is normal pulse Pm3, Pm
5 and Pm7, one smaller normal pulse Pm
2, Pm4, Pm6, but the normal pulse Pm (n-1), that is, the normal pulse Pm2, Pm.
4 and Pm6, the high speed pulse Pf changes from the high speed pulse Pf2 to the high speed pulse Pf1, the high speed pulse Pf3 to the high speed pulse Pf2, and the high speed pulse Pf4.
The selection is changed to the high-speed pulse Pf3. However, if the small normal pulses Pm2, Pm4, and Pm6 do not move, the high-speed pulses Pf2, Pf3, and Pf4 are maintained as they are.

An example will be described. If the power supply voltage Vc is 1.6 V when there is no load on the date dial 81, the normal pulse Pm5 whose minimum drivable voltage is 1.5 V is the optimum normal pulse Pm, as shown in Table 3. In the normal time mode, the second load compensation selection circuit 116 is the second normal pulse selection circuit 1
09, and the normal pulse Pm5 is selectively output. Further, as shown in Table 6, the second high speed pulse selection circuit 110 is controlled to selectively output the high speed pulse Pf3. Therefore, when the normal time mode is switched to the alarm mode here, the second step motor 20 is rotated at high speed by the high speed pulse Pf3. From Table 4, the drivable voltage range of the high-speed pulse Pf5 is 1.0 to 2.2.
The second step motor 20 can be sufficiently driven with the power supply voltage Vc of 1.6V. When the normal pulse Pm5 is output 100 times in the normal time mode, the second load compensation selection circuit 116 controls the second normal pulse selection circuit 109 to output the normal pulse Pm4 which is one smaller. From Table 3, the minimum driveable voltage of the normal pulse Pm4 is 1.7V.
Therefore, the second step motor 20 cannot be driven with the power supply voltage Vc1.6V. And the second load compensation selection circuit 1
Reference numeral 16 again controls the second normal pulse selection circuit 109 to select and output the normal pulse Pm5 again from the next time. However, the switching of the high speed pulse Pf of the second high speed pulse selection circuit 110 is performed only when the second step motor 20 can be driven by the normal pulse Pm4, and the second step motor 20 can be driven by the normal pulse Pm4 as described above. If not, the second high speed pulse selection circuit 110 outputs the high speed pulse Pf.
Continue to select 3. Therefore, when the normal time mode is switched to the alarm mode with the power supply voltage Vc of 1.6 V, the second step motor 20 always outputs the appropriate high-speed pulse P.
It is rotated at high speed by f3.

Next, the case where the power supply voltage Vc fluctuates will be described. First, a case where the power supply voltage Vc drops from 1.6V will be described. As described above, the second step motor 20 is driven by the normal pulse Pm5 in the normal time mode with the power supply voltage Vc1.6V. The second load compensation selection circuit 116 controls the second high speed pulse selection circuit 110 to select the high speed pulse Pf3. When the power supply voltage Vc gradually decreases from here, the driving force becomes weak with the normal pulse Pm5. Then, when the power supply voltage Vc falls below the minimum drivable voltage of 1.5 V of the normal pulse Pm5, the second step motor 20 cannot be driven by the normal pulse Pm5, and it is determined that the second detection circuit 121 cannot rotate. The second load compensation selection circuit 116 controls the second normal pulse selection circuit 109 according to this determination result to output the correction pulse Pmh to drive the second step motor 20 for correction, and to select and output the normal pulse Pm6 from the next time.
Here, the normal pulse Pm is switched from the normal pulse Pm5 to the normal pulse Pm6, but at this time, the second load compensation selection circuit 116 does not cause the second high-speed pulse selection circuit 112 to switch the high-speed pulse Pf, but the high-speed pulse Pf3. It remains selected. Therefore, when the normal time mode is switched to the alarm mode here, the second step motor 20 is rotated at high speed by the high speed pulse Pf3. From Table 4, the drivable voltage range of the high-speed pulse Pf5 is 1.0 to 2.2V, and the second step motor 20 can be sufficiently driven by the power supply voltage Vc of 1.5V. When the power supply voltage Vc further decreases, the driving force becomes weak even with the normal pulse Pm6. Then, when the power supply voltage Vc falls below the minimum drivable voltage 1.3V of the normal pulse Pm6, the second step motor 20 cannot be driven by the normal pulse Pm6, and it is determined that the second detection circuit 121 cannot rotate. The second load compensation selection circuit 116 controls the second normal pulse selection circuit 109 based on this determination result to correct the correction pulse Pm.
By outputting h, the second step motor 20 is corrected and driven, and the normal pulse Pm7 is selectively output from the next time. At the same time, the second load compensation selection circuit 116 controls the second high speed pulse selection circuit 110 to change the high speed pulse Pf to the high speed pulse Pf3.
To the high-speed pulse Pf4 for selection. Therefore, when the normal time mode is switched to the alarm mode here, the second step motor 20 causes the high-speed pulse Pf4.
Rotated at high speed by. From Table 4, high-speed pulse Pf
The drivable voltage range of No. 4 is 0.9 to 1.7 V and 1.3
The second step motor 20 can be sufficiently driven by the power source voltage Vc of V.

Next, the case where the power supply voltage Vc rises from 1.6 V will be described. The second step motor 20 is driven by the normal pulse Pm5 at the power supply voltage Vc of 1.6 V in the normal time mode. The second load compensation selection circuit 116 controls the second high speed pulse selection circuit 110 to select the high speed pulse Pf3. When the power supply voltage Vc gradually rises from here, the driving force increases with the normal pulse Pm5. On the other hand, the second load compensation selection circuit 116 controls the second normal pulse selection circuit 109 so that once every 100 times, the normal pulse Pm5 is smaller than the normal pulse Pm5 by one.
4 is selectively output. Then, the power supply voltage Vc becomes equal to or higher than the minimum drivable voltage 1.7 V of the normal pulse Pm4,
At this time, when the normal pulse Pm4 is selectively output, the second step motor 20 is driven by the normal pulse Pm4. At this time, at the same time, the second load compensation selection circuit 116 controls the second high speed pulse selection circuit 110 to generate the high speed pulse Pf.
Is switched from the high-speed pulse Pf3 to the high-speed pulse Pf2 for selective output. Therefore, when the normal time mode is switched to the alarm mode here, the second step motor 20 is rotated at high speed by the high speed pulse Pf2.
From Table 4, the driveable voltage range of the high-speed pulse Pf2 is 1.4.
The second step motor 20 can be sufficiently driven by the power supply voltage Vc of 1.7V to 2.8V. When the power supply voltage Vc further rises to 1.9 V and the normal pulse Pm4 is output 100 times, the second load compensation selection circuit 116 controls the second normal pulse selection circuit 109 to output the normal pulse Pm3 which is one smaller. . Then, the second step motor 20 is driven by the normal pulse Pm3 having the lowest drivable voltage of 1.9V. At this time, the second load compensation selection circuit 116 is the second high speed pulse selection circuit 110.
The selection of the high speed pulse Pf is not changed and the high speed pulse Pf2 is maintained. Therefore, when the normal time mode is switched to the alarm mode here, the second step motor 20 is rotated at high speed by the high speed pulse Pf2. From Table 4, the drivable voltage range of the high-speed pulse Pf2 is 1.4 to 2.8V, and the second step motor 20 can be sufficiently driven with the power supply voltage Vc of 1.9V.

Although the high speed rotation has been described above, the same operation is performed for the reverse rotation, and the second load compensation control circuit 116 controls the second high speed pulse selection circuit 110 in the same manner as the second reverse rotation pulse. It controls the selection circuit 111. The reverse rotation pulse Pb selected by the second reverse rotation pulse selection circuit 111 is the high speed pulse P described above.
The reverse rotation pulse Pb whose driveable voltage range is substantially equal to f is selected. That is, when the high speed pulse Pf1 is selected, the reverse pulse Pb1 is selected, when the high speed pulse Pf2 is selected, the reverse pulse Pb2 is selected, when the high speed pulse Pf3 is selected, the reverse pulse Pb3 is selected, and the high speed pulse Pf4 is selected. At this time, the reverse rotation pulse Pb4 is selected.

However, the second step motor 20 may not be driven by the normal pulse Pm for a long time depending on the usage condition. For example, you can adjust the time for a long time in the alarm mode, or leave the alarm in the alarm mode for 2 minutes.
5. This is the case where the hour hand 26 has been stopped with the alarm set time displayed all the time. In this case, at the end the normal pulse P
There is a possibility that the driving condition may have changed due to a change in the voltage of the electric double layer capacitor 70 because time has passed since the second step motor 20 was driven at m. In this case, if the high-speed pulse Pf or the reverse rotation pulse Pb is selected and output by the previous normal pulse Pm, it will go out of the drivable voltage range of the pulse and malfunction will occur, causing the clock to go crazy. In order to avoid this, the minute hand control circuit 117 is controlled by the malfunction prevention circuit 124, and when the second step motor 20 is not driven by the normal pulse Pm for a long time, the high speed rotation and the reverse driving are temporarily stopped,
16H which is the maximum speed that can be driven by multi-stage load compensation operation
By switching to the drive for performing the multi-stage load compensation operation by the normal pulse Pm at z, the optimum normal pulse Pm is selected under the driving condition at that time, and the normal pulse Pm is selected.
Appropriate high-speed pulse Pf or reverse rotation pulse Pb
Select again to restart the drive at high speed or reverse rotation.

The above circuit operation will be described in detail. The minute hand control circuit 117 outputs an abnormal pulse, that is, a high-speed pulse P
The signal H is output each time one pulse of the f or the reverse rotation pulse Pb is output. The malfunction prevention circuit 124 is the minute hand control circuit 1
The number of signals H is counted from 17. And signal H
When the number of 2000 becomes 2000, the malfunction prevention circuit 124 controls the minute hand control circuit 117 to interrupt the output of the high speed pulse Pf or the reverse rotation pulse Pb, and instead, the normal pulse Pm output from the second normal pulse selection circuit 109 is set at 16 Hz. Select and output. At the same time, the malfunction prevention circuit 124 controls the second load compensation control circuit to cause the second normal pulse selection circuit 109 to select the normal pulse Pm4 having a substantially intermediate magnitude among the normal pulses Pm1 to Pm8. Further, the malfunction prevention circuit 124 controls the second load compensation control circuit, and normally, if it can be driven by the same normal pulse Pm4 100 times as described above, the normal pulse Pm4 is switched to one smaller normal pulse Pm3 and selectively output. If it can be driven by, it is immediately switched to two small normal pulses Pm2 to be selectively output. If the normal pulse Pm2 cannot be driven, the normal pulse Pm4 or the normal pulse P is set under the driving conditions at that time.
m3 is the optimum normal pulse Pm, and therefore, as shown in Table 6, the suitable high speed pulse Pf and reverse rotation pulse Pb are the high speed pulse Pf2 and reverse rotation pulse Pb2. Therefore, the malfunction prevention circuit 124 is operated by the minute hand control circuit 117.
Is controlled to restart the driving with the high speed pulse Pf2 or the reverse rotation pulse Pb2. If the normal pulse Pm2 can be used for driving, the normal pulse Pm2 or the normal pulse Pm1 is the optimum normal pulse Pm under the driving conditions at that time.
As shown in, the suitable high speed pulse Pf and reverse rotation pulse Pb are the high speed pulse Pf1 and reverse rotation pulse Pb.
It is one. Therefore, the malfunction prevention circuit 124 controls the minute hand control circuit 117 to control the high-speed pulse Pf1 or the reverse rotation pulse Pb.
The driving at 1 is restarted.

If the normal pulse Pm4 output at the beginning cannot be driven, the correction pulse Pmh is output for correction driving, and next two large normal pulses Pm6 are output. If the normal pulse Pm6 can be used for driving, the normal pulse Pm6 or the normal pulse Pm5 is the optimum normal pulse Pm under the driving conditions at that time. Therefore, as shown in Table 6, the suitable high speed pulse Pf and reverse pulse Pb are the high speed pulse Pf3. And the reverse pulse Pb3. Therefore, the malfunction prevention circuit 124 controls the minute hand control circuit 117 to restart the driving with the high speed pulse Pf3 or the reverse rotation pulse Pb3. If the normal pulse Pm6 cannot be used for driving, the normal pulse Pm7 or the normal pulse Pm8 is the optimum normal pulse Pm under the driving conditions. Therefore, as shown in Table 6, the suitable high speed pulse Pf and reverse pulse Pb are the high speed pulse Pf4. And the reverse pulse Pb4. Therefore, the malfunction prevention circuit 124 controls the minute hand control circuit 117 to restart driving with the high speed pulse Pf4 or the reverse rotation pulse Pb4. Needless to say, the high-speed pulse Pf is small by the amount driven by the normal pulse Pm, and the reverse pulse Pb is output as an extra pulse so that the time does not change.

From the minute hand control circuit 117, the normal pulse P
The signal J is output every time one pulse of m is output. The malfunction prevention circuit 124 measures the time from when the signal J is output from the minute hand control circuit 117 to when the next signal J is output. If the time during which the signal J is not output exceeds 1 hour, the malfunction prevention circuit 124 controls the minute hand control circuit 117 and the second load compensation control circuit to interrupt the driving of the next high speed pulse Pf and reverse rotation pulse Pb. , As described above, the optimum normal pulse P is obtained by the multi-stage load compensation operation.
After selecting m and further selecting the high-speed pulse Pf and the reverse rotation pulse Pb, driving with the high-speed pulse Pf and the reverse rotation pulse Pb is started. As described above, the voltage drop due to the continuous drive of the high-speed pulse Pf and the reverse pulse Pb and the voltage fluctuation due to the charging / discharging of the electric double layer capacitor 70 while the normal pulse Pm is not output for a long time are dealt with.

[0054]

As is apparent from the above description, according to the present invention, even in an electronic timepiece having a power supply voltage fluctuating, a drivable voltage corresponding to the lowest drivable voltage of the selected normal pulse is performed by performing a multi-stage load compensation operation. High-speed rotation and reverse rotation are possible by selectively outputting a non-normal pulse with a range, and even an electronic timepiece with a voltage fluctuation such as a solar timepiece can have an alarm function and a chrono function, and the product range is widened. It can be greatly expanded.
That is, even a step motor such as the third step motor 30 that is normally stopped and cannot perform the multi-step load compensation operation and the driving condition is unknown, moves the hand while always performing the multi-step load compensation operation like the first step motor 10. The driving condition can be estimated by the normal pulse of the other step motor, and the optimum non-normal pulse can be determined and driven reliably. Therefore, it is possible to provide a solar clock or the like having a high-speed rotation function such as chrono. Further, when the abnormal pulse is determined by the normal pulse in the same step motor like the second step motor 20, it can be applied to the step motor having a load fluctuation because not only the voltage but also the load condition is taken into consideration. Therefore, there is an effect that it is possible to provide a solar clock or the like which can reliably drive the hour and minute hands having a calendar load at high speed or reverse rotation and has an alarm function. In the present embodiment, the rechargeable pointer type electronic timepiece that exhibits the most remarkable effect is described.Of course, even in a pointer type electronic timepiece that uses a normal silver battery or a lithium battery as a power source, the voltage change and the load change are not caused. It is clear that it has a similar effect.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electronic timepiece according to an embodiment of the present invention.

FIG. 2 is a front view showing the structure of the electronic timepiece according to the embodiment of the invention.

FIG. 3 is a waveform diagram of normal pulses Ps1 to Ps8 according to an embodiment of the present invention and a conventional example.

FIG. 4 is a waveform diagram of a reverse pulse Pb according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional solar clock.

FIG. 6 is a block diagram showing the periphery of the first load compensation circuit of the electronic timepiece according to the embodiment of the present invention.

[Explanation of symbols]

 10 First Step Motor 20 Second Step Motor 30 Third Step Motor 70 Electric Double Layer Capacitor 103 First Normal Pulse Generation Circuit 104 Second Normal Pulse Generation Circuit 105 Second High Speed Pulse Generation Circuit 106 Second Reverse Pulse Generation Circuit 107th Three high speed pulse generation circuit 108 First normal pulse selection circuit 109 Second normal pulse selection circuit 110 Second high speed pulse selection circuit 111 Second reverse pulse selection circuit 112 Third high speed pulse selection circuit 114 First load compensation control circuit 116 Second Load compensation control circuit 119 First detection circuit 116 Second detection circuit

Claims (5)

[Claims] 1. A power supply means, a first step motor, a normal pulse generating means for generating a plurality of normal pulses having different driving forces for driving the first step motor, and one of the plurality of normal pulses. A normal pulse selection circuit for selectively outputting the rotation of the first step motor,
An electronic timepiece having a detection means for detecting non-rotation and a load compensation control circuit for determining a selection condition of the normal pulse selection circuit according to a detection signal of the detection means. And a non-normal pulse selection circuit for selecting and outputting one of the plurality of non-normal pulses, which generates a plurality of non-normal pulses having different driving forces for driving An electronic timepiece, wherein a selection condition of the circuit is determined by the load compensation control circuit. 2. The electronic timepiece according to claim 1, wherein the first step motor and the second step motor are the same step motor. 3. The electronic timepiece according to claim 1, wherein the abnormal pulse generating means is a high speed pulse generating means. 4. The electronic timepiece according to claim 1, wherein the abnormal pulse generating means is a reverse pulse generating means. 5. The electronic timepiece according to claim 1, wherein the power supply unit is a rechargeable power supply unit.