JPH089786Y2 - Data transfer interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a data transfer interface circuit used when data is transferred between a plurality of electronic circuits each having a different operating voltage.

[Prior Art] In recent years, personal schedule data, telephone number data with name and address with telephone number, business card data including company name, free data such as arbitrary comments to be stored, etc. A large number of electronic devices such as electronic notebooks that are stored and called and used as needed are commercialized. All of these electronic devices have a data memory inside, and some of them have a data communication function of transmitting and receiving data between the data memories by connecting a plurality of electronic devices. .

In an electronic device having the above data communication function, for example, by inputting data from a large-sized device side where data key input operation is easy, and then transferring the data to a small-sized portable device side. , Data input can be simplified and used effectively.

[Problems to be Solved by the Invention] In the electronic device having the data communication function, the signal voltage level V ₀ of the large electronic device on the transmitting side and the signal voltage level V ₁ of the small electronic device on the receiving side are different. In some cases, in order to compensate for this, an interface circuit that converts the signal voltage of data transferred in the middle of the transfer path is used during data transfer. For example, when the signal voltage level is V ₀ > V ₁ , this interface circuit is equipped with a power source of voltage V ₀ by a battery or the like, and receives the data of the potential difference V ₀ sent from the electronic device on the transmission side. The voltage is converted into the data of the potential difference V ₁ according to the electronic device on the side and output.

Conversely, when sending a signal (potential difference V ₁ ) from a small electronic device to a large electronic device, the signal with the potential difference V ₁ is leveled up by the power supply of the interface circuit itself and converted into a signal with the potential difference V _0. And then send it.

Then, if the power supply voltage of the interface circuit itself drops below the reference value or if the battery that serves as the power supply comes out of its storage position, the power from the input / output terminals of the small electronic device on the receiving side Inflow current is generated, or the output data of the interface circuit for the data from the large electronic device on the transmitting side changes near the input threshold level of the small electronic device on the receiving side. There is a possibility that the stored data contents may be erroneously changed or destroyed.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a data transfer interface circuit which does not erroneously change or destroy stored data of an electronic device connected thereto by a change in power supply voltage. To aim.

[Means and Actions for Solving the Problem] The present invention is to constantly operate the power supply while converting the signal voltage level of the data output from the electronic circuit on the transmitting side into the signal voltage level of the data on the electronic circuit on the receiving side. Voltage level of the operating power supply is detected, and when the voltage level of the operating power supply falls below a specific value, transmission data from the electronic circuit on the transmitting side is cut off to prevent an inflow current of the electronic circuit on the receiving side. Thus, even if the power supply voltage of the interface circuit changes, the stored data of the connected electronic circuit will not be erroneously changed or destroyed.

[Embodiment] An embodiment in which the present invention is applied to an interface circuit used when data is transferred between an electronic notebook and an electronic wristwatch having an electronic notebook function will be described below with reference to the drawings.

1 and 2 show the external configuration of an electronic wristwatch, and 11 is a wristwatch case. This watch case 11 is
For example, it is made of metal such as stainless steel or synthetic resin, and a watch glass 12 is mounted on the upper surface thereof as an exterior, and a dot matrix liquid crystal display 13 is arranged on the lower surface side thereof. Further, a connector portion 14 and a push button switch S1 which will be described later are arranged on the right side surface of the wristwatch case 11, and push button switches S2 to S4 are arranged on the left side surface thereof. Input key group for inputting
15 are provided. The input key group 15 is provided with a SET key 15a for setting the input data, in addition to the character keys for inputting data with alphabets, numbers and symbols. The connector section 14 is for performing data communication with other electronic devices described later,
Three electrically conductive pins 17, which will be described later, which serve as connection terminals, are provided in the elongated holes 16 each having a semicircular shape at both ends.

FIG. 3 shows an electronic notebook 21 and an interface circuit 26 connected to the connector section 14. Here, the electronic notebook 21 is assumed to have both a calculator and a notebook function for storing and displaying free data such as telephone number data, schedule data and arbitrary comments. Electronic notebook 21
The left case 21a and the right case 21b are connected and integrated, and are of a size that can be held in a hand when folded, and FIG. 3 shows the opened state. On the left case 21a of the electronic notebook 21, a dot matrix liquid crystal display unit 22 and numerical / arithmetic operation keys 23 for numerical value input and calculation
And the right case 21b is provided with a character key 24, such as an alphabet key or a kana character key, for inputting characters. Telephone number data, schedule data, and free data are input by using the numerical value / four arithmetic keys 23 and the character keys 24. Further, a connector portion 21c is provided on the upper side surface portion of the left case 21a, and is connected to the interface circuit 26 via the cable 25.
The interface circuit 26 appropriately converts the voltage of the data signal sent via the cable 25, and the cable 27 to which the data signal of the converted voltage value is sent is provided with a jack (described later) provided at its tip. Is connected to the connector portion 14 of the wristwatch case 11.

Further, when sending data from the wristwatch to the electronic notebook 21, the signal sent via the cable 27 is converted into the voltage of the electronic notebook 21 by the interface circuit 26 and sent to the electronic notebook 21 via the cable 25. It is what is done.

FIG. 4 is a diagram showing a detailed connection structure of the connector portion 14 of the wristwatch case 11.

In the figure, the elongated hole 16 is formed by a resin pipe 31 having a bottom, and the pipe 31 is embedded in the side surface of the wristwatch case 11, and the pin 17 is loosely inserted into the bottom portion 31a thereof. This pin 17 has a flange 17a at one end on the front side of the pipe 31.
Is formed, and the spring 32 is disposed between the flange 17a and the bottom 31a of the pipe 31 while being inserted into the pin 17 body. The pin 17 penetrates the waterproof packing 33 on the lower surface side of the pipe 31, and a step portion 17b is provided in the vicinity of the other end to engage the pin removal preventing member 34, while the other end surface 17c electrically connects with an electronic circuit described later. It faces the fixed terminal 35 connected. When nothing is inserted in the long hole 16 of the pipe 31, the elasticity of the spring 32 causes the flange 17a to move to the wristwatch case 1.
1 and the outer peripheral surface of the pipe 31, the other end surface 17c of the pin 17 is in a state of facing away from the fixed terminal 35, the jack 36 is inserted into the long hole 16 of the pipe 31 as illustrated. In the state, the jack terminal 36a pushes the pin 17 to the left in the drawing, the other end surface 17c comes into contact with the fixed terminal 35, and the electronic circuit and the cable 27 are electrically connected.

37 is the back cover of the watch case 11, 38 is the back cover 37
This is a waterproof packing that maintains an airtight state between the watch case 11 and the watch case 11.

With the above-mentioned structure, the structure of the electronic circuit provided in the wristwatch case 11 is as shown in FIG. In the figure, reference numeral 41 denotes an oscillating unit, which oscillates a reference frequency pulse serving as a reference for various operations and timing. The reference frequency pulse oscillated by the oscillating unit 41 is divided by the frequency dividing / timing signal unit 42 into a timing signal, which is sent to the control unit 43 composed of a CPU. The control unit 43 operates the other circuits in accordance with the timing signal from the frequency division / timing signal unit 42 and the key input signal from the key input unit 44 including the push button switches S1 to S4 and the input key group 15. For control, the ROM 45 storing a microprogram for operation control is addressed to read the microprogram, and data is input / output to / from the RAM 46 storing various data by addressing. The control unit 43 is a communication circuit unit.
Buzzer drive circuit while sending and receiving data to and from 47
The drive signal is output to 48 and the display data is output to the display control unit 49. The buzzer drive circuit 48 drives the speaker 50 to emit sound according to the drive signal from the control unit 43. Display control unit
The control unit 49 decodes the display data sent from the control unit 43 to obtain a drive signal, and drives and controls the display unit 51 including the liquid crystal display 13 by this drive signal to display and output the time, communication data and the like.

The communication circuit section 47 is connected to the interface circuit 26 via the connector section 14 and transmits / receives data to / from an external device 52 such as the electronic notebook 21. External device 52
Although not shown, the CP is similar to the circuit configuration of FIG.
U, ROM, RAM and the like, and the data sent from the external device 52 via the interface circuit 26 and the connector unit 14 is received by the communication circuit unit 47, and then the control unit 43.
Is stored in RAM 46 by.

Next, the circuit configuration in the interface circuit 26 will be described with reference to FIG.

In the figure, the communication circuit section 47 on the timepiece side and the electronic notebook 21 are connected via an interface circuit 26 by three data lines L1 to L3. Of these, the data line L1 is a common data line of GND level which is the reference potential, "0V", and the data line L2 is from the electronic notebook 21 toward the communication circuit section 47.
The data line L3 is a data line to which data is transferred from the communication circuit unit 47 toward the electronic notebook 21. The electronic notebook 21 operates with a power supply voltage of "-5V", and outputs a data clock signal having a peak value of the same voltage on the data line L2. The data output from this electronic notebook 21 is converted into a voltage conversion unit 62 via an input buffer 61 in the interface circuit 26.
To the connector section 14 and the communication circuit section 47 through the output buffer 63 after being transformed into “−3V”.

On the other hand, the communication circuit section 47 is the wristwatch case 11 shown in FIG.
Like the other circuits, it operates by the power supply voltage of "-3V", and outputs the data clock signal having the peak value of the same voltage on the data line L3. The data output from the communication circuit unit 47 is sent to the voltage conversion unit 65 via the input buffer 64 in the interface circuit 26 via the connector unit 14, and after being transformed into “−5V”, is output. The electronic notebook 21 is reached via the buffer 66.

Further, 67 is a voltage detection unit, which is a power supply battery for the interface circuit 26 in which the positive terminal is connected to the data line L1.
It is connected to both the positive and negative terminals of 68 and detects the generated voltage, and the voltage value is a predetermined value, for example, the electronic notebook 21 that normally operates at `` -5V '' is `` -3.5V. When the voltage drops to less than −3.5V, the detection signals are output to the output buffers 63 and 66, respectively. . The negative terminal of the power battery 68 is also
The input buffer 61, voltage conversion units 62 and 65, constant voltage circuit 69
Connected to. The input buffer 61 is connected to the data line L1 and is composed of a C-MOS inverter like the input buffer 64 described later.

The output buffer 63 has a circuit configuration similar to that of the output buffer 66, and is composed of _four FETs Q _{1 to} Q ₄ . The data from the voltage conversion unit 62 via the data line L2 is given to the gates of the FETs Q ₁ and Q ₂ , and the detection signal from the voltage detection unit 67 is given to the gates of the FETs Q ₃ and Q ₄ . The sources of FETs Q ₁ and Q ₄ are both connected to data line L 1. The drain of the FETQ ₁ is connected to the drain of the FETQ _{2 and} the drain of the FETQ ₄ , and is also directly connected to the data line L2 as an output terminal. The source of the FETs Q ₂ is connected to the drain of the FETs Q _3, the constant voltage circuit 6 to the source of the FETs Q ₃
The constant voltage of "-3V" from 9 is given.

The constant voltage circuit 69 is provided with "-
The output buffer 63, the voltage conversion unit 62, the input buffer 64, and the voltage conversion unit described above by converting the voltage of “5V” into the constant voltage “−3V”.
Supply to 65.

The input buffer 64 is a C-MOS inverter having the same circuit configuration as the input buffer 61 as described above, and is composed of two diodes D ₁ and D ₂ , a resistor R and two FETs Q ₅ and Q ₆ . Voltage detecting unit 67, the data from the connector 14 via a data line L3 is the anode of the diode D ₂ through the anode and the resistor R of the diode D _1, it is applied to the gate of the FETs Q ₅ and Q _6. The cathodes of the diodes D ₁ and D ₂ and the source of the FET Q ₅ are connected to the data line L1 and the FET Q ₅
The drain of is connected to the drain of FET Q ₆ , and is also directly connected to the data line L 3 as an output terminal. FE
The source of the TQ ₆ constant voltage "-3V" from the constant voltage circuit 69 is applied.

In the above configuration, when the power supply battery 68 generates the predetermined voltage, that is, "-5V", the voltage detection unit
67 detects this and sets the detection signals to the output buffers 63 and 66 to the "H" level. This allows the output buffer 63
FETQ ₃ is turned on, FETQ ₄ is turned off, and the output buffer 63 as a whole functions as an inverter.When the data whose peak value has been converted to “−3V” is sent from the voltage conversion unit 62, That is, when data is being transferred from the electronic notebook 21 to the communication circuit section 47, the data is inverted and sent to the communication circuit section 47 via the connector section 14. In this case, since the data sent from the electronic notebook 21 side has already been once inverted in the input buffer 61 by the operation described later, the output of the output buffer 63 has a correct data waveform.

Further, when the generated voltage of the power supply battery 68 becomes lower than "-5V" and becomes "-3.5V", the voltage detection unit 67 detects this and outputs the detection signal to the output buffers 63 and 66 to "L". "Set as a level. As a result, the FETQ ₃ of the output buffer 63 is turned off and the FETQ ₄ is turned on, and regardless of the data from the voltage conversion unit 62, the outputs to the connector unit 14 and the communication circuit unit 47 are all "0V", and the voltage conversion is performed. Data from the unit 62 is cut off.

The above operation is the same in the output buffer 66,
When the power supply battery 68 generates a voltage of "-3.5V" or higher, the peak value is converted to "-3.5V" by the "H" level detection signal from the voltage detector 67. The data from the conversion unit 65 is inverted and sent to the electronic notebook 21. Further, when the generated voltage of the power supply battery 68 is lower than “−3.5V”, the electronic notebook 21 is irrespective of the data from the voltage conversion unit 65 due to the “L” level detection signal from the voltage detection unit 67. The output from the voltage converter 65 is cut off by setting the output to "0V".

Further, in the input buffer 64, the cathodes of the diodes D ₁ and D ₂ are connected to the “0 V” level data line L _{1 as} described above. Therefore, even if the power battery 68 may come out of its storage position,
The current from the power supply battery of the communication circuit unit 47 flowing from the communication circuit unit 47 through the connector unit 14 is FE in the input buffer 64.
There is almost no inflow into TQ ₅ , Q _6, and even if there is, incorrect data caused by the inflow current is output buffer.
By the operation described above at 66, it is surely blocked and is not sent to the electronic notebook 21.

The operation of the input buffer 64 is similar to that of the input buffer 61. Even if the power supply battery 68 may come out of its storage position, the power supply battery of the electronic organizer 21 flowing from the electronic organizer 21 may be removed. The current of the input buffer
It rarely flows into the FET (not shown) in 61, and even if there is, incorrect data caused by the inflow current is reliably cut off by the above operation in the output buffer 63,
It is not sent to the communication circuit section 47.

In the above embodiment, the electronic notebook 21 and the electronic watch case are used.
Although the interface circuit 26 using a battery power source when connecting 11 and 11 has been described, the case where a personal computer as shown in FIG. 7 is connected instead of the electronic notebook will be described next.

In FIG. 7, 70 is a personal computer,
The personal computer 70 includes a main body device 71 having a CRT display, a keyboard 72, and a floppy disk device 73 as an external storage device, and a cable 74.
Is connected to an interface circuit 75 not shown here.

The circuit configuration of the interface circuit 75 will be shown below with reference to FIG.

Since the basic circuit configuration of this figure is the same as that shown in FIG. 6, the same parts are designated by the same reference numerals and the description thereof is omitted.

In the figure, reference numeral 76 is a plus power supply unit that generates a power supply voltage at "+ 12V", the minus side terminal is connected to the data line L1, and the generated voltage is the input buffer 61 and the voltage conversion unit 62.
And to the voltage detector 67. Also, 77 is "-12V".
Is a negative power supply unit that generates a power supply voltage, and the positive terminal is connected to the data line L1, and the generated voltage is a voltage detection unit 67, an input buffer 61, a voltage conversion unit 62, a voltage conversion unit 65, and a constant voltage. It is supplied to the circuit 69.

The personal computer 70 is operated by an AC power supply, and outputs the peak value data of "-12V" on the data line L2. The data output from the electronic organizer 21 is sent to the voltage conversion unit 62 via the input buffer 61 in the interface circuit 26, and after being transformed into “−3V”,
It reaches the connector unit 14 and the communication circuit unit 47 via the output buffer 63.

On the other hand, the communication circuit section 47 is the wristwatch case 11 shown in FIG.
Like the other circuits in the above, it operates by the power supply voltage of "-3V", puts the peak value data of the same voltage on the data line L3, and outputs it. The data output from the communication circuit unit 47 is sent to the voltage conversion unit 65 via the input buffer 64 in the interface circuit 26 via the connector unit 14, and here, "-
After being transformed into “12V”, it reaches the personal computer 70 via the output buffer 66.

The voltage detection unit 67 detects the voltage generated by each of the positive power supply unit 76 and the negative power supply unit 77, and outputs a detection signal when the voltage value falls below a specified value.
Output to 6 respectively.

The constant voltage circuit 69 is provided with "-
The voltage of "12V" is converted into a constant voltage "-3V" and supplied to the output buffer 63, the voltage conversion unit 62, the input buffer 64, and the voltage conversion unit 65 described above.

In the above-mentioned configuration, the plus power source unit 76 and the minus power source unit 77 have their predetermined voltages, that is, "+ 12V" and "-12".
When "V" is generated, the voltage detection unit 67 detects this and sets the detection signals to the output buffers 63 and 66 to "H" level. This causes the output buffer 63 to function as an inverter, and when the data whose peak value is converted to “−3V” is sent from the voltage conversion unit 62, that is, from the personal computer 70 to the communication circuit unit 47. When data is being transferred in the direction, the data is inverted and sent to the communication circuit section 47 via the connector section 14. In this case, the data sent from the personal computer 70 is already inverted in the input buffer 61 by the operation described later, so that the output of the output buffer 63 has a correct data waveform.

In addition, when the voltage generated by the positive power supply unit 76 and the negative power supply unit 77 is lower than “+ 12V” and “−12V” and becomes equal to or lower than a predetermined specified value, the voltage detection unit 67 detects this and outputs the output buffer. The detection signals to 63 and 66 are set to "L" level. As a result, the output buffer 63 sets all the outputs to the connector unit 14 and the communication circuit unit 47 to “0V” regardless of the data from the voltage conversion unit 62, and shuts off the data from the voltage conversion unit 62.

The above operation is the same in the output buffer 66,
When the power supply battery 68 generates predetermined "+ 12V" and "-12V", the peak value is converted to "-12V" by the output signal of "H" level from the voltage detection unit 67. The data from 65 is inverted and sent to the personal computer 70. Further, when the generated voltages of the positive power supply unit 76 and the negative power supply unit 77 are lower than the predetermined voltage, the voltage conversion unit 65 outputs the “L” level detection signal from the voltage detection unit 67. Regardless of the data, the output from the voltage conversion unit 65 is cut off by setting the output to the personal computer 70 to "0V".

Further, in the input buffer 64, the positive power supply unit 7
6. Even if at least one of the negative power supply 77 suddenly drops the generated voltage for some reason, the communication circuit 47 flows from the communication circuit 47 through the connector 14.
The current from the 47 power supply battery is FET Q ₅ and Q in the input buffer 64.
It rarely flows into _6, and even if there is, erroneous data caused by the inflow current is reliably cut off by the above-mentioned operation in the output buffer 66 and is not sent to the personal computer 70.

The operation of the input buffer 64 is similar to that of the input buffer 61. Even if the power supply battery 68 comes off from its storage position, the power supply battery of the personal computer 70 flows from the personal computer 70. The current of the FET in the input buffer 61 (not shown)
In most cases, the erroneous data caused by the inflow current is certainly cut off by the output buffer 63 by the above operation and is not sent to the communication circuit section 47 even if there is.

In the above embodiment, the interface circuit for transferring data between the wristwatch having the electronic notebook function and the electronic notebook, or the personal computer is shown, but the electronic device to be connected is not limited to these. Of course.

Although the interface circuit is provided separately from the device for transferring data, it may be provided in each device such as an electronic notebook, a wristwatch, and a personal computer.

Further, in the case of a wristwatch and an electronic notebook, a wristwatch and a personal computer, etc., data transfer with different power supply voltages is performed by respective interfaces. However, a large number of power supply voltages are provided in one interface circuit, and selective switching is performed by switching switches or the like. May be done.

[Effect of the Invention] As described in detail above, according to the present invention, the signal voltage level of the data output from the electronic device on the transmission side is constantly converted into the signal voltage level of the data on the electronic device on the receiving side. The voltage level of the power supply is detected, and when the voltage level of the operating power supply falls below a specific value, the transmission data from the electronic device on the transmission side is cut off and the inflow current of the electronic device on the reception side is prevented. Thus, it is possible to provide a data transfer interface circuit that does not erroneously change or destroy the stored data of the connected electronic device even if the power supply voltage of the interface circuit changes.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a plan view showing the external configuration, FIG. 2 is a side view of the same, and FIG. 3 is a perspective view showing the external appearance of an external electronic notebook. FIG. 4 is a sectional view showing a specific structure of the connector portion, FIG. 5 is a block diagram showing a configuration of an electronic circuit, FIG. 6 is a block diagram showing a detailed circuit configuration of the interface circuit of FIG. 5, and FIG. FIG. 8 is a diagram showing another example of the connection device, and FIG. 8 is a block diagram showing a detailed circuit configuration of an interface circuit used in the connection device of FIG. 11 ... Watch case, 12 ... Watch glass, 13 ... Liquid crystal display, 14 ... Connector section, 15 ... Key input group, 15a ... Set key, 16 ... Slot, 17 ... Pin, 21 ... Electronic notebook, 22
... Liquid crystal display, 23 ... Numerical / arithmetic key, 24 ... Character key, 25, 27, 74 ... Cable, 26, 75 ... Interface circuit, 31 ... Pipe, 32 ... Spring, 33, 38 ... Waterproof packing, 34
… Pin removal prevention member, 35… Terminal, 36… Jack, 37… Back cover, 41… Oscillation circuit, 42… Dividing / timing signal part, 43…
Control unit, 44 ... Key input unit, 45 ... ROM, 46 ... RAM, 47 ... Communication circuit unit, 48 ... Buzzer drive circuit, 49 ... Display control unit, 50 ... Speaker, 51 ... Display unit, 52 ... External device, 61 , 64 ... Input buffer, 62, 65 ... Voltage converter, 63, 66 ... Output buffer, 67 ...
Voltage detector, 68 ... Power battery, 69 ... Constant voltage circuit, 70 ... Personal computer, 71 ... Main device 71, 72 ... Keyboard
72, 73 ... Floppy disk device, 76 ... Plus power supply unit,
77 ... Negative power supply.

Claims (1)

[Scope of utility model registration request] 1. A data transfer interface circuit, which is connected between electronic circuits that output transfer data having different voltages, and relays the transfer data, and a voltage generating source that generates the respective different voltages; Voltage level converting means for converting the signal voltage level of the data supplied with the generated voltage and output from the transmitting side electronic circuit into the signal voltage level of the receiving side electronic circuit, and the voltage level generated from the voltage generating source. Voltage detecting means for detecting whether or not the voltage level is within a predetermined level range, and from the electronic circuit on the transmitting side when the voltage level is detected by the voltage detecting means not within the predetermined level range. 2. A data transfer interface circuit, comprising: