JPH0897812A - Scrambler and descrambler - Google Patents

Abstract

PURPOSE: To turn a selection circuit and a loop back circuit to a small scale and to provide inexpensive system constitution by utilizing the relation of the byte number of a header and the bit number of delay data and performing a loop back operation in the entire shift register. CONSTITUTION: The shift registers(SRs) 7 and 9 for respectively storing 40 bits for five stages of 8-bit parallel data(PD) and 3 bits for one stage of 3-bit PD are provided. A selector 11 respectively selects and outputs the output of the fifth stage of the SR 7 to the first stage of the SR 7 at the time of header transmission(HT) and the 8-bit PD to the first stage of the SR 7 at the time of payload transmission(PT). Also, the selector 13 respectively selects and outputs the output of the SR 9 to the SR 9 at the time of the HT and 3-bit data in the output of the fifth stage of the SR 7 to the SR 9 at the time of the PT. Further, the selector 1 respectively selects and outputs unscrambled data at the time of the HT and the data scrambled by using the delay data of the SRs 7 and 9 at the time of the PT. Thus, the need of the selector and the loop back circuit for holding the data of F.F or the like is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scrambler and a descrambler, and more particularly to a scrambler and a descrambler which can be implemented at a small scale and at a low cost by reducing the circuit scale.

[0002]

2. Description of the Related Art FIG. 5 shows a principle diagram of scrambling and descrambling using a generator polynomial X ⁴³ +1 based on I.432 according to CCITT recommendations. The data transmitted from the transmission side (left side of the drawing) is obtained by exclusive-ORing the data 43 bits before output from the shift register section 25a having a shift register of 43-bit length with the exclusive OR output section 23a. Sent after. In order to delay the output to the exclusive OR output unit 23a by 43 bits, it is known that, for example, 43 flip-flops are connected in series (for convenience of the following description, the flip-flops are provided. The unit of the number of serially connected data holding means such as is a stage, for example, four flip-flops.
The three connected in series is called 43 stages). The contents of the data that has been subjected to such operations are different from the original data,
Since it becomes difficult to decipher, there is an effect that the confidentiality of information is maintained even when a malicious third party eavesdrops on the data. In addition, the signal sequence is randomized and 0 of the information bit sequence is
Alternatively, the continuous occurrence of 1 can be suppressed, so that there is an effect that it is possible to improve transmission performance such as suppression of pattern jitter and retention of timing information. The operation of encrypting the data to be transmitted in this way is called scrambling, and the device for that purpose is called a scrambler. On the other hand, on the receiving side, as an operation for restoring the encrypted data to the original form, the received data is delayed by the 43-bit length shift register 29 and the exclusive OR output unit 27 Take an exclusive OR. By the above operation, the original data is restored by inverting the scramble bit added as the exclusive OR to the original data at the time of scrambling. Such an operation of decryption (descrambling) is called descrambling, and a device therefor is called a descrambler.

Here, an actual ATM (Asynchronous Tran
sfer Mode; Asynchronous transfer mode) In communication, data is transmitted and received in units of 53-byte packets called cells. The cell is composed of a portion called a header of the first 5 bytes in which the transmission destination of the cell, management information and the like are written, and a portion called a payload of 48 bytes in which the communication content (communication data portion) that follows is written. Of these, the CCITT recommendation also specifies that the header part is not scrambled. Therefore, in addition to the basic operation shown in FIG. 5, in order to scramble only the payload part excluding the header, Action is required. That is, it is necessary to be a circuit that performs a selective operation of transmitting transmission data without scrambling at the time of header transmission, and scrambling transmission data at the time of payload transmission using the delay data from the shift register.
FIG. 6 shows a scrambler which performs the above-mentioned operation.
The description will be given below. Since the circuit configuration and operation of the descrambler are almost the same as those of the scrambler, the description thereof will be omitted.

The scrambler shown in FIG. 6 selects the output of the input line 31 or the output of the exclusive OR circuit 3 by the control signal 5 and outputs it to the output line 31.
And holds 43 bits of data for controlling whether or not the output of the selector 1 is input by the control signal 5.
The 3-bit shift register 25a and the exclusive OR of the 43-bit shift register 25a and the signal line 31 (EX
And an exclusive OR circuit 3 for calculating OR) and outputting it to the selector 1. Here, the portion corresponding to the above-mentioned exclusive OR output unit 23a is 23b (dotted line portion in the drawing). Next, the operation of this scrambler will be described.
The shift register 25b has a register having a length of 43 bits, does not perform the shift operation when the selector 1 selects the signal line 31, and conversely the selector 1 selects the output of the exclusive OR circuit 3. The control signal 5 is controlled so that the shift operation is performed during the shift. When the header portion of the cell data is sent, the control signal 5
As a result, the selector 1 selects the signal line 31, and the header is transmitted as it is to the receiving side through the signal line 31. At this time, since the shift register 29 does not perform the shift operation, the payload information stored inside is retained as it is. When the first payload bit arrives after the header has been transmitted, the control signal 5 changes, the selector 1 switches, the output of the exclusive OR circuit 3 is selected, and the shift operation of the shift register 29 starts. The data output from here is exclusive ORed with the data on the signal line 31. The data in which the payload portion is scrambled in this manner is transmitted from the signal line 33.

In the above description, the conventional technique has been described for serial communication for the sake of simplicity. However, in actual ATM communication, data is converted from serial to 8-bit parallel inside the transmitter and the receiver. It is generally processed. Therefore, the case of 8-bit parallel will be described below. FIG. 7 shows a circuit for performing the function of the scrambler described in FIG. 6 as it is in the case of 8-bit parallel. The scrambler shown in FIG. 7 selects the output of the input line 19 or the output of the exclusive OR circuit 3 by the control signal 5 and controls the selector 1 which outputs to the output line 21 and the output of this selector 1. A 40-bit shift register 35 for holding 40-bit (8 bits × 5 stages) data by the signal 5 and an output of the 40-bit shift register 35 for upper 3 bits (3 bits × 1 stage) by the control signal 5. A 3-bit shift register 37 for holding data and this 40-bit shift register 3
5 and the exclusive OR circuit 3 for calculating the exclusive OR (EXOR) of the signal line 31 and outputting it to the selector 1.

As described above, since it is necessary to scramble only the payload part while avoiding the header part, the shift operation of the shift register must be stopped while the header is being transmitted. How the shift operation is stopped will be described with reference to FIG.

FIG. 8 shows a circuit for storing 1 bit which is a component of the shift register. This one
The bit storage circuit includes a flip-flop 41 that holds the input 1-bit data, and the flip-flop 4
It has a selector 39 which selects the output of 1 and the output from the preceding flip-flop or the like by the control signal 5 and outputs it to the flip-flop 41. Control signal 5 is selector 9
The control signal 5 selects the input of the preceding stage or the output of the flip-flop 41. Eight such circuits are arranged in parallel to form a 1-byte shift register, and five circuits are arranged in series to form a 5-byte shift register 35 as a whole. Further, three are arranged in parallel to form a 3-bit shift register 37.
When the header arrives and the data is not input to the flip-flop and the data stored up to the previous clock is held as it is, the output of the flip-flop 41 is selected by the selector and the data loops back to restore the original data. Return to the flip-flop (hereinafter referred to as loopback operation). On the other hand, in order to shift the data to the next-stage flip-flop upon arrival of the payload, the selector selects the signal line 43 to input new data and outputs the stored data to the next flip-flop.

When the 8-bit data output from the selector 1 is output to the exclusive OR circuit 3 through the circuit composed of these shift registers 35 and 37, the respective data of 8 bits are stored in the selector 1. A delay of 43 bits occurs as compared with the output equal data. These data are scrambled by taking the exclusive OR of the data input from the signal input line 19. The selection operation of the selector 1 and the shift operations of the shift registers 35 and 37 are the same as those in the conventional example. That is, when the selector 1 selects the input data of the signal input line 19, the shift operation of both shift registers is stopped, and when the selector selects the exclusive OR circuit 3, the shift operation is performed. These operations are controlled by the control signal 5.

Next, the detailed operation of the entire scrambler will be described with reference to FIG. For convenience of description, the header part (5 bytes) of the cell is read from the first bit to header bit 1, header bit 2, ..., Header bit 4
Set to 0. Also, the payload part (48 bytes) of the cell is defined as payload bit 1, payload bit 2, ..., Payload bit 384 from the first bit. Also, 40
Of the 8-bit × 5-stage register of the bit shift register 35, the 1-stage register, the 2-stage register,
..., 5-stage register.

(1) Header bit 1, header bit 2, ..., Header bit 8 (referred to as the first word), which is the header portion of the cell, are input in order from the lower input line of the input line 19. Header bits 1, header bits 2, ..., Header bits 8 are sequentially output from the upper portion of the output line 21 without being scrambled.

(2) Similarly, header bit 9, header bit 10, ..., Header bit 16 (second word) ,.
In the order of the fifth word, the fifth word is output to the output line 21 as it is because it is the header part.

(3) Next, the payload portion of the cell is input to the input line 19 from the sixth word. At this time, the control signal 5 causes the selector 1 to select the output of the exclusive OR circuit 3, and the control signal 5 changes to a signal for causing the shift register 35 and the shift register 37 to perform a shift operation. This shift operation causes the shift register 35 to move to the first
The 6th word, the 7th word, ... are shifted in the order of the stage register, the 2nd stage register, ..., and the 6th word payload bit 1, payload bit 2, ..., payload bit 8 reaches the 5th stage register. .

(4) Next, the 3-bit shift register 37
Since the lower 3 bits are shifted, * (previous data is shown. This is described later. Same as below), *, *, payload bit 1 from the right to the output line C of 43-bit delay data. , Payload bit 2, payload bit 3, payload bit 4, and payload bit 5 are output in this order. This data is input from the exclusive OR circuit 3 through the input line 19 to the payload bit 41, payload bit 42, payload bit 43, payload bit 44, payload bit 45, payload bit 4
6, the payload bit 47 and the payload bit 48 are exclusively ORed. Here, the exclusive logic is taken for the payload bit 1 and the payload bit 44, and the payload bit 2 is taken for the payload bit 45. Therefore, each data is exclusive ORed with the data 43 bits before. It is output to the output line 21.

(5) When the last 53rd word of the payload portion is input from the input line 19 and the header portion of the next cell is input to the input line 19, the control line 5 is input to the selector 1 and the input line 1 is input.
The output of 9 is selected, and the signals are changed to signals for causing the shift register 35 and the shift register 37 to perform the loopback operation. As a result, the flop flop 41 of each shift register re-inputs the data output by itself.
That is, when the header part is input, each shift register holds the data of the payload part of the cell input before that. This holds the data of the payload part of the previous cell until the payload part of the next cell is input, and when the payload part of the next cell is input, the exclusive OR is performed with the data of 43 bits before. This is to allow it.

As described above, the conventional scrambler uses the generator polynomial X ⁴³ + based on I.432 according to the CCITT recommendation.
It is possible to realize the scrambling using 1 and to scramble only the payload part excluding the header. In the descrambler, similarly, the header part receives data received from the network without scrambling, and the payload part takes an exclusive OR with the data 43 bits before to descramble the data.
Output to the output line.

[0016]

However, as described above, in order to stop the shift operation of the shift register and hold the stored data, each shift register is constructed as shown in FIG. One flip-flop must have a selector and a loopback circuit. Therefore, in an ATM scrambler that requires 43-bit delay data, a data holding circuit including a selector and a loopback circuit for inputting control signals to all 43 flip-flops is required, and The wiring has become extremely complicated. For the above reasons, the circuit scale of the scrambler and the descrambler has been increased. This increase in the circuit scale not only increases the scrambler and the descrambler itself, but also brings a disadvantage that the development cost and the manufacturing cost increase.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a scrambler and a descrambler which can be implemented at a small scale and at a low cost by reducing the circuit scale. is there.

[0018]

In order to achieve the above object, the first aspect of the present invention is characterized in that, in a scrambler for scrambling cells to be transmitted to an ATM communication network, data inputted in 8-bit parallel is divided into 5 stages. Minute shift storage register, a second shift register storing one stage of 3-bit parallel data, and the output of one of the first shift register and the second shift register is selected when the header is input. And outputs to the one shift register, selects 8-bit parallel input data when the payload is input, and outputs the selected 8-bit parallel input data to the one shift register, and the first selection circuit or the second selection circuit when the header is input. Output from the other shift register among the shift registers of A second selection circuit that selects the output data of the one shift register and outputs the data to the other shift register when the power is input, and data that is not scrambled when the header is input, and the first selection circuit when the payload is input. And a selection circuit section for scrambling the input data using the delay data of the shift register and the second shift register, and selecting and outputting the scrambled data.

The feature of the second invention is that, in the descrambler for descrambling the cells received from the ATM communication network, the data inputted in 8-bit parallel for five stages are stored. A shift register, a second shift register for storing 3-bit parallel data for one stage, and an output of one of the first and second shift registers at the time of header input to select the one shift A first selection circuit that outputs to a register and selects 8-bit parallel input data when the payload is input and outputs the 8-bit parallel input data to the one shift register; and the other of the first and second shift registers when the header is input. Output from the other shift register is selected and output to the other shift register. A second selection circuit for selecting data output from one shift register and outputting the data to the other shift register; and data not scrambled for header input, and the first shift register for payload input And a selection circuit section that scrambles the input data using the delay data of the second shift register and selects and outputs the scrambled data.

Here, the second selection circuit selects the output from the second shift register and outputs it to the second shift register when the header is input, and the first shift when the payload is input. Of the data output from the register, the upper 3 bits of the data in the 5th stage are selected to select the second
It is preferable to output to the shift register.

The second selection circuit selects the output from the first shift register and outputs it to the first shift register when the header is input, and the second shift register when the payload is input. 3 bits of data output from the first shift register
It is preferable to output to bits.

[0022]

According to the above configuration, among the cells that perform transmission,
When the header arrives, the selection circuit section selects the input data,
The data is transmitted unscrambled. At this time, the first selection circuit selects the data of the output of one (self) shift register in order to hold the data of the payload currently stored in the one shift register, and inputs it to the one shift register again. . Similarly, the second selection circuit selects the data of the output of the other (self) shift register to hold the data of the payload currently stored in the other shift register, and again stores the data in the one shift register. input. Therefore, for example, when the one shift register is the first shift register, the data of the fifth stage is input to the first stage again, so that the entire shift register performs the loopback operation. Therefore, unlike the conventional shift register, the data holding means such as the flip-flops individually perform the loop-back operation, so that the control signals are not individually input. Also, A
Since the TM cell header has 5 bytes, it takes 5 clocks to complete the transmission. Here, since the number of stages of the first shift register is 5, when the five clocks until the end of the transmission of the header have passed, the 5 bytes of data stored in the first shift register are exactly loopbacked. It means that the circuit has returned to the data holding means of the predetermined number of stages of the shift register after one round. That is, the same data as when the input of the payload section of the previous cell is completed is output to the selection circuit section. Therefore, only the data in the payload portion can be scrambled with the data delayed by 43 bits. For the above reason, it becomes unnecessary to provide the selector and the loopback circuit in all the data holding means such as the flip-flops as in the conventional example.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. The scrambler and descrambler according to the present invention utilize the relationship between the number of bytes of the header, which is a value defined in the CITT standard for ATM communication, and the number of bits of delay data used for scrambling and descramble. , It consists of a circuit with a significantly reduced number of selectors and loopback circuits. The details will be described below in the first and second embodiments.

First Embodiment FIG. 1 is a block diagram of a scrambler according to a first embodiment of the present invention. This scrambler is a 8-bit parallel shift register 7 for extracting and storing data transmitted in 8-bit parallel, a 3-bit parallel shift register 9 for one stage, and these shift registers. 3-bit parallel data bus connecting between
At the time of header transmission, the output from the fifth stage of the 5-stage shift register is selected in the 8-bit parallel, the output from the fifth stage of the 5-stage shift register is selected in the 8-bit parallel, and the 8-bit parallel is selected. Selector 1 for outputting to the first stage of the 5-stage shift register, selecting 8-bit parallel transmission data at the time of payload, and outputting to 8-stage parallel to the first stage of the 5-stage shift register
1, the output from the one-stage shift register in the 3-bit parallel is selected at the time of header transmission and output to the one-stage shift register in the 3-bit parallel, and the output of the five stages in the 8-bit parallel is performed at payload transmission. A selector 13 for selecting 3-bit data from the output from the fifth stage of the shift register and outputting it to the first-stage shift register in the 3-bit parallel, and scrambles the transmission data at the time of header transmission. It has a selection circuit 1 that performs a selective operation of transmitting without transmitting and scrambling the transmission data using the delay data of the shift register 7 and the shift register 9 when transmitting the payload.

Next, the individual operation of each of the above units will be described. The selector 11 selects and outputs either the 8-bit parallel data bus 15 or the output of the selector 4. The configuration of the shift register 9 of one stage in 3-bit parallel is exactly the same as that of the shift register 37 in the circuit of the conventional example, but the selector and the loopback circuit which are not shown in FIG. 7 are drawn in FIG. There is. The selector 13 selects and outputs either the 3-bit parallel data bus 17 or the upper 3 bits of the output of the shift register.

The selector 1 is controlled by the control signal 5, and selects either the 8-bit parallel input data 19 or the output of the exclusive OR circuit 3 and outputs it to the selector 11 and the output line 21. . The exclusive OR circuit 3 takes the exclusive OR of the input data 19 and the data output from the data holding unit.

In the conventional example, all the flip-flops forming the shift register are accompanied by the selector and the loopback circuit, but in the present embodiment, each flip-flop forming the shift register 7 also has a selector. No loopback circuit is attached. Instead, a loopback bus 15 is provided from the output of the fifth-stage flip-flop to the selector 11 located in front of the first-stage flip-flop, which is a significant difference from the conventional example. Therefore, the conventional shift register 35
In the circuit of the present embodiment, the number of selectors and loopback buses required for 40 pairs in the above example is reduced to 8 pairs of selectors 11 and loopback buses 15. For the above reasons, the circuit scale can be reduced.

Next, detailed operation of the entire scrambler according to this embodiment will be described with reference to FIG. For convenience of this description, the header part (5 bytes) of the cell will be referred to as header bit 1, header bit 2, ..., Header bit 40 from the first bit. Also, the payload part (48 bytes) of the cell is defined as payload bit 1, payload bit 2, ..., Payload bit 384 from the first bit. Further, among the 8-bit × 5-stage registers of the 40-bit shift register 7, the 1-stage register, the 2-stage register, ... The scrambler performs operations such as input of the input line 19, shift operation of each shift register, and output of the output line 21 in synchronization with the clock signal.

(1) Header bit 1, header bit 2, ..., Header bit 8 (referred to as the first word), which is the header portion of the cell, are sequentially input from the upper part of the input line 19. This header is output line 21 without being scrambled.
Header bit 1, header bit 2, ..., Header bit 8 are output from the upper part.

(2) Similarly, header bit 9, header bit 10, ..., Header bit 16 (second word) ,.
In the order of the fifth word, the fifth word is output to the output line 21 as it is because it is the header part.

(3) Next, the payload portion of the cell is input to the input line 19 from the sixth word. At this time, the control signal 5 becomes a signal that causes the selector 1 to select the output of the exclusive OR circuit 3 and causes the selectors 11 and 13 to perform the shift operation of the shift registers 7 and 9. By this shift operation, the shift register 9 shifts the sixth word, the seventh word, ... In the order of the first-stage register, the second-stage register, ..., And the payload bit 1, the payload bit 2 ,. Payload bit 8 reaches the fifth stage register.

(4) Next, since the lower 3 bits are shifted in the 3-bit shift register 9, * (previous data is shown from the right to the output line A of 43-bit delay data from the right. This will be described later. The same shall apply hereinafter), *, *, payload bit 1, payload bit 2, payload bit 3, payload bit 4, payload bit 5 are output in this order. This data is input from the exclusive OR circuit 3 through the input line 19 to the payload bit 41, payload bit 42, payload bit 43, payload bit 44, payload bit 45, payload bit 4
6, the payload bit 47 and the payload bit 48 are exclusively ORed. Here, the exclusive logic is taken for the payload bit 1 and the payload bit 44, and the payload bit 2 is taken for the payload bit 45. Therefore, each data is exclusive ORed with the data 43 bits before. It is output to the output line 21.

(5) When the last 53rd word of the payload section is input from the input line 19 and the header section of the next cell is input to the input line 19, the control line 5 is input to the selector 1 and the input line 1 is input.
9 is selected, and the signals are changed to signals for causing the shift register 7 and the shift register 9 to perform a loopback operation. As a result, the selector 11 selects the data from the loopback circuit 15, and the selector 13 similarly selects the data from the loopback circuit 17.

Here, it takes 5 clocks to input the header portion of 5 bytes, while the number of stages of the shift register 7 is 5. Therefore, when 5 clocks until the end of transmission of the header have elapsed, the shift is performed. It means that the 5-byte data stored in the register 7 has returned to the original flip-flop even if the loopback bus 15 has just completed one round. That is, the same data as when the input of the payload portion of the previous cell is completed is output to the output point A. Therefore, the input from the input line 19 can be exclusive ORed with the payload bit 43 bits before by the exclusive OR circuit 3 and output to the output line 21.

Next, another embodiment of the scrambler according to the present invention is shown in FIG. This embodiment is an example in which the upper 3 bits of the output of the selector 1 are first shifted by the 3-bit shift register 9 and then shifted by the 40-bit shift register 7. In this embodiment, the upper 3 bits of the output of the selector 1 are input to the selector 13,
It is input to the 3-bit shift register 9. The 3-bit data output from the 3-bit shift register 9 is converted into 40
The lower 3 bits of the bit shift register 7 are output, and the lower 5 bits of the output of the selector 1 are output to the upper 5 bits of the 40 bit shift register 7. With this configuration as well, as in the above-described embodiment, the data in the payload portion input from the input line 19 can be scrambled with the data delayed by 43 bits and output to the output line 21.

Second Embodiment Next, a descrambler according to the present invention will be described with reference to FIG. This descrambler
An 8-bit parallel 5-stage shift register 7 for extracting and storing data received in 8-bit parallel, and a 3-bit parallel 1-stage shift register 9
And a 3-bit parallel data bus connecting these shift registers, and when receiving a header, the output from the fifth stage of the 8-stage parallel shift register is selected to select the 8-bit parallel 5-stage shift register. Output from the 5th stage of the shift register is output to the 1st stage of the shift register of 5 stages in the 8 bit parallel, and 8-bit parallel received data is selected in the payload stage and 5 stages of the 8 bit parallel are selected. Selector 11 for outputting to the first stage of the shift register, and when the header is received, the output from the shift register of the first stage is selected in parallel with the 3 bits.
It outputs to the 1-stage shift register in bit parallel, and when the payload is received, 3-bit data is selected from the output from the 5th stage of the 5-stage shift register in the 8-bit parallel to select the 3-bit parallel. A selector 13 for outputting to a one-stage shift register, receives data without descrambling the received data at the time of header reception, and receives by using delay data of the shift register 7 and the shift register 9 at the time of payload reception. It has a selection circuit 1 for performing a selective operation of descrambled and received data.

Here, since the individual operations of the above-mentioned respective parts have been described in the first embodiment, the description thereof will be omitted.

Further, in the conventional example, all the flip-flops constituting the shift register are accompanied by the selector and the loopback circuit, but in the present embodiment, the shift register 7 is provided.
There is no selector or loopback circuit associated with each flip-flop that composes the. Instead, a loopback bus 15 is provided from the output of the fifth-stage flip-flop to the selector 11 located in front of the first-stage flip-flop, which is a significant difference from the conventional example. Therefore, the number of selectors and loopback buses required for 40 sets in the shift register 35 of the conventional example is reduced to 8 sets of the selector 11 and the loopback bus 15 in the circuit of this embodiment. For the above reasons, the circuit scale can be reduced.

Next, the detailed operation of the entire descrambler according to this embodiment will be described with reference to FIG.

(1) Header bit 1, header bit 2, ..., Header bit 8 (referred to as the first word), which is the header portion of the cell, are sequentially input from the upper part of the input line 19. Since the header portion is not descrambled, the header bit 1, the header bit 2, ...
Header bit 8 is output.

(2) Similarly, header bit 9, header bit 10, ..., Header bit 16 (second word) ,.
In the order of the fifth word, the fifth word is output to the output line 21 as it is because it is the header part.

(3) Next, the payload portion of the cell is input to the input line 19 from the sixth word. At this time, the control signal 5 causes the selector 1 to select the output of the exclusive OR circuit 3, and causes the selectors 11 and 13 to select the shift register 7.
And 9 are signals for causing the shift operation. By this shift operation, the shift register 9 shifts the first-stage register and the second-stage register.
The sixth word, the seventh word, ... Are shifted in the order of the stage register, ... And the payload bit 1, payload bit 2, ..., Payload bit 8 which is the sixth word reach the fifth stage register.

(4) Next, since the lower 3 bits are shifted in the 3-bit shift register 9, * (previous data is shown from the right to the output line B of 43-bit delay data from the right. This will be described later. The same shall apply hereinafter), *, *, payload bit 1, payload bit 2, payload bit 3, payload bit 4, payload bit 5 are output in this order. This data is input from the exclusive OR circuit 3 through the input line 19 to the payload bit 41, payload bit 42, payload bit 43, payload bit 44, payload bit 45, payload bit 4
6, the payload bit 47 and the payload bit 48 are exclusively ORed. Here, the exclusive logic is taken for the payload bit 1 and the payload bit 44, and the payload bit 2 is taken for the payload bit 45. Therefore, each data is exclusive ORed with the data 43 bits before. It is output to the output line 21. As a result, descrambling is performed.

(5) When the last 53rd word of the payload part is input from the input line 19 and the header part of the next cell is input to the input line 19, the control line 5 is input to the selector 1 and the input line 1 is input.
9 is selected, and the signals are changed to signals for causing the shift register 7 and the shift register 9 to perform a loopback operation. As a result, the selector 11 selects the data from the loopback circuit 15, and the selector 13 similarly selects the data from the loopback circuit 17.

Here, it takes 5 clocks to input the header portion of 5 bytes, while the number of stages of the shift register 7 is 5, the shift is performed when 5 clocks until the end of the transmission of the header have elapsed. It means that the 5-byte data stored in the register 7 has returned to the original flip-flop even if the loopback bus 15 has just completed one round. That is, the same data as when the input of the payload portion of the previous cell is completed is output to the output point A. Therefore, the input from the input line 19 can be exclusive ORed with the payload bit 43 bits before by the exclusive OR circuit 3 and output to the output line 21.

Next, another embodiment of the descrambler according to the present invention is shown in FIG. This embodiment is an example in which the upper 3 bits of the output of the selector 1 are first shifted by the 3-bit shift register 9 and then shifted by the 40-bit shift register 7. In this embodiment, the upper 3 bits of the output of the selector 1 are input to the selector 13 and the 3-bit shift register 9. The 3-bit data output from the 3-bit shift register 9 is output to the lower 3 bits of the 40-bit shift register 7, and the lower 5-bit data output from the selector 1 is output to 40 bits.
It outputs to the upper 5 bits of the bit shift register 7. With this configuration as well, as in the above-described embodiment, the data in the payload section input from the input line 19 is descrambled with the data delayed by 43 bits, and the output line 2
Can be output to 1.

[0047]

As described above, according to the configurations of the scrambler and the descrambler according to the present invention,
Since the loopback operation is performed in the entire shift register, the number of selection circuits (selectors) and loopback circuits can be reduced. This makes it possible to provide an inexpensive scrambler and descrambler that can be configured with a small-scale circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a scrambler according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing another scrambler according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a descrambler according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing another descrambler according to the second embodiment of the present invention.

FIG. 5 is a diagram for explaining the principle of scrambling and descrambling.

FIG. 6 is a diagram showing a conventional example of a scrambler that scrambles only a payload portion of a cell in a serial data transmission system.

FIG. 7 is a diagram showing a conventional example of a scrambler that scrambles only a payload portion of a cell in a parallel data transmission system.

8 is a diagram showing the configuration of each flip-flop that composes the shift register in FIG. 7 and the selectors and loopback circuits associated with it.

[Explanation of symbols]

 1, 11, 13, 39 Selector 3 Exclusive OR circuit 5 Control signal 7 40-bit shift register 9 3-bit shift register 15, 17 Loopback circuit 19, 31 Input line 21, 33 Output line 23a, 23b, 27 Exclusive OR output section 25a, 25b, 29 shift register section 35 40-bit shift register 37 3-bit shift register 41 flip-flop 43 signal line A, B, C 43-bit delay data output line

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H04Q 3/00

Claims (4)

[Claims] 1. A scrambler for scrambling cells to be transmitted to an ATM communication network, comprising: a first shift register for storing 5 stages of data input in 8-bit parallel; and 1 stage of 3-bit parallel data. A second shift register for storing minutes, and an output of one of the first and second shift registers at the time of inputting a header to be output to the one shift register, and at the time of inputting a payload, 8
A first selection circuit that selects bit-parallel input data and outputs it to the one shift register, and selects an output from the other shift register of the first or second shift registers when the header is input. Second output to the other shift register, and when the payload is input, the output data of the one shift register is selected and output to the other shift register.
Selection circuit and the data that is not scrambled when the header is input, and when the payload is input, the input data is scrambled using the delay data of the first shift register and the second shift register, and this scramble is performed. And a selection circuit section for selecting and outputting the selected data, and a scrambler. 2. A descrambler for descrambling a cell received from an ATM communication network, comprising: a first shift register for storing 5 stages of data input in 8-bit parallel; and 3-bit parallel. A second shift register for storing one stage of data, and an output of one of the first and second shift registers at the time of header input to be output to the one shift register, and at the time of payload input 8
A first selection circuit that selects bit-parallel input data and outputs it to the one shift register, and selects an output from the other shift register of the first or second shift registers when the header is input. Second output to the other shift register, and when the payload is input, the output data of the one shift register is selected and output to the other shift register.
Selection circuit and the data that is not scrambled when the header is input, and when the payload is input, the input data is scrambled using the delay data of the first shift register and the second shift register, and this scramble is performed. And a selection circuit section for selecting and outputting the selected data. 3. The second selection circuit selects the output from the second shift register and outputs it to the second shift register when the header is input, and the first shift register when the payload is input. 5 of the output data
2. The upper 3 bits of data in the second stage are selected and output to the second shift register.
The scrambler according to claim 2 or the descrambler according to claim 2. 4. The second selection circuit selects the output from the first shift register and outputs it to the first shift register when a header is input, and outputs the second shift register when a payload is input. 3. The scrambler according to claim 1 or the descrambler according to claim 2, wherein the 3-bit data of the output of 1 is selected and output to the lower 3 bits of the first shift register.