JPH0897705A - Output buffer circuit - Google Patents

Abstract

PURPOSE: To provide an output of a signal satisfying an interface condition even when a power supply voltage in the inside is high by providing an output circuit and an output voltage drop circuit supplying a current to the output circuit so as to decrease a voltage of an output signal of the output circuit when a power supply voltage exceeds a predetermined voltage. CONSTITUTION: The buffer circuit is provided with output circuits 1, 2 providing an output of a voltage signal corresponding to a power supply voltage Vcc based on an input signal and output voltage drop circuits 3-5 connecting to output terminals of the output circuits 1, 2 and supplying a current to the output circuits when the power supply voltage Vcc exceeds a predetermined voltage to decrease a voltage of output signals from the output circuits 1, 2. Then the output circuits 1, 2 provide a voltage signal corresponding to the power supply voltage based on an input signal and the output voltage drop circuits 3-5 connecting to output terminals of the output circuits 1, 2 supply a current to the output circuits 1, 2 when the power supply voltage Vcc exceeds a predetermined voltage to decrease a voltage of output signals from the output circuits 1, 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit for a semiconductor device, and more particularly, to a semiconductor device having an internal power supply of 5V, which enables an interface with a semiconductor device having a power supply voltage of 3.3V. It is a thing.

[0002]

23 to 25 show the configuration of a conventional output buffer circuit. FIG. 23 shows an N-N type buffer circuit
24 shows a LowVth N-N type buffer circuit, and FIG. 25 shows a P-N type buffer circuit. In FIG. 23, 2c and 2db are NMOS transistors connected in series, one end of the output end of the NMOS transistor 2c is connected to the power supply VCC, and one end of the output of the NMOS 2d is grounded (GND). The other output terminals of the NMOS transistors 2c and 2d are output terminals DOU, respectively.
It is connected to T. Also, the NMOS transistor 2
The input ends of c and 2d are connected to a circuit (not shown).

In FIG. 24, 1 is a normal NMO.
Low whose threshold voltage Vth is lower than that of the S transistor
It is a Vth NMOS transistor. LowVth NMOS
The transistor 1 and the NMOS transistor 2 are connected in series with each other, one end of the output terminal of the LowVth NMOS transistor 1 is connected to VCC, one end of the output terminal of the NMOS transistor 2 is grounded, and the input terminal is connected to a circuit (not shown). This is the same as the case of FIG.

Further, in FIG. 25, 44 is a PMOS transistor. PMOS transistor 44 and NMO
23. The connection with the S transistor 2 is that one end of the output is connected in series with the grounded NMOS transistor 2 and the input end is connected to a circuit (not shown).
Is the same as in.

FIG. 26 shows the relationship between the power supply voltage VCC and the H level output voltage VOH of the output buffer circuit shown in FIGS. 23 to 25. 101 is N-N
Type buffer circuit characteristics (VOH VCC dependency)
02 shows the characteristics of the LowVth N-N type buffer circuit.
3 shows the characteristics of the P-N type buffer circuit. Here, the H-level output current IOH = -4 mA. In FIG. 26, a rectangular area ABDC is a VOH of a TTL interface whose standard power supply voltage is 5V.
It shows the range of the standard. Point A is the minimum VCC
= 4.5V minimum VOH = 2.4V, and point D is maximum VO for maximum VCC = 5.5V
H = VCC + 10% = 5.5V is given. The point B is the minimum VOH = 2.4V against the maximum VCC = 5.5V.
And point C gives a maximum VOH = 5.5V for a minimum VCC = 4.5V.

Further, in FIG. 26, a rectangular area AB
D'C 'indicates the allowable range of VOH for the interface with the circuit having the standard power supply voltage of 3.3V.
The point D ′ is the maximum VO for the maximum VCC = 5.5V.
It gives H = VCC + 0.3V = 3.6V. Further, the point C ′ is the maximum VOH = for the minimum VCC = 4.5V.
Apply 3.6V. The characteristics at points A and B are the same as those at the power supply voltage of 5V. Here, the maximum VOH value of 3.6 V is set so that a large amount of current does not flow from the output buffer circuit to a device (not shown) connected to the output buffer circuit and having a power supply voltage of 3.3 V. This is the value that was set. If 5V is applied to the input terminal of the 3.3V power supply system device, the potential difference between both interfaces becomes 1.7V, and a large amount of current flows.

Next, the operation of the conventional output buffer circuit will be described. In any of the buffer circuits in FIGS. 23 to 25, one of the transistors connected in series is turned on by a signal input to the gates of two transistors from a circuit (not shown). Along with this, an L level or H level signal is output to the output DOUT. Power supply V
When the transistors 2c, 1, 44 connected to CC are turned on, an H level signal is output to the output DOUT.

However, this H level output voltage VOH
Is different for each circuit. This will be described with reference to the characteristic diagram of FIG. First, the VOH of the N-N type buffer circuit of FIG. 23 is as shown in the graph 101 of FIG.
Minimum VOH = 2.2 at minimum VCC = 4.5V
V, maximum VO at maximum VCC = 5.5V
H = 3.6V is taken. And VCC = 4.5V-5.
It changes linearly at 5V. Here, VOH is given by a voltage (VCC-Vth) obtained by subtracting the threshold voltage Vth of the NMOS transistor 2c from the power supply voltage VCC. Here, by applying a substrate bias to the semiconductor substrate in which the transistor is formed, Since Vth increases due to the substrate effect that the threshold voltage changes, the characteristics shown in graph 101 are obtained. Graph 101
2 is outside the rectangular ABCD, which is the allowable range when the voltage is 5V, near VCC = 4.5V.
VOH of the N-N type buffer circuit of No. 3 does not satisfy the condition of H level output.

Next, as shown in the graph 102 of FIG. 26, the VOH of the LowVth N-N type buffer circuit of FIG. 24 is the minimum V of about 3.0V at the minimum VCC = 4.5V.
Taking OH, maximum V at maximum VCC = 5.5V
OH = 4.0V is taken. And, VCC = 4.5V ~
It changes linearly at 5.5V. In this circuit as well, VOH is given by VCC-Vth as in the above case, but since the LowVth NMOS transistor 1 is used, the characteristics shown in the graph 102 are obtained. Since the graph 102 is inside the rectangular ABCD, it is within the range of the VOH specifications when the voltage is 5V, and there is no problem even if the circuit of FIG. 24 is used as a 5V interface.

Next, V of the P-N type buffer circuit of FIG.
OH is the minimum VCC as shown in the graph 103 of FIG.
= 4.5V, the minimum VOH = 4.5V, and the maximum VCC = 5.5V, the maximum VOH = VCC =
It takes 5.5V. Then, VCC = 4.5V to 5.5V
Changes linearly at. That is, VOH = VCC in this circuit. Graph 103 is a rectangle ABD
Since it is inside C, it is within the range of VOH specifications when the voltage is 5 V, and there is no problem even if the circuit of FIG. 25 is used as a 5 V interface.

As described above, the circuits of FIGS. 24 and 25 can be used as a 5V system interface circuit.

[0012]

By the way, recently, in order to reduce power consumption, it is rapidly becoming popular to set the power supply voltage of the system to 3.3V. On the other hand, even though the power supply voltage is lower than the conventional 5V, the required performance such as the operation speed of the device is further increasing.
Here, as one of means for solving these contradictory requirements, the power supply voltage is 3.
There is a 3.3V interface that can be connected to a 3V circuit.

The allowable range of VOH in the 3.3V interface is shown by a rectangle ABD'C 'in FIG.
That is, in the 3.3V interface, VCC =
At 4.5V to 5.5V, VOH = 2.4V to 3.V.
Must be in the 6V range.

By the way, according to the characteristic 101 of the N-N type buffer circuit of FIG. 26, in the vicinity of VCC = 4.5V, VOH takes 2.2V which is lower than the minimum value 2.4V, so that the rectangle ABD'C '. It deviates from the area of and does not satisfy the 3.3V interface. Further, according to the characteristic 102 of the LowVth N-N type buffer circuit, VOH exceeds 3.6V in the range exceeding VCC = 5V, and therefore 3.3 similarly.
Not satisfied with the V interface. According to the characteristic 103 of the P-N type buffer circuit, VCC = 4.5V to 5.V.
Since VOH exceeds 3.6V within the range of 5V, the 3.3V interface is not satisfied in the same manner. As mentioned above,
The conventional buffer circuits shown in FIGS. 23 to 25 have a problem that they are not compatible with the 3.3V interface when the internal voltage is 5V.

The present invention has been made to solve the above problems, and an output buffer circuit capable of outputting a signal satisfying a 3.3V interface condition even when the internal power supply voltage is 5.5V. Aim to get.

[0016]

According to another aspect of the present invention, there is provided an output buffer circuit, which is connected to an output circuit for outputting a signal of a voltage corresponding to a power supply voltage based on an input signal and an output terminal of the output circuit, An output voltage drop circuit that lowers the voltage of the output signal of the output circuit by causing a current to flow when the voltage exceeds a predetermined voltage.

An output buffer circuit according to a second aspect of the present invention further comprises a power supply voltage adjusting circuit for adjusting the output voltage in accordance with the power supply voltage, and the power supply of the output circuit is supplied from the power supply voltage adjusting circuit. Is.

According to a third aspect of the present invention, in the output buffer circuit, the power supply voltage adjusting circuit is configured such that a control voltage generating circuit for generating a control voltage corresponding to the power supply voltage and one of output terminals are connected to the power supply, And a transistor that outputs a voltage lower than the power supply voltage.

An output buffer circuit according to a fourth aspect of the present invention includes a power supply current adjusting circuit that adjusts an output current according to a power supply voltage, and the power supply of the output circuit is supplied from the power supply current adjusting circuit. .

According to another aspect of the output buffer circuit of the present invention, the power supply current adjusting circuit includes a transistor that is always on when a power supply voltage is applied, and an on-state and an off-state at a predetermined power supply voltage. Is connected in parallel with a transistor that switches.

An output buffer circuit according to a sixth aspect of the present invention is further connected to an output terminal of the output circuit, and when the power supply voltage is lower than a predetermined voltage, the power is supplied to the output circuit for output. The output voltage raising circuit for raising the voltage of the signal to be output is provided.

According to a seventh aspect of the present invention, there is provided an output buffer circuit comprising: a first diode-connected transistor that causes a current to flow through the output voltage drop circuit when the applied voltage exceeds a predetermined voltage; The second transistor is connected in series with the first transistor and controls the on / off of the current based on a control signal from the outside.

According to another aspect of the present invention, there is provided an output buffer circuit comprising: a first diode-connected transistor which causes a current to flow through the output voltage drop circuit when an applied voltage exceeds a predetermined voltage; The second transistor is connected in series with the first transistor and controls the on / off of the current based on the input signal of the output circuit.

According to a ninth aspect of the present invention, in the output buffer circuit, the output voltage drop circuit comprises a diode-connected transistor that causes a current to flow when the applied voltage exceeds a predetermined voltage.

An output buffer circuit according to a tenth aspect of the present invention is an output circuit which outputs a signal of a voltage corresponding to a power supply voltage based on an input signal, a reference voltage generation circuit which generates a predetermined reference voltage, and the output circuit. And an output voltage maintaining circuit for making the voltage of the output signal of the output circuit constant by supplying a constant voltage based on the reference voltage output from the reference voltage generating circuit.

According to another aspect of the present invention, there is provided an output buffer circuit, wherein the output voltage maintaining circuit includes a switch circuit for disconnecting a reference voltage output from the reference voltage generating circuit based on an input signal of the output circuit, and one of output terminals. Is connected to the power supply and the other is connected to the output terminal of the output circuit, and is composed of a bipolar transistor that operates based on the output of the switch circuit.

[0027]

According to the first aspect of the invention, the output circuit outputs the signal of the voltage corresponding to the power supply voltage based on the input signal, and the output voltage drop circuit connected to the output terminal of the output circuit,
The voltage of the output signal of the output circuit is lowered by passing a current when the power supply voltage exceeds a predetermined voltage.

According to the second aspect of the present invention, the power supply voltage adjusting circuit adjusts the output voltage corresponding to the power supply voltage and supplies the output to the output circuit.

According to another aspect of the present invention, the control voltage generating circuit of the power supply voltage adjusting circuit generates a control voltage corresponding to the power supply voltage, and the transistor whose one output terminal is connected to the power supply is set to the control voltage. Based on this, a voltage lower than the power supply voltage is output.

According to the fourth aspect of the present invention, the power supply current adjusting circuit adjusts the output current corresponding to the power supply voltage and supplies the output circuit with this current.

According to a fifth aspect of the present invention, there are provided a transistor which is included in the power supply current adjusting circuit and which is always on when a power supply voltage is applied, and a predetermined power supply voltage which is connected in parallel with the transistor. A transistor that switches between an on state and an off state regulates the current.

According to a sixth aspect of the invention, the output voltage raising circuit connected to the output terminal of the output circuit supplies power when the power source voltage falls below a predetermined voltage. Raise the voltage of the signal output by.

According to a seventh aspect of the present invention, the first diode-connected transistor, which constitutes the output voltage drop circuit, flows a current when the applied voltage exceeds a predetermined voltage, and the first transistor. A second transistor that is connected in series with the first transistor and controls the on / off of the current based on a control signal from the outside causes a current to flow and lowers the voltage of the output signal.

According to an eighth aspect of the present invention, a diode-connected first transistor, which constitutes the output voltage drop circuit, flows a current when the applied voltage exceeds a predetermined voltage, and the first transistor. A second transistor connected in series with the first transistor and controlling the on / off of the current based on the input signal of the output circuit causes a current to flow and lowers the voltage of the output signal.

According to a ninth aspect of the present invention, the diode-connected transistor that makes up the output voltage drop circuit and makes a current flow when an applied voltage exceeds a predetermined voltage makes a current flow and outputs an output signal. Lower the voltage.

According to the tenth aspect of the present invention, the output circuit outputs the signal of the voltage corresponding to the power supply voltage based on the input signal, the reference voltage generating circuit generates the predetermined reference voltage, and the output voltage maintaining circuit operates. The voltage of the output signal of the output circuit is made constant by being connected to the output terminal of the output circuit and supplying a constant voltage based on the reference voltage output from the reference voltage generating circuit.

In the eleventh aspect of the present invention, the switch circuit of the output voltage maintaining circuit disconnects the reference voltage output from the reference voltage generating circuit based on the input signal of the output circuit, and one of the output terminals is the power source. A bipolar transistor connected to the output terminal of the output circuit and the other connected to the output terminal of the output circuit operates based on the output of the switch circuit to output a constant voltage.

[0038]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a buffer circuit according to the first embodiment. In FIG. 1, 1 is LowVth having a lower threshold voltage Vth than a normal NMOS transistor.
NMOS transistors, 2 to 5 are NMOS transistors. LowVth NMOS transistor 1 and NMOS
The transistor 2 is connected in series with each other. Lo
The other end of the output terminal of the wVth NMOS transistor 1 is the power supply V
The other end of the output end of the NMOS transistor 2 connected to CC is grounded (GND). Further, these gates are connected to a circuit (not shown).

Further, the NMOS transistors 3 to 5 are connected in series with each other to form an output voltage drop circuit. The gates of the NMOS transistors 3 and 4 are diode-connected with their gates connected to the output terminals. NMOS
One of the output terminals of the transistor 3 is connected to the output terminal DOUT of this buffer circuit. Also, NM
One of the output terminals of the OS transistor 5 is grounded. The gate of the NMOS transistor 5 is connected to an internal circuit (not shown), and the output control signal (OE signal) is input.

Next, the operation will be described. This buffer circuit is the same as the LowVth N-N type buffer circuit of FIG. 24 except that the output voltage drop circuit is connected to the output terminal DOUT. That is, from the circuit not shown, 2
A signal input to the gates of the two transistors 1 and 2 turns on one of the transistors connected in series. Along with this, an L level or H level signal is output to the output DOUT. When the transistor 1 connected to the power supply VCC is turned on, an H level signal is output to the output DOUT.

If there is no output voltage drop circuit, the relationship between the output voltage VOH of this circuit and the power supply voltage VCC is as shown in the graph 102 of FIG. 2 (the same as the graph 102 of FIG. 26), and VCC is 5V. If exceeded, VOH is 3.6V
As described above, the rectangle ABD'C ', which is the area of the 3.3V interface, is deviated. Therefore, this embodiment 1
Is to suppress the increase of VOH by satisfying the condition of 3.3V interface by causing a current to flow through the output voltage drop circuit when VCC becomes large.

H is applied to the output terminal DOUT of this buffer circuit.
When outputting a level signal, the gate potential of the LowVth NMOS transistor 1 is VCC and the gate potential of the NMOS transistor 2 is GND. Therefore,
LowVth NMOS transistor 1 is turned on,
If the NMOS transistors 3 to 5 are not provided, the level of DOUT becomes VCC-VTH.

Further, the OE signal is at the H level in such a read state, and the NMOS transistor 5 is turned on, so that the output voltage drop circuit operates. It should be noted that this internal OE signal is generated on the basis of external / CS / WE / OE signals (not shown), and goes to L level when the external / CS / OE signal is at H level and the external / WE signal is at L level. . Therefore, when the semiconductor device in which this buffer circuit is formed is in the standby state, the chip disable state or the write state, the OE signal becomes L level and the NMOS transistor 5 is turned off. At this time, no current flows in the output voltage drop circuit. Even if the NMOS transistor 5 is on, the potential is low when the L-level signal is output to DOUT, so the potential is low.
The drain voltage of the transistor 5 is small, and no current flows in the output voltage drop circuit. As described above, the current flows through the output voltage drop circuit only when the OE signal is at the H level and the signal of the predetermined level or more is output to DOUT.

When the NMOS transistor 5 is turned on, a current flows through the output voltage drop circuit, so that the output voltage of DOUT is clamped and its level drops. Therefore,
In order for the graph 102 of FIG. 2 to satisfy the 3.3V interface condition, the NMOS transistor 5 is turned on at a predetermined voltage (for example, V _{1 of} FIG. 2) so as not to exceed the rectangular area ABD'C '. You can do it like this.

Next, the conditions for turning on the NMOS transistor 5 will be described. The potential V _A of the non-grounded output terminal (point A) of the NMOS transistor 5 is given by V _A = VCC-Vth (NMOS1) -Vth (NMOS3) -Vth (NMOS4). Here, Vth (NMOSi) is the transistor i
Means the threshold voltage of. In order for the NMOS transistor 5 to be turned on, V _A must be higher than 0V. Therefore, the NMOS transistor 5 is turned on,
The condition that the power supply voltage VCC that clamps the voltage of the output terminal DOUT is satisfied is VCC-Vth (NMOS1) -Vth (NMOS3) -Vth (NMOS4)> 0 ∴ VCC> Vth (NMOS1) + Vth (NMOS3) + Vth (NMOS4)

Therefore, the VCC voltage V1 which is the starting point of the graph 104 in FIG. 2 is obtained by the right side of the above equation. That is, V1 = Vth (NMOS1) + Vth (NMOS3) + Vth (NMOS4)
Is. Here, the graph 104 has a rectangular area ABD ′.
In order to set V1 to a desired value so as not to deviate from C ',
The number of diode-connected NMOS transistors 3 and 4 may be adjusted according to the configuration of each semiconductor device (two in FIG. 2). The NMOS transistors 3 and 4
The threshold voltage Vth is about 1 to 2V due to the substrate effect.

When the NMOS transistor 5 is turned on, the LowVth NMOS transistor 1 and the NMO are turned on.
A current flows from VCC in FIG. 1 toward the ground point through the S transistors 3 to 5. At this time, LowVthNMO
Since a voltage drop occurs in the S-transistor 1, the voltage of the output terminal DOUT becomes lower than VCC-Vth (NMOS1) by this voltage drop.

Next, a condition for VOH to satisfy the 3.3V interface condition even when VCC becomes 5.5V, that is, a condition for VOH ≦ 3.6 will be described. As described above, VOH changes from VCC to LowV
The voltage drops by the voltage drop in the th NMOS transistor 1. Therefore, VOH = VCC-Vth (NMOS1) ≤ 3.6V ∴Vth (NMOS1) ≥ VCC-3.6V = 1.9V The LowVth NMOS transistor 1 satisfying such a condition is selected. A graph 104 in FIG. 2 shows VOH characteristics when the above conditions are satisfied.

As described above, according to the buffer circuit of the first embodiment, the output voltage can be suppressed to a low level by providing the output voltage drop circuit. Therefore, even if the internal voltage is 5V, the 3.3V interface is provided. Can be adapted to.

Since the output voltage drop circuit is controlled by the OE signal, the current flows from the output terminal DOUT only when the signal is output to the outside, and the current does not flow at other times. Therefore, the average current consumption of the buffer circuit can be reduced as compared with the case where the output voltage drop circuit is always operated.

Example 2. In addition, the buffer circuit of the above-described first embodiment includes the LowVth NMOS transistor 1 and the NMOS.
LowVth NMOS with transistor 2 connected in series
Although the -N type buffer circuit is used, the output voltage reduction circuit may be provided in the NN type buffer circuit configured by connecting two NMOS transistors in series.

FIG. 3 is a diagram showing the structure of the buffer circuit according to the second embodiment. In FIG. 3, 2a and 2b are NMOS transistors connected in series with each other. N
The other end of the output end of the MOS transistor 2a is connected to VCC, and the other end of the output end of the NMOS transistor 2b is grounded (GND). Further, these gates are connected to a circuit (not shown). NMOS transistor 3 ~
The output voltage drop circuit constituted by 5 is the same as that shown in FIG. 1 and its explanation is omitted.

Here, the NMOS transistor 2 of FIG.
a and 2b are NMOS transistors 2c and 2d of FIG.
And the threshold voltage is small. That is, this is a case where all the transistors of the semiconductor device in which the buffer circuit of FIG. 3 is formed are LowVth NMOS transistors. At this time, VC of the buffer circuit of FIG.
The C-VOH characteristics are as shown in FIG.
101 and LowVth, which are the characteristics of the type buffer circuit
The characteristic is intermediate to that of the graph 102, which is the characteristic of the N-N type buffer circuit, and is, for example, the graph 101b.
In the following description, unlike the conventional N-N type buffer circuit, the N-N type buffer circuit is different from the Low type described above.
VthN-Low VthN type buffer circuit.

Also in the second embodiment, the voltage for turning on the NMOS transistor 5 can be set based on VCC> Vth (NMOS2a) + Vth (NMOS3) + Vth (NMOS4) = V1 as in the case of the first embodiment. When the power supply voltage VCC is higher than the predetermined voltage V1, the output voltage can be suppressed low by causing a current to flow in the output voltage drop circuit. As a result, VCC> V
1, the characteristics of the buffer circuit of FIG. 3 are as shown in the graph 104b of FIG. 4, and the voltage VOH output by this buffer circuit is smaller than that of the graph 101b. Therefore, the output characteristic of this buffer circuit can be set to be within the rectangle ABD'C 'which is the 3.3V interface area.

As described above, according to the buffer circuit of the second embodiment, the output voltage can be suppressed to a low level by providing the output voltage drop circuit. Therefore, even if the internal voltage is 5V, the 3.3V interface is provided. Can be adapted to.

Since the output voltage drop circuit is controlled by the OE signal, the current flows from the output terminal DOUT only when the signal is output to the outside, and the current does not flow at other times. Therefore, the average current consumption of the buffer circuit can be reduced as compared with the case where the output voltage drop circuit is always operated.

Further, according to the second embodiment, the NMOS
Since the circuit is composed of transistors, LowVthN
A special process required for forming a MOS transistor and a mask therefor are not required, and the number of masks is reduced and the manufacturing process is simplified as compared with the case of manufacturing the buffer circuit of the first embodiment.

Example 3. In addition, in the above-mentioned Example 1,
Although the ON / OFF of the NMOS transistor 5 is directly controlled by the OE signal, it may be controlled by a signal common to the control signals of the other transistors.

FIG. 5 shows the structure of the buffer circuit according to the third embodiment. This circuit is a modification of the circuit of FIG. In FIG. 5, 7 is an SA signal which is an output signal of a sense amplifier for amplifying and outputting the data stored in a memory cell (not shown) and an OE signal of negative logic (/
OE) as an input and outputs a control signal for the LowVth NMOS transistor 1. Reference numeral 8 denotes a negative logic output signal (/ SA signal) of the sense amplifier and a negative logic O.
The NOR circuit receives the E signal as an input and outputs a control signal for the NMOS transistor 2. LowVthNM
The OS transistor 1 and the NMOS transistors 2 to 5 are
This is the same as that shown in the first embodiment, but is different in that the NMOS transistor 5 is controlled by the output of the NOR circuit 7 (the gate input of the LowVth NMOS transistor 1).

Next, the operation will be described. The negative logic OE signal (/ OE) becomes H level during the write operation, the standby state, and the chip disable state, and the NOR circuit 7 outputs the L level signal. Therefore, NMO
The gate potential of the S transistor 5 becomes L level, and this transistor is in the off state. Therefore, at this time, no current flows in the output voltage drop circuit.

On the other hand, in the operation of / OE going to L level, when SA is at L level, NOR circuit 7 outputs H level. Only in this case, the buffer circuit of FIG. 5 outputs the H level. At the same time, the gate potential of the NMOS transistor 5 becomes H level, and the output voltage drop circuit operates. The operation of the output voltage drop circuit is similar to that of the first embodiment. Further, when SA is at H level, the NOR circuit 8 outputs at H level, so the buffer circuit outputs at L level.

Thus, even if the output voltage drop circuit is controlled by the gate signal of the LowVth NMOS transistor 1 instead of directly by the OE signal, the output voltage drop circuit operates in the same manner as in the first embodiment.

According to the third embodiment, the internal / O
Since the E signal is not connected to the output voltage drop circuit, the load capacitance of the internal / OE signal is small. Therefore, there is an effect that the OE access can be made faster than in the case of the first embodiment.

Example 4. In the second embodiment, the NMO
Although the on / off of the S transistor 5 is directly controlled by the OE signal, it may be commonly controlled by the control signals of the other transistors as in the case of the third embodiment.

FIG. 6 shows the structure of the buffer circuit according to the third embodiment. This circuit is a modification of the circuit of FIG. In FIG. 6, reference numeral 7 is an input of the SA signal which is the output of the sense amplifier and the OE signal (/ OE) of negative logic,
A NOR circuit for outputting a control signal to the NMOS transistor 2a, and 8 is a negative logic output of the sense amplifier /
It is a NOR circuit which receives the SA signal and the OE signal of negative logic and outputs a control signal for the NMOS transistor 2b. The NMOS transistors 2a, 2b and 3 to 5 are
Same as that of the second embodiment, except that the NMOS transistor 5 outputs the output of the NOR circuit 7 (the NMOS transistor 2
The difference is that it is controlled by the gate input of a).

In the buffer circuit of FIG. 6, the operations of the NOR circuits 7 and 8 and the NMOS transistor 5 are the same as those in the third embodiment, and the operations of the output voltage drop circuit are the same as those in the second embodiment. Therefore, the detailed description of the operation is omitted.

According to the fourth embodiment, since the internal / OE signal is not connected to the output voltage drop circuit, the internal / OE signal is generated.
The load capacity is smaller for signals. Therefore, there is an effect that the OE access can be made faster than in the case of the second embodiment. Furthermore, since a manufacturing process for the LowVth NMOS transistor and a mask therefor are not required, the number of masks can be reduced and the manufacturing process can be omitted.

Example 5. Although the output voltage drop circuit is controlled by the OE signal in the first embodiment, when the control by the OE signal is unnecessary, the configuration can be further simplified.

FIG. 7 is a diagram showing the structure of the buffer circuit according to the fifth embodiment. In FIG. 7, 9 is a diode-connected NMOS transistor. The buffer circuit according to the fifth embodiment is different only in that the transistor 5 connected in series in the output voltage drop circuit of the buffer circuit in FIG. 1 is changed to a diode connection. The basic operation is the same as when the OE signal is at the H level in the buffer circuit of FIG.

As in the case of the first embodiment, the transistor 1 and the transistors 3, 4 and 9 of the fifth embodiment have the following operating condition formulas so that the operating point of the output voltage drop circuit becomes a predetermined voltage. Selected to meet. VCC-Vth (NMOS1) -Vth (NMOS3) -Vth (NMOS4) -Vth (NMOS9)>
0 However, (operating voltage) = Vth (NMOS1) + Vth (NMOS3) + Vth (NM
OS4) + Vth (NMOS9). Further, in order to satisfy the 3.3V interface condition when VCC = 5.5V, the following formula is also selected. VOH = VCC-Vth (NMOS1) ≤ 3.6V ∴Vth (NMOS1) ≥ 1.9V In order to satisfy the above conditions, transistors 1, 3,
The sizes of 4 and 9 and the threshold voltage Vth are adjusted.

According to the fifth embodiment, as compared with the third and fourth embodiments, the structure of the output voltage drop circuit is simplified and the NMO to which the OE signal inside the semiconductor device is connected.
Since the number of S-transistors is reduced, the load of the internal OE signal is reduced, so that the OE access can be speeded up.

Example 6. The output voltage drop circuit of the fifth embodiment may be applied to the buffer circuit of the second embodiment. The structure of the buffer circuit in this case is shown in FIG. Since the operation of this circuit is the same as that of the fifth embodiment, its explanation is omitted.

According to the fifth embodiment, as compared with the third and fourth embodiments, the structure of the output voltage drop circuit is simplified and the NMO to which the OE signal inside the semiconductor device is connected.
Since the number of S-transistors is reduced, the load of the internal OE signal is reduced, so that the OE access can be speeded up. Further, a mask for manufacturing the LowVth transistor is unnecessary, the number of masks can be reduced, and the process can be omitted.

Example 7. Further, the power consumption of the buffer circuit may be reduced by reducing the current flowing through the output voltage drop circuits of the first to sixth embodiments. FIG. 9 shows the structure of the buffer circuit of the seventh embodiment. Figure 9
The buffer circuit of FIG. 3 adds a circuit for lowering the voltage (power supply voltage) applied to the output transistors 1 and 2 to the buffer circuit of FIG. 1, and directly reduces the level of the signal appearing at the output terminal DOUT, It limits the current flowing through the output voltage drop circuit.

In FIG. 9, the gate 10 is a PMO.
Connected to the output terminal (node B) of the S transistor 12,
This is an NMOS transistor for reducing the power supply voltage applied to the LowVth NMOS transistor 1 based on the voltage of the node B. Power is supplied to the output transistors 1 and 2 via the NMOS transistor 10. Reference numeral 12 is a PMOS transistor whose gate is grounded, 13 and 14 are diode-connected NMOS transistors, and 15 is an N transistor that operates based on the OE signal to turn on / off the current flowing through the NMOS transistors 13 and 14.
It is a MOS transistor. These NMOS transistors 13 to 15 are connected in series like the output voltage drop circuit of the first embodiment. Also, the PMOS transistor 1
One of the two output terminals is connected to the power supply VCC and the other is N
It is connected to the output terminal of the MOS transistor 13. Further, the LowVth NMOS transistor 1 and the NMOS transistors 2 to 5 are the same as those shown in FIG.

The difference between the buffer circuit of FIG. 9 and the buffer circuit of FIG. 1 is that the power supply VCC is supplied to the LowVth NMOS transistor 1 via the NMOS transistor 10, and this NMOS transistor 10 is PMO.
S transistor 12 and NMOS transistors 13-1
This is a point controlled by the circuit composed of 5.

Next, the operation will be described. First, PMO
S transistor 12 and NMOS transistors 13-1
The operation of the circuit configured by 5 will be described. PM
Since the gate of the OS transistor 12 is grounded (GND), the PMOS transistor 12 is normally on (normally on). Therefore, the voltage VCC is applied to the drain of the NMOS transistor 13.
The NMOS transistor 15 is turned on when VCC> Vth (NMOS13) + Vth (NMOS14) as in the case of the output voltage drop circuit of the first embodiment.

Therefore, the voltage VB of the drain (node B) of the NMOS transistor 13 is VB = VCC when VCC <Vth (NMOS13) + Vth (NMOS14) and VB = VCC when VCC> Vth (NMOS13) + Vth (NMOS14) -VD
It becomes S (PMOS12). Here, VDS (PMOS12) is a voltage drop in the PMOS transistor 12, and VDS (PMOS12) = (ON resistance of PMOS12) × (current flowing in NMOS15).

Based on this voltage VB, the voltage VC of the source (node C) of the NMOS transistor 10 is given by the following equation. VC = VB-Vth (NMOS10)

As described above, according to the buffer circuit of FIG. 9, the source potential of the LowVth NMOS transistor 1 becomes lower than that in the case of the buffer circuit of FIG. 1 (VCC). Here, the characteristics of the buffer circuit of FIG. 9 are basically the same as the characteristics of FIG. However, LowVth NMOS
Since the voltage applied to the transistor 1 becomes lower than VCC, the slope of the characteristic (graph 104) from V ₁ to VCC = 5V in FIG. 2 becomes gentler and the output VO
The difference is that H is further lowered.

As described above, according to the seventh embodiment, the VO
Since H becomes lower than that in the first embodiment, the current flowing through the output voltage drop circuit constituted by the NMOS transistors 3 to 5 becomes small. Therefore, the power consumption of the buffer circuit can be reduced. Furthermore, all the output drivers (transistors 1, 2, 10) of this buffer circuit are NMO.
Since it can be configured with an S transistor, there is no fear of latch-up unlike the case of a CMOS circuit.

The through current is the same as that of the NMOS transistor 1.
Although it also flows through the gate control circuit (transistors 12 to 15) of 0, this through current is small and the current consumption of the buffer circuit as a whole is small. Because this gate control circuit only controls the gate of the NMOS transistor 10, it is not necessary to increase the driving capability of each transistor, and therefore, the transistors 12 to 15 are smaller than the transistors 3 to 5 of the output voltage drop circuit in size. This is because the size can be reduced and the shoot-through current can be made sufficiently smaller than the shoot-through current of the output voltage drop circuit.

Example 8. The configuration of the seventh embodiment may be applied to the N-N type buffer circuit of the second embodiment.

FIG. 10 shows the structure of the buffer circuit according to the eighth embodiment. This circuit is a modification of the circuit of FIG. In FIG. 10, the gate 10 is a PMO.
Connected to the output terminal (node B) of the S transistor 12,
This is an NMOS transistor for reducing the power supply voltage applied to the NMOS transistor 2a. Reference numeral 12 is a PMOS transistor whose gate is grounded, 13 and 14 are diode-connected NMOS transistors, and 15 is an OE
Operates on the basis of signals, and NMOS transistors 13 and 14
It is an NMOS transistor that turns on / off the current that flows in. These NMOS transistors 13 to 15 are connected in series like the output voltage drop circuit of the first embodiment. One of the output terminals of the PMOS transistor is connected to the power supply VCC and the other is connected to the NMOS transistor 13.
Is connected to the output end of. Further, the NMOS transistors 2 to 5 are the same as those shown in FIG.

In the buffer circuit of FIG. 10 of the eighth embodiment, the NMOS transistors 10, 13 to 15 and PMO are provided.
Since the operation of the S-transistor 12 is the same as that of the seventh embodiment, the detailed description of the operation is omitted.

As described above, according to the buffer circuit of FIG. 10, the source potential of the NMOS transistor 2a becomes lower than that (VCC) of the buffer circuit of FIG. Therefore, the current flowing through the output voltage drop circuit composed of the NMOS transistors 3 to 5 becomes smaller than that in the case of FIG. 3, and the power consumption of the buffer circuit can be reduced. Furthermore, since all transistors are NMOS, L
A manufacturing process for the owVth NMOS transistor and a mask therefor are not necessary, so that the number of masks can be reduced and the manufacturing process can be omitted.

Example 9. In Example 7 above, the NMO
Voltage (power supply voltage) applied by connecting the S transistor in series with the output transistors 1 and 2 of the buffer circuit of FIG.
But instead of connecting two PMOS transistors connected in parallel to each other, the output transistor 1,
You may make it limit the electric current sent to 2.

FIG. 11 shows the structure of the buffer circuit according to the ninth embodiment. This buffer circuit is a modification of the buffer circuit shown in FIG. 9, and aims to reduce the power consumption of the buffer circuit by limiting the current flowing through the output voltage drop circuit. The difference between the buffer circuit of FIG. 11 and the buffer circuit of FIG. 9 is that the source of the LowVth NMOS transistor 1 is connected to the PMOS transistors 17 and 19 which are connected in parallel with each other, and the gate potential of the PMOS transistor 19 is predetermined. That is, it is controlled by the signal D that changes with the voltage. In FIG.
The LowVth NMOS transistor 1 and the NMOS transistors 2 to 5 are the same as those shown in FIG.

Next, the operation will be described. The signal D input to the gate of the PMOS transistor 19 is a signal that changes at a predetermined voltage. For example, the signal D is
It is assumed that the H level is set when VCC ≦ 5V and the L level is set when VCC> 5V. At this time, the PMOS transistor 19 is
It turns off when C ≦ 5V and turns on when VCC> 5V. On the other hand, the PMOS transistor 17 connected in parallel with this is always on (normally on). Note that the transistor 17
Since 19 and 19 are PMOS, the voltage applied to the source of the LowVth NMOS transistor 1 is VCC regardless of whether the PMOS transistor 19 is on or off.

If VCC≤5V, only PMOS transistor 17 is on. At this time, LowVthNMO
The current flowing through the S transistor 1 is smaller than that when the PMOS transistor 19 is on. That is, the current flowing through the output voltage drop circuit is the PMOS transistor 17
Limited by This allows LowVth NMOS
The voltage drop that occurs in the transistor 1 is limited to a constant value. The VCC-VOH characteristic at this time is as shown by a graph 102 in FIG. 12, for example.

On the other hand, when VCC> 5V, the PMOS transistor 19 is turned on based on the control signal D, and therefore Lo
The current that can flow in the wVth NMOS transistor 1 is VCC
It becomes larger than the case of ≦ 5V. Therefore, when VOH is large, the current flowing through the output voltage drop circuit becomes larger, and accordingly, the LowVth NMOS transistor 1
The voltage drop that occurs at is larger. From this, the VOH is the PMO as shown in 104c of FIG.
It is even lower than in the case of the straight line graph 102 at VCC> 5V when the S transistor 19 turns on. As described above, according to the VCC-VOH characteristic of FIG. 12, it is possible to prevent the VOH from exceeding 3.6V even if the VCC increases, and satisfy the 3.3V interface condition.

LowVth NMOS transistor 1
Must satisfy the condition of the following formula so that the 3.3V interface condition is satisfied when the power supply voltage is high (for example, VCC = 5.5V). VOH = VCC-Vth (NMOS1) ≤ 3.6V With VCC = 5.5V Vth (NMOS1) ≥ 1.9V

LowVthNMO of the buffer circuit of FIG.
VCC is applied to the source of the S-transistor 1. On the other hand, in the case of the buffer circuit of FIG.
A lower voltage is applied. Therefore, the buffer circuit of the ninth embodiment is characterized in that it can operate at a higher speed than the buffer circuit of the eighth embodiment (FIG. 10). Since the power supply current is limited by the PMOS transistors 17 and 19, the current flowing through the output voltage drop circuit configured by the NMOS transistors 3 to 5 is smaller than that in the case of FIG. 1, and the buffer circuit consumes less power. Electricity becomes possible.

In the ninth embodiment, LowVthN-N
Although the case of application to the type buffer circuit is shown, it is needless to say that the same can be applied to the NN type buffer circuit of the second embodiment.

Example 10. In Example 9 above, Lo
Two PMOS transistors connected in parallel with each other were connected to the source of the wVth NMOS transistor 1.
Not limited to this, three PMOS transistors connected in parallel may be connected.

FIG. 13 shows the structure of the buffer circuit according to the tenth embodiment. In FIG. 13, 17 is a PMOS transistor whose gate is grounded, 20 is a PMOS transistor controlled by a signal E, and 21 is a PMOS transistor controlled by a signal F. These three transistors are connected in parallel, and one end of the output is the power supply (VC
C), the other end is connected to the output end of the LowVth NMOS transistor 1. The LowVth NMOS transistor 1 and the NMOS transistors 2 to 5 are the same as those shown in FIG. The buffer circuit of FIG. 13 is characterized in that the VCC dependency of VOH is 2 based on the signals E and F.
It is a change in stages.

Next, the operation will be described. The signal E input to the gate of the PMOS transistor 20 is a signal that changes at a predetermined voltage. For example, the signal E is
It is assumed that the H level is set when VCC ≦ 5V and the L level is set when VCC> 5V. At this time, the PMOS transistor 20 is
It turns off when C ≦ 5V and turns on when VCC> 5V.

The signal F input to the gate of the PMOS transistor 21 is a signal that changes at a predetermined voltage different from the signal E. For example, the signal F is VCC
It is assumed that the H level is set when ≦ 4.5V and the L level is set when VCC> 4.5V. At this time, the PMOS transistor 21
It turns off when CC ≦ 4.5V and turns on when VCC> 4.5V. On the other hand, the PMOS transistor 17 connected in parallel with these is always on (normally on).

When VCC ≦ 4.5V, only the PMOS transistor 17 is on. Therefore, the VCC-VOH characteristic is as shown in FIG.
The graph 102 has a solid line portion.

On the other hand, in the case of 5V ≧ VCC> 4.5V, the PMOS transistor 21 is additionally turned on, so that the voltage drop amount in the LowVth NMOS transistor 1 increases and the VCC-VOH characteristic is the same as in the case of the ninth embodiment. The graph 104d in FIG. 14 is obtained.

If VCC> 5V, the PMO
Since the S transistor 20 is also turned on, LowVth
The amount of voltage drop in the NMOS transistor 1 increases,
The VCC-VOH characteristic is as shown by the graph 104e in FIG.

By the way, in the graph 104e, 3.3 is generated.
In order to satisfy the V interface condition,
Specifically, the size and threshold voltage Vth of the PMOS transistor 21, the NMOS transistors 3, 4, and 5 are adjusted based on the following conditional expressions. VOH = VCC-Vth (NMOS1) ≤ 3.6V With VCC = 5.5V Vth (NMOS1) ≥ 1.9V

Similarly, in the graph 104d, VOH ≦
If 3.3V is set, the PMOS is based on the following conditional expression.
The size of the transistor 20 and the NMOS transistors 3, 4, 5 and the threshold voltage Vth are adjusted. VOH = VCC-Vth (NMOS1) ≤ 3.3V With VCC = 5.0V Vth (NMOS1) ≥ 1.7V

As a result, the VCC-VOH characteristic of the buffer circuit of the tenth embodiment becomes as shown in FIG.
VOH does not exceed 3.6V even if is increased,
Satisfies 3.3V interface condition.

According to the tenth embodiment, VCC of VOH
By changing the dependency in two steps, VCC is 5V
In the above cases, the increase of VOH can be suppressed further (the portion of the graph 103e in FIG. 14). Therefore, Example 1
The VCC dependency of VOH can be made smaller than that in the above case. As a result, a more stable 3.3V interface circuit can be realized.

LowVth Since the voltage applied to the source of the NMOS transistor 1 is VCC, higher speed operation is possible, and the current flowing through the output voltage drop circuit composed of the NMOS transistors 3 to 5 is smaller than that in the case of FIG. This is the same as the case of the ninth embodiment in that the power consumption of the buffer circuit can be reduced.

In the tenth embodiment, LowVthN-
The case of application to the N-type buffer circuit is shown.
Needless to say, the same can be applied to the N-N type buffer circuit.

Example 11. 2. A transistor that pulls up the output level when the power supply voltage is low is connected to the output terminal of the buffer circuit of the first embodiment, and not only when VCC = 5.0V but also when VCC = 3.3V. You may comprise so that the conditions of 3V interface may be satisfy | filled.

The structure of the buffer circuit of the eleventh embodiment is shown in FIG. In the figure, 24 has one end of the output VCC
Connected to and the other end connected to the output DOUT
It is a transistor. The PMOS transistor 24 is controlled by a signal G supplied from a circuit (not shown). L
The owVth NMOS transistor 1 and the NMOS transistors 2 to 5 are the same as those shown in FIG.

Next, regarding the operation, VCC- shown in FIG.
Description will be made based on the characteristic diagram of the signal G and the VCC-VOH characteristic diagram shown in FIG. In addition, in FIG. 17, a rectangle AB
The area of D'C 'is the 3.3V interface area for VCC = 5V, and the area of the rectangular EFGH is VCC = 3.
The 3.3V interface areas for 3V are shown respectively.

In the buffer circuit of the eleventh embodiment,
When VCC is high, that is, in the range of 4.5V to 5.5V, the signal G which is the gate signal of the PMOS transistor 24 is at the H level as shown in FIG.
The transistor 24 is off. Therefore, the operation of the buffer circuit of the eleventh embodiment at this time is the same as the operation of the buffer circuit of the first embodiment. In other words, the characteristic of this buffer circuit becomes a graph 102 near 4.5V and a graph 10 near 5.5V as shown in FIG.
The graph 104 has a gentler slope than 2, and VOH is in the range of 2.4V to 3.6V. Therefore, 3.
Satisfies the 3V interface condition.

By the way, when VCC becomes low, VOH becomes T
It fell below the TL specification of 2.4 V, and could not satisfy the standard. For example, when VCC = 3.3V, VOH <VCC-Vth (NMOS1) = 3.3V-1.5V = 1.8V <2.4V, which is far below the standard value of 2.4V. So VO
When H is likely to fall below 2.4V, the PMOS transistor 24 is turned on to pull up the level of DOUT.

Specifically, VCC = 3.0V to 3.6V
In the range, the signal G is set to the L level as shown in FIG. This turns on the PMOS transistor 24 and pulls up the output DOUT. At this time VOH
Is 3.0V to 3.6V as shown in the graph 105 of FIG.
It is 3.3V because it is in the range of and within the rectangular EFHG.
Satisfies the interface conditions. In addition, ± 10% of the regular power supply voltage 3.3V, that is, VCC = 3.0V to 3.V.
It is only necessary to satisfy the 3.3V interface condition at 6V, and it is not necessary to satisfy it at 3.6V to 4.5V outside the power supply voltage.

The buffer circuits of the first to tenth embodiments are V
Although the 3.3V interface condition could be satisfied only when CC = 5V, the buffer circuit of the eleventh embodiment further has an excellent performance of satisfying the 3.3V interface condition even when VCC = 3.3V. Have.

Example 12. The pull-up circuit (PMOS transistor 24) of the eleventh embodiment may be applied to the buffer circuit of the second embodiment. The structure of the buffer circuit in this case is shown in FIG. Since the operation of this circuit is the same as that of the eleventh embodiment, its explanation is omitted.

According to the twelfth embodiment, as compared with the case of the eleventh embodiment, a mask for manufacturing the LowVth transistor is unnecessary, the number of masks can be reduced, and the step can be omitted.

Example 13. Although the output voltage is reduced by using the output voltage drop circuit in the above embodiment, the output voltage may be pulled up to a constant value by using the down converter circuit and the bipolar transistor.

FIG. 19 is a block diagram of the output buffer circuit of the thirteenth embodiment. Reference numerals 2a and 2b are NMOS transistors connected in series with each other, and this connection portion serves as an output terminal DOUT. The other end of the output end of the NMOS transistor 2a is grounded, and the other end of the output end of the NMOS transistor 2b is connected to VCC. The gates of the NMOS transistors 2a and 2b are connected to a circuit (not shown). 27 is a CMOS inverter driven by the gate signal of the NMOS transistor 2b, 28 is a bipolar transistor whose output end is connected to VCC and which receives the reference voltage VREF output from the down converter circuit 34 as a base, 29 is an output end One end of DO
It is a PMOS transistor connected to the UT and driven by the CMOS inverter 27. The bipolar transistor 28 and the PMOS transistor 29 are connected in series.

Reference numeral 34 is a down converter circuit for generating the reference voltage VREF. 341 and 342 are NMO
S transistors, 343 to 349 are PMOS transistors, 320 is an operational amplifier, and 321 is a resistor. Here, the PMOS transistors 346, 348, 349 are P
Functions as MOS ON resistance, and each resistance value is RT
R, R1 and R2.

Next, the operation will be described. When the NMOS transistor 2a is off and the NMOS transistor 2b is on, DOUT becomes H level. At this time, NM
Since the gate potential of the OS transistor 2b is at H level, the output of the CMOS inverter 27 is at L level.
In response to this, the PMOS transistor 29 is turned on. By the way, the down converter circuit 34 outputs a constant reference voltage VREF as described later. Since this reference voltage is input to the base of the bipolar transistor 28, the voltage applied to the drain of the PMOS transistor 29 becomes VREF-VBE with the base-emitter voltage of the bipolar transistor 28 being VBE.
Therefore, the voltage of the H level output VOH = VREF-V
It becomes BE and becomes constant regardless of the power supply voltage VCC.

Therefore, if VREF and VBEH are selected so as to satisfy the following equation 2.4V <VREF-VBE <3.6V, the buffer circuit of FIG. 19 satisfies the condition of 3.3V interface. For example, as shown in FIG.
Since EF becomes constant (4.0 V) when VCC = 4.5 V or more, VOH becomes VOH = 3.2 V when VCC = 4.5 V or more as shown in FIG. 21, and becomes constant regardless of VCC. It should be noted that the reason why VREF is constant when VCC = 4.5V or more is that the minimum VC is set when VCC = 5V.
This is because C becomes 4.5V. Note that VCC = 3.3
When it is necessary to keep VOH constant even at V,
It is sufficient to keep VREF constant at 3.0 V or higher.

Since the buffer circuit of FIG. 19 does not have the output voltage drop circuit, the shoot-through current can be reduced. Thereby, the power consumption of the buffer circuit can be reduced.

The circuit shown in FIG. 19 has a structure of LowVthNMO.
It can be applied to a LowVth N-N type output buffer circuit composed of an S transistor and an NMOS transistor and has the same effect.

There is no particular limitation on the bipolar transistor. Therefore, for example, by using a parasitic bipolar transistor manufactured by a CMOS process, a mask for the bipolar transistor is not needed and the mask is not increased. Further, since the output stage is driven by the bipolar transistor, the address access can be speeded up.

Next, the operation of the down converter circuit (constant voltage generating circuit) 34 of FIG. 19 will be described. PMOS
Channel width-to-length ratio W / L = Wp / Lp of transistors 343, 344, and 345, threshold voltage Vth = V
thp. Also, the NMOS transistors 341, 3
42 W / L = Wn / Ln.

VGS = I · R (1) I = A · (Wp / Lp) · (VGS-Vthp) ² (2) Here, VGS is between the gate and the source of the PMOS transistor 343. The voltage, I is the current flowing through the PMOS transistor 343. In addition, as shown in FIG.
1. The current flowing through the PMOS transistor 345 is also I. R is the resistance value of the resistor 321, A is a constant, and Wp is PMO.
Channel width of S transistor, Lp is channel length of PMOS transistor, Vthp is PMOS transistor 3
43 threshold voltage.

By substituting (1) into (2), I = A (Wp / Lp)  (IR-Vthp) ² (3) is obtained. Solving (3) for I · R, I · R = Vthp + [I / {A · (Wp / Lp)}]
^1/2 where Wp / Lp >> Wn / Ln, so I becomes very small, and therefore [I / {A · (Wp / Lp)}] ^1/2 ≈0
Becomes Therefore, I = Vthp / R (4)

Therefore, VREF1 = IRTR = VthpRTR / R = R2VREF / (R1 + R2) Here, VREF1 is an input signal of the operational amplifier 320, RTR is an ON resistance of the PMOS transistor 346, VREF is an output reference voltage of the down converter circuit 34, R1 is an ON resistance of the PMOS transistor 348, and R1.
Reference numeral 2 is the on resistance of the PMOS transistor 349.

Therefore, VREF = VREF1 (R1 + R2) / R2, and VREF is constant regardless of the power supply voltage VCC. The characteristics shown in FIG. 20 can be obtained by appropriately setting R1, R2, Vthp, RTR, R and the like. In addition,
In FIG. 20, VREF changes when VCC <4.5V, but since VCC is a constant value VREF = 4.0V when VCC = 4.5V to 5.5V, there is no problem in the operation of this buffer circuit. When applied in a wider VCC range, the circuit constant of the down converter circuit 34 may be appropriately changed so that VREF becomes constant in a desired range.

Example 14. In the thirteenth embodiment, the pull-up circuit includes a bipolar transistor and a PMO.
Although the S transistor and the S transistor are connected in series, the present invention is not limited to this and may be a bipolar transistor.

FIG. 22 shows the structure of the buffer circuit according to the fourteenth embodiment. 30 is a PMOS transistor, 31
Is an NMOS transistor, 32 is a bipolar transistor in which one of the output terminals is connected to the power supply VCC and the other is connected to the output terminal DOUT, 33 is the NMOS transistor 2
It is a CMOS inverter circuit that inverts the gate input signal of b. The gate of the PMOS transistor 30 has a CM
A signal obtained by inverting the gate input signal of the NMOS transistor 2b is input via the OS inverter circuit 33.
The gate of the NMOS transistor 31 has an NMO
The gate input signal of the S transistor 2b is input. P
The output end of the MOS transistor 30 and the output end of the NMOS transistor 31 are connected in parallel, and switch whether to input the reference voltage VREF from the down converter circuit 34 to the base of the bipolar transistor 32. The NMOS transistors 2a and 2b are the same as those shown in FIG.

Next, the operation will be described. When an H level signal is output from DOUT, that is, when the gate input signal of the NMOS transistor 2b is H level, P
The gate input signal of the MOS transistor 30 is L level, and the gate input signal of the NMOS transistor 31 is H level. Therefore, these two transistors are both turned on, and the reference voltage VREF is supplied to the base of the bipolar transistor 32.

At this time, the DOUT output level is VOH
= VREF-VBE, so that VREF and VBE are selected so as to satisfy the following equation 2.4V <VREF-VBE <3.6V, as in the case of the thirteenth embodiment.
The buffer circuit of FIG. 22 satisfies the condition of 3.3V interface. For example, as shown in FIG.
= 4V, VOH = 3.2V, which is constant regardless of VCC.

Regarding the buffer circuit of the fourteenth embodiment,
As in the case of the thirteenth embodiment, since there is no output voltage drop circuit, there is no current path therefor, and power consumption can be reduced. Further, unlike the case of the thirteenth embodiment, the buffer circuit of the fourteenth embodiment does not have a PMOS transistor added to the emitter of the bipolar transistor 32. Therefore, since there is no resistance component between the emitter and the output DOUT, the effect that the address access becomes faster can be obtained.

Note that the circuit of FIG. 22 has a LowVthNMO
It can be applied to a LowVth N-N type output buffer circuit composed of an S transistor and an NMOS transistor and has the same effect.

There is no particular limitation on the bipolar transistor. Therefore, for example, by using a parasitic bipolar transistor manufactured by a CMOS process, a mask for the bipolar transistor is not needed and the mask is not increased. Further, since the output stage is driven by the bipolar transistor, the address access can be speeded up.

[0137]

As described above, according to the invention of claim 1, an output circuit for outputting a signal of a voltage corresponding to the power supply voltage based on an input signal, and an output terminal of the output circuit, the power supply being connected to the output circuit. An output voltage drop circuit that lowers the voltage of the output signal of the output circuit by causing a current to flow when the voltage exceeds a predetermined voltage is provided.
Even at V, the voltage of the output signal can be lowered to satisfy the 3.3V interface condition.

Further, according to the invention of claim 2, there is provided a power supply voltage adjusting circuit for adjusting the output voltage corresponding to the power supply voltage, and the power supply of the output circuit is supplied from the power supply voltage adjusting circuit. Therefore, by lowering the power supply voltage supplied to the output circuit, the current flowing through the output voltage drop circuit can be reduced and the power consumption can be reduced.

According to a third aspect of the present invention, the power supply voltage adjusting circuit is configured such that a control voltage generating circuit for generating a control voltage corresponding to the power supply voltage and one of the output terminals are connected to the power supply. Since it is composed of a transistor that outputs a voltage lower than the power supply voltage, the power consumption can be reduced with a simple configuration.

Further, according to the invention of claim 4, there is provided a power supply current adjusting circuit for adjusting the output current in accordance with the power supply voltage, and the power supply of the output circuit is supplied from the power supply current adjusting circuit. Therefore, by limiting the current supplied to the output circuit, the current flowing through the output voltage drop circuit can be reduced and the power consumption can be reduced.

According to the invention of claim 5, the power supply current adjusting circuit is provided with a transistor that is always on when a power supply voltage is applied, and an on state and an off state with a predetermined power supply voltage. Since the transistors that switch between and are connected in parallel, the power consumption can be reduced with a simple configuration.

According to the invention of claim 6, further,
Since an output voltage raising circuit that is connected to the output terminal of the output circuit and that raises the voltage of the signal output by the output circuit by supplying power when the power source voltage falls below a predetermined voltage is provided, The 3.3V interface condition can be satisfied not only when the power supply voltage is 5V but also when the power supply voltage is 3.3V.

According to a seventh aspect of the invention, the first diode-connected first output diode is connected to the output voltage drop circuit, which allows a current to flow when the applied voltage exceeds a predetermined voltage.
And a second transistor that is connected in series with the first transistor and controls the on / off of the current based on a control signal from the outside, so that the output voltage drop circuit receives the current only when necessary. Can be flowed, and power consumption can be reduced.

Further, according to the invention of claim 8, the diode-connected first output voltage drop circuit is configured to flow a current when the applied voltage exceeds a predetermined voltage.
And a second transistor that is connected in series with the first transistor and controls the on / off state of the current based on the input signal of the output circuit. Therefore, the output voltage drop circuit is provided only when necessary. A current can be passed to reduce power consumption, and the control signal and the input signal of the output circuit are made common to reduce the load of the control signal, which enables high-speed operation.

Further, according to the invention of claim 9, since the output voltage drop circuit is composed of a diode-connected transistor that causes a current to flow when the applied voltage exceeds a predetermined voltage, it is simple. An output voltage drop circuit can be realized with such a configuration.

Further, according to the invention of claim 10, an output circuit for outputting a signal of a voltage corresponding to the power supply voltage based on the input signal, a reference voltage generating circuit for generating a predetermined reference voltage, and the above-mentioned output. Since an output voltage maintaining circuit that is connected to the output terminal of the circuit and supplies a constant voltage based on the reference voltage output by the reference voltage generating circuit to make the voltage of the output signal of the output circuit constant, The power consumption can be reduced by saving the current flowing through the output voltage drop circuit, which is not required.

According to the eleventh aspect of the present invention, the output voltage maintaining circuit includes a switch circuit for disconnecting the reference voltage output from the reference voltage generating circuit based on the input signal of the output circuit, and an output terminal. Since one is connected to the power supply and the other is connected to the output terminal of the output circuit and is composed of a bipolar transistor that operates based on the output of the switch circuit, an output voltage drop circuit is not required and the current flowing through it By saving the power consumption, the power consumption can be reduced and the operation speed of the circuit can be further increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a buffer circuit according to a first embodiment of the present invention.

FIG. 2 is an output characteristic diagram of the buffer circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a buffer circuit according to a second embodiment of the present invention.

FIG. 4 is an output characteristic diagram of the buffer circuit according to the second embodiment of the present invention.

FIG. 5 is a configuration diagram of a buffer circuit according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of a buffer circuit according to a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a buffer circuit according to a fifth embodiment of the present invention.

FIG. 8 is a configuration diagram of a buffer circuit according to a sixth embodiment of the present invention.

FIG. 9 is a configuration diagram of a buffer circuit according to a seventh embodiment of the present invention.

FIG. 10 is a configuration diagram of a buffer circuit according to an eighth embodiment of the present invention.

FIG. 11 is a configuration diagram of a buffer circuit according to a ninth embodiment of the present invention.

FIG. 12 is an output characteristic diagram of the buffer circuit according to the ninth embodiment of the present invention.

FIG. 13 is a configuration diagram of a buffer circuit according to a tenth embodiment of the present invention.

FIG. 14 is an output characteristic diagram of the buffer circuit according to the tenth embodiment of the present invention.

FIG. 15 is a configuration diagram of a buffer circuit according to an eleventh embodiment of the present invention.

FIG. 16 is a control signal G according to the eleventh embodiment of the present invention.
FIG.

FIG. 17 is an output characteristic diagram of the buffer circuit according to the eleventh embodiment of the present invention.

FIG. 18 is a configuration diagram of a buffer circuit according to a twelfth embodiment of the present invention.

FIG. 19 is a configuration diagram of a buffer circuit according to a thirteenth embodiment of the present invention.

FIG. 20 is a characteristic diagram of a reference voltage output by a down converter circuit according to a thirteenth embodiment of the present invention.

FIG. 21 is an output characteristic diagram of the buffer circuit according to the thirteenth embodiment of the present invention.

FIG. 22 is a configuration diagram of a buffer circuit according to Embodiment 14 of the present invention.

FIG. 23 is a configuration diagram of a conventional N-N type output buffer circuit.

FIG. 24 is a configuration diagram of a conventional LowVth N-N type output buffer circuit.

FIG. 25 is a configuration diagram of a conventional P-N type output buffer circuit.

FIG. 26 is an output characteristic diagram of a conventional output buffer circuit.

[Explanation of symbols]

1 LowVth NMOS transistor, 2-5 NMO
S-transistor, 7, 8 NOR circuit, 10 NMOS
Transistor, 12 PMOS transistor, 13-1
5 NMOS transistors, 17, 19-21, 24
PMOS transistor, 27 Inverter circuit, 28
Bipolar transistor, 29 PMOS transistor, 30 PMOS transistor, 31 NMOS transistor, 32 bipolar transistor, 33 inverter circuit, 34 down converter circuit.

Claims (11)

[Claims] 1. An output circuit for outputting a signal of a voltage corresponding to a power supply voltage based on an input signal, and an output circuit connected to an output terminal of the output circuit, which supplies a current when the power supply voltage exceeds a predetermined voltage. An output buffer circuit including an output voltage drop circuit that lowers the voltage of the output signal of the output circuit by flowing the output voltage. 2. The output according to claim 1, further comprising a power supply voltage adjusting circuit that adjusts an output voltage corresponding to a power supply voltage, and the power of the output circuit is supplied from the power supply voltage adjusting circuit. Buffer circuit. 3. The power supply voltage adjusting circuit, wherein a control voltage generating circuit for generating a control voltage corresponding to the power supply voltage and one of the output terminals are connected to a power supply, and a voltage lower than the power supply voltage is output based on the control voltage. 3. The output buffer circuit according to claim 2, wherein the output buffer circuit comprises 4. The output according to claim 1, further comprising a power supply current adjusting circuit that adjusts an output current according to a power supply voltage, and the power supply of the output circuit is supplied from the power supply current adjusting circuit. Buffer circuit. 5. The power supply current adjusting circuit is configured such that a transistor that is always on when a power supply voltage is applied and a transistor that switches between an on state and an off state at a predetermined power supply voltage are connected in parallel. The output buffer circuit according to claim 4, wherein the output buffer circuit is configured as described above. 6. An output voltage connected to the output terminal of the output circuit, which raises the voltage of the signal output by the output circuit by supplying power when the power supply voltage falls below a predetermined voltage. The output buffer circuit according to claim 1, further comprising a rising circuit. 7. The output voltage drop circuit is connected in series with a diode-connected first transistor that causes a current to flow when the applied voltage exceeds a predetermined voltage, and the first transistor. 7. The output buffer circuit according to claim 1, further comprising: a second transistor that controls on / off of a current based on a control signal from the outside. 8. The output voltage drop circuit is connected in series with a first diode-connected transistor that causes a current to flow when the applied voltage exceeds a predetermined voltage, and the first transistor. 7. A second transistor for controlling on / off of a current based on an input signal of the output circuit, and a second transistor.
The output buffer circuit according to any one. 9. The output voltage drop circuit comprises a diode-connected transistor that causes a current to flow when the applied voltage exceeds a predetermined voltage. The output buffer circuit according to any one. 10. An output circuit that outputs a signal of a voltage corresponding to a power supply voltage based on an input signal, a reference voltage generation circuit that generates a predetermined reference voltage, and an output terminal of the output circuit, An output buffer circuit comprising: an output voltage maintaining circuit for making a voltage of an output signal of the output circuit constant by supplying a constant voltage based on a reference voltage output from the reference voltage generating circuit. 11. A switch circuit which connects and disconnects the output voltage maintaining circuit with a reference voltage output from the reference voltage generating circuit based on an input signal of the output circuit; 11. The output buffer circuit according to claim 10, further comprising a bipolar transistor connected to the output terminal of the output circuit and operating based on the output of the switch circuit.