JPH0895942A - One-chip microcomputer - Google Patents

Abstract

PURPOSE: To provide a one-chip microcomputer which is suitable for portable electronic equipment using a battery and effectively utilizes the merit of a mask ROM and an EEPROM. CONSTITUTION: A mask ROM 1 for storing data with mask processing and an EEPROM 2 for writing/reading data are integrated on the same chip, the mask ROM 1 can be accessed by address data within the first range of a program counter 3, and the EEPROM 2 can be accessed by address data within the second range of the program counter 3. Then, data to be used for a long time or never to be changed, are stored in the mask ROM 1, and data to be used in a short time or to be changed are stored in the EEPROM 2. Thus, the one-chip microcomputer, which can easily change a program and reduces the power consumption, can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer suitable for use in battery-powered electronic equipment.

[0002]

2. Description of the Related Art Generally, a one-chip microcomputer has a built-in ROM in which program data for controlling operation is stored. In this ROM, a mask ROM for writing program data by mask processing,
There is an EEPROM or the like that enables writing and reading of program data by electrical processing, and either R
The OM is integrated on one chip, and 1 is obtained based on the result of decoding the program data read from these ROMs.
It controlled the operation of the chip microcomputer.

[0003]

However, when the mask ROM is built in the one-chip microcomputer, the power consumption can be suppressed due to the structure of the mask ROM, but the program data once written cannot be rewritten. In order to change the program data, a new mask has to be created again and printed on a new one chip, which complicates the work process and completes a new one-chip microcomputer with the changed program. There was a problem that it took a lot of time. On the other hand, the one-chip microcomputer has EEPRO
When M is built in, rewriting of program data can be easily executed by electrical processing due to the structure of the EEPROM, but it consumes a large amount of power and is a 1-chip microcomputer with a built-in EEPROM for portable electronic equipment that uses a battery. There was a problem that was unsuitable.

Therefore, the present invention is suitable for a portable electronic device using a battery, such as a mask ROM and EEPRO.
It is an object of the present invention to provide a one-chip microcomputer that takes advantage of the advantages of M.

[0005]

The present invention has been made to solve the above problems, and is characterized in that it is accessed by address data in the first range of the program counter in advance. A first non-volatile memory in which data is written by a mask process, a second non-volatile memory in which data can be written and read and which is accessed by address data in a second range of the program counter; Latch circuit for latching read data of the non-volatile memory, second latch circuit for latching read data of the second non-volatile memory, and upper x bits of address data output from the program counter For selectively sending the latch output of either the first or second latch circuit to the data bus. A control unit for generating a No. 択信, 1
The point is that it is integrated on a chip.

[0006]

According to the present invention, the first non-volatile memory for storing data by mask processing and the second non-volatile memory capable of writing and reading data are integrated on the same chip, and the program counter The first non-volatile memory can be accessed by the first range of address data, and the second non-volatile memory can be accessed by the second range of address data of the program counter. Then, the first non-volatile memory stores data that is not used or changed for a long time, and the second non-volatile memory stores data that may be used or changed for a short time. As a result, it is possible to provide a low power consumption one-chip microcomputer in which the program can be easily changed.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a one-chip microcomputer of the present invention. In FIG. 1, (1) is a mask ROM (first non-volatile memory), which stores n-bit program data by burning a mask on a chip, and changes the program data once written. Is something you cannot do without recreating a new mask. Due to the structure of the mask ROM (1), it is preferable to write program data that consumes less power, is used for a relatively long time, or is not changed in the future. (2) is an EEPROM in which writing or reading of n-bit program data can be repeated by electrical processing. The EEPROM
Since (2) consumes a large amount of power due to its structure, it is desirable to use it only for a short time or to write program data that may be changed in the future. (3) is a program counter, which generates m-bit address data. That is, the program counter (3) generates 2 ↑ m (2 to the m-th power) types of address data. The mask ROM (1) is accessed by the address data belonging to the first range in the first half, and the latter half. Second
The EEPROM (2) is accessed with the address data belonging to the range. Here, the mask ROM (1) and the EEPR
When accessing OM (2), it is assumed that the upper x bits of the address data are different. For example, if the address data is 8 bits, the mask ROM (1) and the EEPROM (2) can access 256 (= 2 ↑ 8) addresses, but here, the mask ROM (1) and the EEPROM (2) are accessible. , Both have a storage capacity of 128 addresses each, only the most significant bit (upper 1 bit) of the address data is different. Specifically, when accessing the mask ROM (1), the most significant bit of the address data becomes "0", and when accessing the EEPROM (2), the most significant bit of the address data becomes "1". . (4) and (5) are mask ROMs (1), respectively
And a latch circuit for latching n-bit program data read from the EEPROM (2). (6)
Is a control unit, a mask ROM (1) and an EEPROM
Different upper x bits are discriminated when (2) is accessed, "1" is output when the address data is the content that accesses the mask ROM (1), and the address data is the content that accesses the EEPROM (2). At the time of, "0" is output. The NAND gate (7) is a gate for controlling output of the output of the latch circuit (4) to a data bus which will be described later, and a discrimination output from the control unit (6) is applied to one input terminal. An output permission signal, which will be described later, is applied to the other input terminal. Similarly, NAND
The gate (8) is a gate for controlling output of the output of the latch circuit (5) to the data bus, and the discrimination output from the control unit (6) is provided to the inverter (9) at one input terminal. And the output enable signal is applied to the other input terminal. NOR gates (10) are provided in a number of n corresponding to each n-bit output of the latch circuit (4), and one input terminal of each of the n NOR gates (10) is provided in the latch circuit (4). The output of the NAND gate (7) is commonly applied to the other input terminal, which is connected to each n-bit output. Similarly, NOR gate (11)
Is n in correspondence with each n-bit output of the latch circuit (5).
One of the n NOR gates (11) has one input terminal connected to each n-bit output of the latch circuit (5), and the other input terminal has a common output of the NAND gate (8). Is being applied. The gate of the N-channel type MOS transistor (12) is a NOR gate (10).
Of which the drain is connected to one data bus (13) for one bit, and the source is grounded. Similarly, N-channel type MOS transistor (1
In 4), the gate is connected to the output terminal of the NOR gate (11), the drain is connected to the data bus (13), and the source is grounded. P channel type MO
The precharge signal is applied to the gate of the S transistor (15) through the inverter (16), the drain is connected to the data bus (13), and the source is the power supply Vd.
It is connected to d. The P-channel type MOS transistor (17) has its gate connected to the data bus (13) via the inverter (18), its drain connected to the data bus (13), and its source connected to the power supply Vdd. Here, the P-channel MOS transistor (17) and the inverter (18) form a holding circuit. Since each output of the latch circuits (4) and (5) is n bits, the N channel type MOS transistor (12)
(14), data bus (13), P-channel type MOS
Transistors (15) (17) and inverter (1
6) (18) consists of latch circuits (4) (5)
It is assumed that there are n in number according to the number of bits.

The operation of FIG. 1 will be described below with reference to the time chart of FIG. It should be noted that one machine cycle for operating the one-chip microcomputer will be described as comprising three cycles T1 to T3 of the clock signal. Further, it is assumed that the address data output from the program counter (3) is changed in synchronization with the falling edge of the clock signal in the T1 period. Further, the latch signal for the latch circuits (4) and (5) to latch is generated as a high level only during the high level period of the T1 period of the clock signal.
Furthermore, the output enable signal for sending the latched output of the latch circuits (4) and (5) to the data bus (13) is output as a high level during the low level period of the T1 period of the clock signal.

First, m-bit address data a is generated from the program counter (3), and the address data a is generated.
If a predetermined address of the mask ROM (1) is accessed by, the n-bit program data A is read from this address of the mask ROM (1) (it is assumed that the program data A corresponds to the address data a). ). The program data A is latched in the latch circuit (4) at the timing when the latch signal becomes high level. On the other hand, in the control section (6), the most significant bit "0" of the program data a is discriminated and a discrimination signal of "1" is output, and the discrimination signal is the NAND gate (7).
Applied to one of the input terminals. When the output enable signal goes high immediately after the latch signal, the output signal of the NAND gate (7) goes low and the output of the NOR gate (10) depends on the n-bit output of the latch circuit (4). It will be. On the other hand, as the precharge signal, a clock signal is applied, and the P-channel type MOS transistor (15) is turned on during the high level period of the clock signal, and the P-channel type MOS transistor (17) is accordingly turned on. The data bus (13) is kept on and precharged to the high level. Depending on the output of the NOR gate (10), N
When the channel type MOS transistor (12) is turned on / off, the level of the data bus (13) changes. For example, when the predetermined 1-bit output of the latch circuit (4) is "0", the output of the NOR gate (10) becomes high level and the N-channel type MOS transistor (13).
Is turned on, and the data bus (13) is pulled down from the high-level precharge state to the low level. The data bus (13) is a predetermined 1-bit output of the latch circuit (4) "0". Is output. This operation is performed by the program counter (3).
The same applies to the case of accessing M (2), so the description of the operation in this case will be omitted.

As described above, on one chip, the mask ROM (1) and the EE are provided by one program counter (3).
Since the PROM (2) is configured to be accessible, it is not necessary to use the mask ROM (1) for a long time or rewrite it in the future when using the built-in one-chip microcomputer in a portable electronic device. By writing the program data in advance and using it in the EEPROM (2) for a short time or writing it in the future, the power consumption can be reduced and the program can be easily changed in a short time. The effect that can be obtained is obtained.

The mask ROM (1) has an EEPROM.
By writing the program data for instructing the rewriting of the program data of (2), the program data of the EEPROM (2) can be changed inside the one-chip microcomputer.

[0012]

According to the present invention, a first non-volatile memory for storing data by mask processing and a second non-volatile memory capable of writing and reading data are integrated on the same chip, and a program is stored. The first non-volatile memory can be accessed by the first range address data of the counter, and the second non-volatile memory can be accessed by the second range address data of the program counter. And
By storing in the first non-volatile memory data that is not used or changed for a long time, and by storing in the second non-volatile memory data that may be used or changed for a short time. It is possible to provide an advantage that it is possible to provide a low power consumption one-chip microcomputer in which the program can be easily changed.

[Brief description of drawings]

FIG. 1 is a diagram showing a one-chip microcomputer of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

[Explanation of symbols]

 (1) Mask ROM (2) EEPROM (3) Program counter (6) Control unit

Claims (2)

[Claims] 1. A first non-volatile memory in which data is written in advance by mask processing, which is accessed by address data in a first range of a program counter, and is accessed by address data in a second range of the program counter. A second non-volatile memory capable of writing and reading data, a first latch circuit for latching read data of the first non-volatile memory, and latching read data of the second non-volatile memory To discriminate the upper x bits of the address data output from the second latch circuit and the program counter, and selectively output the latch output of either the first latch circuit or the second latch circuit to the data bus. A one-chip micro computer characterized by integrating a control unit for generating a selection signal of Over data. 2. The first memory is used for masking to write data that will not be used or changed for a long time, and the second memory will be used or changed for a short time. The one-chip microcomputer according to claim 1, wherein certain data is written.