JPH0895929A - Multiprocessor system - Google Patents

Abstract

PURPOSE: To provide a multiprocessor system for preventing time-out from occurring even for a CPU, to which the use of a bus is not permitted, when plural CPU simultaneously request the bus and the time-out occurs at the CPU that possesses the bus. CONSTITUTION: Concerning the multiprocessor system with which the right of bus use is arbitrated between the CPU and a bus arbitrating circuit, a time- out detecting circuit 3 composed of a counter and equipped with first time-out time T1 is installed in the bus arbitrating circuit 1 and time-out detecting circuits 4A-4C composed of counters and equipped with second time-out time T2 are similarly installed at the respective CPU as well. When the CPU more than two simultaneously use the bus, the first time-out time is set shorter than the second time-out time. Thus, the CPU requesting the bus is released from the bus within the timer set time inside the bus arbitrating circuit 1 so that one CPU can not occupy the bus for a long time, and the other CPU can use the bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system having a bus timeout detection circuit.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional multiprocessor system in which a plurality of arithmetic processing circuits (hereinafter referred to as CPUs) composed of a microprocessor and peripheral circuits are connected to a system bus. In this conventional example, a plurality of substrates 8 such as CPUs are connected to the system bus 10 via connectors 9 and mounted in a case 11.

Usually, in a multiprocessor system, one system bus is used by a plurality of CPUs. Therefore, the bus arbitration and the CPU determine the CPUs that can use the system bus so that there is no competition for the use of the system bus. It is necessary to detect the bus time-out when the request is made and the request cannot be acquired.

Such bus arbitration and bus timeout detection will be described with reference to FIG. This figure shows a multiprocessor system in which four CPUs are connected to a system bus. That is, each arithmetic processing circuit 12A, 12
B, 12C, 12D (CPU-1, CPU-2, CPU
-3, CPU-4) are almost the same circuits, and are respectively bus arbitration circuits 13A, 13B, 13C, 13D (ARB).
-1, ARB-2, ARB-3, ARB-4) and priority determination circuits 14A, 14B, 14C, 14D (PRI-
1, PRI-2, PRI-3, PRI-4) and timeout detection circuits 15A, 15B, 15C, 15D (TI
ME-1, TIME-2, TIME-3, TIME-
4) is provided.

Bus arbitration circuits 13A, 13B, 13C, 1
3D sends a bus request signal RQ to the bus request bus RQ.
1, RQ2, RQ3, RQ4 are output, priority signals PR1, PR2, PR3, PR4 are input from the priority determination circuits 14A, 14B, 14C, 14D, respectively, and the bus busy signal bus BUSY is in use. It is connected so as to output the signal and input this BUSY at the same time, and the use permission signals EN1, EN2, EN3, EN4
Is output.

As described above, the bus arbitration circuits 13A to 13D for performing bus arbitration of the system bus include the CPUs 12A to 1D, respectively.
In the 2D, a plurality of bus request lines are provided in the system bus RQ, and the priority determination circuit 14 is provided for each CPU.
A to 14D are provided, and which CPU has the highest priority is determined by each C
Each CPU individually determines whether or not it is the highest priority in the PU.

Bus timeout detection circuits 15A-1
5D is composed of, for example, a ripple counter, and is controlled by a clock signal and a clear signal. The output of the counter is 2
Different kinds of times can be set, which are set by the short-circuit pin.
As the clock signal, the clock signal of the microprocessor is input to CLK, and the counter counts up in synchronization with this clock signal. The clear signal is always high
Since h is input and the counter outputs low in response to this, the time-out signal TMO is not counted up.
Do not output UT. When the CPU acquires the bus as described above and reads / writes (R / W) another CPU, the clear signal is input as low, the counter starts counting up at the rising edge of the clock signal, and the clear signal indicates When the set time low set by the short circuit pin is exceeded, the counter outputs the timeout signal TMOUT at the set time.

As described above, the bus timeout detection circuits 15A to 15D are provided in the CPUs 12A to 12D, issue a bus request, acquire the bus, output an R / W signal, and return a response signal. If the time until arrival does not occur within the set time, timeout is detected.

[0009]

By the way, in the multiprocessor system having the above-mentioned configuration, a plurality of CPs are used.
When U simultaneously uses the system bus, each CPU outputs a bus request and the priority determination circuit permits the use of the bus. When the time required to acquire and read data exceeds the set time of the bus time-out detection circuit, time-out is detected and the time-out signal TMOUT is output. Then, the CPU that was in the standby state without being permitted to use the bus by the priority determination circuit of the other CPU that was outputting the bus request also exceeded the set time set by its own timeout detection circuit, The time-out signal TMOUT is output. That is, the CP that actually detected the timeout due to a defect.
Since it is U, there is a problem that a timeout will be detected up to another normal CPU.

Even if the CPU permitted to use the bus completes the request for the bus, the acquisition of the bus, and the reading of the data within the set time, the other CPUs not permitted to use the bus are in the standby state. Therefore, there is a problem in that when the bus is used, the set time of its own timeout circuit is immediately exceeded and the timeout detection signal TMOUT is output.

The present invention has been made to solve the above problems, and an object thereof is a multiprocessor system in which a plurality of CPUs are connected to a system bus, and a plurality of CPUs simultaneously make bus requests to obtain the bus. It is an object of the present invention to provide a multiprocessor system that prevents a CPU that has not been permitted to use the bus from timing out even if the CPU times out.

[0012]

In order to solve the above-mentioned problems, a first aspect of the present invention is directed to a plurality of arithmetic processing circuits, an input / output circuit and a bus arbitration in which a microprocessor and its peripheral circuits are connected by a local bus. Circuits are connected by a system bus, and data is transferred between the arithmetic processing circuit and the input / output circuit and between the arithmetic processing circuits via the system bus, and a bus is provided between the arithmetic processing circuit and the bus arbitration circuit. In a multiprocessor system having at least one bus request line, a bus use permission line, and a bus busy line in the system bus so as to arbitrate the right of use, in the system bus, the arithmetic processing circuit and the bus arbitration Circuits are connected to each other, the arithmetic processing circuit has a function of requesting, acquiring, and releasing a bus use right, and the bus arbitration circuit uses the bus. A second timeout detection circuit connected to the bus error line is provided in the arithmetic processing circuit, and a first timeout detection circuit connected to the bus error line is provided in the bus arbitration circuit. The arithmetic processing circuit outputs a bus request signal to the bus request line, the bus arbitration circuit inputs a bus request, outputs a bus use permission signal to the bus use permission line, and the arithmetic processing circuit uses the bus use Input a permission signal, output a bus busy signal to the bus busy line, read and write via the bus, output an R / W signal, wait for a response signal to return, and complete. When the R / W signal is output for a first time-out period or longer, the first time-out circuit of the bus arbitration circuit outputs a bus error signal via the bus error line, and the bus error signal is output. Is released to the bus that is input to the arithmetic processing circuit that has made a bus request, and that releases the bus when the bus use permission signal is not output from the bus arbitration circuit for a second timeout time of the arithmetic processing circuit or more. A multiprocessor system in which the arithmetic processing circuit is configured to give up a bus request.

According to a second aspect of the present invention, in the multiprocessor system according to the first aspect, when the bus arbitration circuit requests that at least two of the arithmetic processing circuits use the system bus at the same time, the bus request level is the same level. Then, the arithmetic processing circuit having the higher bus priority is determined to be able to use the bus.

According to a third aspect of the present invention, in the multiprocessor system according to the first aspect, the bus arbitration circuit has the same bus request level when at least two of the arithmetic processing circuits simultaneously use the system bus. If there,
The arithmetic processing circuit close to the bus arbitration circuit is determined to use the bus.

According to a fourth aspect of the present invention, bus request signals from a plurality of arithmetic processing circuits are passed to a bus arbitration circuit via a bus request line having a priority order, and a bus permission signal from the bus arbitration circuit is transferred to the bus. A multiprocessor system for sequentially passing to a plurality of arithmetic processing circuits via a permission line, wherein the bus arbitration circuit is not in use when there are a plurality of bus request signals on the bus request lines of the same priority at the same time. Under the above conditions, a circuit for outputting a bus permission signal to the arithmetic processing circuit via the bus permission line corresponding to the priority of the bus request line, and the bus of one arithmetic processing circuit is in use for more than the first timeout time. And a first time-out detection circuit for opening the bus to the arithmetic processing circuit, and each of the arithmetic processing circuits outputs a bus when both its own bus request signal and bus permission signal are present. And a bus busy signal is output, and when the bus is acquired by itself, the bus request / acquisition determination circuit that blocks the transfer of the bus permission signal to the arithmetic processing circuit in the subsequent stage, and after outputting the own bus request signal And a second time-out detection circuit for blocking the output of the bus request signal when the bus cannot be acquired even after the elapse of the second time-out time.

According to a fifth aspect of the present invention, bus request signals from a plurality of arithmetic processing circuits are passed to the bus arbitration circuit via a bus request line having a priority order, and a bus permission signal from the bus arbitration circuit is transferred to the bus. A multiprocessor system for sequentially passing to a plurality of arithmetic processing circuits via a permission line, wherein the bus arbitration circuit is not in use when there are a plurality of bus request signals on bus request lines of different priorities at the same time. Circuit for outputting a bus permission signal to the arithmetic processing circuit via the bus permission line corresponding to the priority of the bus request line having a higher priority, and the first timeout when the bus of one arithmetic processing circuit is in use. A first time-out detection circuit for opening the bus to the arithmetic processing circuit when it continues for a time or longer, and each arithmetic processing circuit receives its own bus request signal and bus permission signal. If the bus request signal is acquired, the bus request signal is output, the bus busy signal is output, and the bus request / acquisition determination circuit that blocks the transfer of the bus permission signal to the arithmetic processing circuit in the subsequent stage when the bus is acquired A second time-out detection circuit for preventing the bus request signal from being output when the bus cannot be acquired even after the second time-out period has elapsed after the output.

According to a sixth aspect of the present invention, in the multiprocessor system according to the first, fourth or fifth aspect, the first
Is set to be shorter than the second timeout time.

According to a seventh aspect of the present invention, bus request signals from a plurality of arithmetic processing circuits are passed to a bus arbitration circuit via a bus request line having a priority order, and a bus permission signal from the bus arbitration circuit is transferred to a bus. A multiprocessor system for sequentially passing to a plurality of arithmetic processing circuits via a permission line, wherein the bus arbitration circuit is not in use when there are a plurality of bus request signals on the bus request lines of the same priority at the same time. On the condition that the bus request signal is output to the arithmetic processing circuit via the bus permission line corresponding to the priority of the bus request line. When there is both a bus request and acquisition judgment time that prevents the passing of the bus permission signal to the arithmetic processing circuit in the subsequent stage when the bus is acquired and the bus busy signal is output Characterized in that it has and.

[0019]

The bus request from each CPU that intends to use the system bus is output as a low level signal. Each CPU
These request signals output from the bus arbiter are input to the bus arbitration circuit, and the bus arbiter grants the bus use right by each bus permission line. To do this, drive the bus enable line low. This low level is transmitted by the daisy chain method, and for all CPUs connected to the system bus,
The CPU on the bus arbiter side sequentially inputs to each CPU, and the output from the last CPU is connected so as to be returned to the bus arbiter. The CPU requesting the bus in the middle acquires the bus by the bus permission line, and the next CPU Since the connected bus permission line outputs high, the bus cannot be acquired from the next CPU because the bus permission line is high. CPU
When the right to use the system bus is granted through the bus granting daisy chain, the bus busy line is driven low.

Next, the CPU holds the system bus until the bus busy line is released. The bus arbiter allows another CPU to use the system bus by releasing the bus busy line by the CPU. Also, the bus arbiter has multiple CPs.
Which CP when U is requesting the system bus at the same time
It is a functional module that decides whether to allow U to use it.
The bus arbiter responds to the bus request and allows the appropriate CPU to use the system bus on one of the bus grant lines.
When the bus arbiter detects one or more bus requests when the bus busy line is high, it issues a bus grant signal to the bus request having the highest priority. When the CPU receives the bus grant, it drives the bus busy line low. CP
When U finishes using the bus, it releases the bus busy line. At the rising edge of the bus busy line at this time, the bus arbiter issues another bus permission according to the bus request level at that time.

If the bus busy line is not driven low by the CPU within the time-out period by the first time-out circuit, the bus arbiter outputs the bus busy C.
Forcibly revokes the PU bus grant. The first timeout time T1 is made longer than the sum of the maximum time of the bus grant daisy chain propagation delay and the time required for the CPU having the lowest priority to generate the bus busy line. Further, each CPU is provided with a second timeout time T2 composed of a counter.

Next, the CPU 1 and the CPU 2 simultaneously operate as the CPU.
The setting time of each time-out time when 3 is accessed and the operation by the installation method will be described. Here, when each timeout time is set to T2 only, or T2 <T1, when the CPU 2A requests the bus and the bus use permission signal is not returned, or the bus use permission signal is not returned within the timeout time T2. CPU2
Since A detects a time-out and the CPU 2B is also requesting the bus at the same time, the counter is being counted up at that time, so even if the CPU 2A releases the bus, C
The PU 2B also detects the time-out by exceeding the time-out time T2 before returning the bus use permission signal.

Therefore, the phenomenon that the CPU 2B also detects the time-out occurs due to the detection of the time-out of the CPU 2A. If only T1 is installed, C
When one of the PU 2A and the CPU 2B has a bus I / F failure and the other CPU cannot access the bus, the CPU 2 remains in the standby state even if both CPUs make a bus request. Therefore, by setting T2> T1, the CPU2
Even if A drives the bus use permission signal for a long time, the timer T1 of the bus arbiter is shorter. Therefore, by releasing the bus from the bus arbiter, the CPU 2B can use the bus, and the CPU 2B does not detect the timeout. From the above, by setting T2> T1, the conventional problem can be solved.

[0024]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention. As shown in FIG.
A, 2B, 2C and one bus arbiter 1 are connected to the system bus to form a multiprocessor system.

By the way, each arithmetic processing circuit 2A, 2B, 2
C is the same circuit, and is a bus request circuit and bus acquisition determination circuits 6A, 6B, 6C (RQ-1, RQ-2, R).
Q-3) and the timeout detection circuits 4A, 4B, 4C (T
IME-1, TIME-2, TIME-3). The bus request circuit and the bus acquisition decision circuits 6A, 6
The details of B and 6C are configured as shown in FIGS. 2 and 3 described later.

For example, when a bus request is made in the bus request circuit and the bus acquisition determination circuit 6A of the operation processing circuit 2A, a bus request signal is output to the bus request line BR * and the bus acquisition determination circuit 6A and the adjacent operation processing circuit 2B are output. The bus permission signal is output to the bus permission line BG * for outputting the bus permission signal to the bus request circuit of the adjacent arithmetic processing circuit 2B and the bus acquisition determination circuit 6B. .
Even in a multiprocessor including a plurality of arithmetic processing circuits, the bus is connected as described above.

The timeout detection circuits (second timeout detection circuits) 4A to 4C are composed of counters as shown in FIG. 4A, and are controlled by a clock signal and a clear signal. As the clock signal, the clock signal SCLK from the oscillator is input to the CLK of the counter, and the counter counts up in synchronization with the clock signal SCLK. As for the clear signal, when the CPU uses the bus, "L" is input to the CLR of the counter, the counter outputs "L", does not start counting up, and does not output time-out. Similarly, a bus arbiter (bus arbitration circuit) 1
The same timeout detection circuit (first timeout detection circuit) 3 as the arithmetic processing circuit is also provided therein.

Further, the bus arbiter 1 inputs the bus request signal when any one of the arithmetic processing circuits outputs the bus request signal to the bus request line BR * for arbitrating the bus, inputs the bus request signal, determines the bus priority, and makes the bus permission line BG. A bus arbitration circuit (ARB) 5 that outputs a bus permission signal is provided at *.

Next, the CPU which can use the bus according to the bus priority when the arithmetic processing circuits 2A and 2B simultaneously output the low level bus request signal to the bus request line BR *.
The arbitration circuit ARB5 that determines? Is described. Each of the bus request lines BR0 * to BR3 * corresponds to the bus priority, BR0 * is the lowest, and BR1 *,
It is said that BR2 * and BR3 * increase in this order.

First, the bus acquisition procedure when the bus request signal is output to the bus request lines BR0 * having the same priority will be described with reference to FIG. Arithmetic processing circuit CPU2A, CPU
When the bus arbiter 1 inputs the bus request signal output from the 2B to the bus request line BR0 *, it outputs a low level bus enable signal corresponding to the bus request signal to the bus enable line BG0 *. The bus permission signal is first input to the bus acquisition determination circuit 6A of the CPU 2A closest to the bus arbiter 1 by the daisy chain method. The bus acquisition determination circuit 6A is
Bus request signal low level output and bus enable signal low
The logic L1 makes a determination based on the level input signal, and the determination result is low, and the bus is acquired. Now the CPU
2A can use the bus. Further, in the logic L2, the low level bus request signal and the low level bus permission signal are input separately from the logic L1 to make a determination, and the determination result becomes high.
The CPU 2A outputs the level signal to the bus permission line BG0 *. This indicates that the CPU 2A has won the bus.
High output from the CPU 2A to the bus permission line BG0 *
The h-level signal is input to the bus request circuit of the CPU 2B and the bus acquisition determination circuit 6B, and similarly to the CPU 2A, the logic L3 outputs the low-level signal that the CPU 2B itself outputs to the bus request line BR0 * and the logic L2 to the BG0 *. The bus acquisition is determined by the high level signal output to
The result of the determination is high, and the bus cannot be acquired. Further, the logic L4 makes the same determination as that of the logic L2 of the CPU 2A, that is, the logic L3 is separate from the logic L3.
Level bus request signal and this BG0 * high level bus enable signal are input for determination, and the determination result is high.
Then, the CPU 2B outputs the high-level signal to the bus permission line BG0 * and outputs it to the CPU 2C in the next stage. This indicates that the CPU 2A has won the bus.

Next, the bus acquisition procedure when the bus request signals are output to the bus request lines BR0 * and BR1 * having different priorities will be described with reference to FIG. This is a case where the CPU 2A outputs a low level bus request signal to the bus request line BR0 *, and the CPU 2B outputs a low level bus request signal to the bus request line BR1 *. The bus arbiter 1 inputs each bus request signal of the CPU and makes a priority determination in an arbitration circuit ARB5. In this arbitration circuit, four bus request lines BR0 *, BR1 *,
BR3 *> BR is given priority to BR2 * and BR3 *
2 *> BR1 *> BR0 *. As a result, CP
Low level bus request line BR0 * output from U2A
And the low-level bus request line B output by the CPU 2B
In R1 *, the bus request of the CPU 2B is prioritized, and the bus arbiter 1 has the bus permission line B corresponding to the bus request line BR1 *.
A low level bus enable signal is output to G1 *. The low level bus enable signal from the bus arbiter 1 is C
Both the PU 2A and the CPU 2B are input to the bus request circuit and the bus acquisition determination circuits 6A and 6B. In the CPU 2A, the low level signal bus enable signal is not input until the logic L5, and the logic L5 is considered to be high at BG0 *. The bus request signal of the level is determined, and the determination result is high, and the bus cannot be acquired. B in CPU2B
The low-level bus permission signal of G1 * is input to the logic L7, and it is determined to be a low-level bus request signal. The determination result is low, and the bus is acquired. It should be noted that the delivery of signals on the bus permission lines in FIGS. 3 and 4 is as shown in FIG.

The time-out detection circuit in each CPU and the bus arbiter will be described with reference to FIG. Figure 4
(A) is a block diagram of the counter which comprises the time-out circuit, This counter inputs TMCL to CLR.
It is controlled by the R signal and the SCLK signal (clock signal from an oscillator not shown) input to CLK. FIG. 4
(B) is a timing chart of signals of the time-out detection circuit (first time-out detection circuit) 3 in the bus arbiter 1. The TMCLR signal is always hi.
This signal is at the gh level and is output to the low level when any CPU uses the bus. And
The output of this counter is reset to 0 when the TMCLR signal is at the low level, and counts up at the rising edge of the SCLK signal when the TNCLR signal is at the high level. In addition, the output of the counter can be set in two ways by the short-circuit pin, and determines the time-out time. In addition, since the timeout detection circuits (second timeout detection circuits) 4A and 4B in the CPUs 2A and 2B count up from the bus request to the bus acquisition, the CPUs 2A and 2B in FIG. When the low level is output to the line BR * for the set time T2 of the counter or more, the counter outputs the bus error line BER after the set time.
A bus error signal is output to R * and time out occurs.

As described above, according to the present embodiment, the system bus has a plurality of bus request lines BR * and bus permission lines B.
G *, Bus in-use line BBSY *, Bus error line BERR
*, And the circuit for arbitrating the bus is CPU2A,
A bus arbiter 1 is provided separately from 2B and 2C,
The bus arbiter 1 is provided with an arbitration circuit ARB5 connected to the system bus and a time-out detection circuit 3 for detecting an over-use time of the CPU bus.
1 is set, and each CPU is also provided with a timeout detection circuit, and a timer T2 for detecting the output time over of the bus request signal is set so that the bus arbitration circuit is established and the bus occupation of one CPU does not take a long time. In addition, the CPU requesting the bus within the time set by the timer in the bus arbitration circuit is released from the bus so that another CPU can use the bus.

[0034]

As described above, according to the present invention,
A CP in which multiple CPUs simultaneously requested the bus and acquired the bus
The bus arbitration circuit is provided with a bus arbiter that is separate from the CPU to prevent U from timing out and causing CPUs that are not permitted to use the bus to time out. In order to prevent such a situation, a multiprocessor system is provided in which a CPU requesting a bus at a timer setting time in a bus arbitration circuit is released from the bus so that another CPU can use the bus.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing bus acquisition when the bus requests are at the same level in FIG. 1;

FIG. 3 is a diagram showing bus acquisition when bus requests are at different levels in FIG. 1;

FIG. 4A is a configuration diagram of a timeout detection circuit,
FIG. 16B is a timing chart of the timeout detection circuit of FIG.

FIG. 5 is a diagram showing a connection relationship of bus permission lines in FIGS. 2 and 3;

FIG. 6 is a perspective view in which a plurality of CPUs are mounted in a case.

FIG. 7 is a configuration diagram of a conventional multiprocessor system.

[Explanation of symbols]

1 ... Bus arbitration circuit (bus arbiter), 2A, 2B, 2C
... arithmetic processing circuit, 3 ... timeout detection circuit, 4A, 4
B, 4C ... Timeout detection circuit, 5 ... Bus use permission determination circuit (arbitration circuit), 6A, 6B, 6C
… Bus request / acquisition circuit, 8… Board, 9… Connector, 10
... system bus, 11 ... case, 12A, 12B, 12
C, 12D ... Arithmetic processing circuit, 13A, 13B, 13C,
13D ... Bus arbitration circuit, 14A, 14B, 14C, 14
D ... Priority determination circuit, 15A, 15B, 15C, 15D
… Timeout detection circuit.

Claims (7)

[Claims] 1. A plurality of arithmetic processing circuits in which a microprocessor and its peripheral circuits are connected by a local bus, an input / output circuit and a bus arbitration circuit are connected by a system bus, and the arithmetic processing circuit and the front circuit are connected via the system bus. At least one bus request line is provided in the system bus so as to transfer data between the input / output circuits and between the arithmetic processing circuits and to arbitrate the bus use right between the arithmetic processing circuits and the bus arbitration circuit. In a multiprocessor system including a bus use permission line and a bus use middle line, the arithmetic processing circuit has a function of requesting, acquiring, and releasing a bus use right, and the bus arbitration circuit arbitrates the bus use right. A second timeout detection circuit having a function, which is connected to the bus error line, is provided in the arithmetic processing circuit, and a bus error line is provided in the bus arbitration circuit. A connected first timeout detection circuit is provided, the arithmetic processing circuit outputs a bus request signal to the bus request line, the bus arbitration circuit inputs a bus request, and the bus use permission signal is input to the bus use permission line. And output
The arithmetic processing circuit inputs the bus use permission signal, outputs a bus busy signal to the bus busy line, reads and writes via the bus, outputs an R / W signal, and waits for a response signal. Upon completion, and when the R / W signal is output for a first time-out period or longer, the first time-out circuit of the bus arbitration circuit outputs a bus error signal through the bus error line, and the bus error signal becomes The bus request is input to the arithmetic processing circuit that has made the bus request, releases the bus, and releases the bus unless the bus use permission signal is output from the bus arbitration circuit for a second timeout time of the arithmetic processing circuit or more. A multiprocessor system in which the arithmetic processing circuit is configured to give up. 2. The multiprocessor system according to claim 1, wherein when two or more arithmetic processing circuits request the system bus to be used simultaneously by the bus arbitration circuit, if the bus request levels are the same, the bus priority order is set. A multiprocessor system characterized in that a high-performance arithmetic processing circuit determines so that a bus can be used. 3. The bus arbitration circuit according to claim 1, wherein the bus arbitration circuit has the same bus request level when at least two arithmetic processing circuits simultaneously use a system bus. A multiprocessor system characterized in that an arithmetic processing circuit close to the circuit determines that a bus can be used. 4. A bus request signal from a plurality of arithmetic processing circuits is passed to a bus arbitration circuit via a bus request line having a priority order, and a bus permission signal from said bus arbitration circuit is passed via said bus permission line. In a multiprocessor system for sequentially delivering to a plurality of arithmetic processing circuits, the bus arbitration circuit is such that the bus is not in use when there are a plurality of bus request signals simultaneously on bus request lines of the same priority. A circuit for outputting a bus permission signal to the arithmetic processing circuit via the bus permission line corresponding to the priority of the request line, and the arithmetic processing circuit when the bus of one arithmetic processing circuit continues to be used for a first timeout time or longer. A first time-out detection circuit for releasing the bus to the bus, each of the arithmetic processing circuits acquires the bus when both its own bus request signal and bus grant signal are present and is in use A bus request / acquisition determination circuit that outputs a signal and blocks the passing of the bus permission signal to the arithmetic processing circuit in the subsequent stage when the bus is acquired, and a second timeout time or more after the own bus request signal is output. A multi-processor system comprising: a second time-out detection circuit that blocks the output of the bus request signal if the bus cannot be acquired even after a lapse of time. 5. A bus request signal from a plurality of arithmetic processing circuits is passed to a bus arbitration circuit via a bus request line having a priority order, and a bus permission signal from said bus arbitration circuit is passed via said bus permission line. In a multiprocessor system for sequentially delivering to a plurality of arithmetic processing circuits, the bus arbitration circuit sets priority levels on the condition that the buses are not in use when there are a plurality of bus request signals simultaneously on bus request lines having different priority levels. A circuit for outputting a bus permission signal to an arithmetic processing circuit via a bus permission line corresponding to a higher priority of the bus request line, and a case in which the bus of one arithmetic processing circuit is in use for more than a first timeout time A first time-out detection circuit for causing the arithmetic processing circuit to open the bus, and each arithmetic processing circuit acquires the bus when both its own bus request signal and bus permission signal are present. A bus request / acquisition determination circuit that prevents the bus grant signal from passing to the arithmetic processing circuit in the subsequent stage when the bus acquired signal is output and the bus is acquired by itself, and after outputting the own bus request signal A multi-processor system comprising: a second time-out detection circuit that prevents the output of the bus request signal when the bus cannot be acquired even after the time-out period of 2 or more has elapsed. 6. The multiprocessor system according to claim 1, 4 or 5, wherein the first timeout time is set shorter than the second timeout time. 7. A bus request signal from a plurality of arithmetic processing circuits is passed to a bus arbitration circuit through a bus request line having a priority order, and a bus permission signal from the bus arbitration circuit is passed through the bus permission line. In a multiprocessor system for sequentially delivering to a plurality of arithmetic processing circuits, the bus arbitration circuit is such that the bus is not in use when there are a plurality of bus request signals simultaneously on bus request lines of the same priority. A bus permission signal is output to the arithmetic processing circuit via the bus permission line corresponding to the priority of the request line, and each arithmetic processing circuit switches the bus when both its own bus request signal and bus permission signal are present. It has a bus request / acquisition determination circuit that prevents the passing of the bus permission signal to the arithmetic processing circuit in the subsequent stage when the bus is acquired and outputs the bus busy signal. A multiprocessor system to collect.