JPH0888557A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To provide a ternary input buffer semiconductor integrated circuit of less current consumption by providing a buffer, whose input threshold voltage is set to a specific value or higher, and a buffer whose input threshold voltage is set to the specific value or lower. CONSTITUTION: The low level is outputted from an input buffer 4 whose input threshold voltage is set to VCC/2 or lower when a clock input terminal 12 is in the high level; and the high/low/low level is outputted in accordance with the state of high level/open/low level applied to an input terminal 1 while the terminal 12 is in the low level. Meanwhile, the high level is outputted from an input buffer 6 whose input threshold voltage is set to VCC/2 or lower while the terminal 12 is in the high level, and the high/high/low level is outputted in accordance with the state of high level/open/low level applied to the terminal 1 while the terminal 12 is in the low level. Thus, a current flows to VCC only when the high level is outputted to the terminal 12 and it is connected to capacitors 8 and 11 through switches 9 and 10, and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ternary input buffer suitable for use in an integrated circuit having a complementary MOS structure.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional example. In this conventional example, a first resistor 2 having one end connected to an input terminal and the other end connected to a power supply VCC, and one end connected to an input terminal and the other end G
A second resistor 3 connected to ND, and first and second input buffers 4 and 6 whose input side is connected to an input terminal and whose output side is connected to first and second output terminals 5 and 7, respectively. Has been done. The input threshold voltage of the first input buffer 4 is VCC / 2 or higher, and the input threshold voltage of the second input buffer 6 is set to VCC / 2 or lower. The resistance values of the resistors 3 and 2 are set to the same value.

In this conventional example, when the L or H level is applied to the input terminal 1, the outputs of the first and second input buffers 4 and 6 both become the L or H level. When the input terminal 1 is open, the voltage of the input terminal 1 becomes VCC / 2 due to the first and second resistors 2 and 3, the first input buffer 4 outputs the L level, and the second input buffer 6 Outputs H level.

As described above, by applying the voltage of H / open / L level to the input terminal 1, the voltage of H / L / L level is output from the first output terminal 5, and the voltage of the second output terminal 5 is output. The H / H / L level voltage is output from the output terminal 7. With these output voltages, three states corresponding to the states of the input terminals can be obtained.

[0005]

In the conventional ternary input buffer, the first resistor 2 and the second resistor 3 are the power supply VCC and GND.
Since they are connected in series between them, there is a drawback that current always flows and current consumption increases. For example, VCC = 5V, first
If both the resistance 2 and the second resistance 3 are set to 50 KΩ, the consumption current ICC is ICC = 5 V / (50 KΩ + 50 KΩ) = 50 μA.

An object of the present invention is to provide a ternary input buffer semiconductor integrated circuit with low current consumption.

[0007]

To achieve the above object, a ternary input buffer of the present invention has one end connected to a power supply VCC and the other end connected to an input terminal or a G terminal via a first switch.
An input terminal is connected to a connection point between the first capacitor connected to ND and the first capacitor and the first switch,
A first input buffer whose input threshold voltage is set to VCC / 2 or higher, and the same capacitance as the first capacitor, with one end connected to GND and the other end input via the second switch A second capacitor connected to the terminal or VCC, and an input terminal connected to a connection point between the second capacitor and the second switch, and an input threshold voltage set to VCC / 2 or lower. It has an input buffer.

The output of the first input buffer is connected to the data input terminal of the first D type flip-flop, the output terminal of the first D type flip-flop is connected to the first output terminal, and the clock A first D-type flip-flop whose terminal is connected to the clock input terminal of the first D-type flip-flop, and an output of the second input buffer is connected to a data input terminal of the second D-type flip-flop, An output terminal of the second D-type flip-flop is connected to the second output terminal, and a clock terminal includes a second D-type flip-flop connected to a clock input terminal of the second D-type flip-flop. Is desirable.

[0009]

In the conventional three-valued input buffer, the first resistor 2 and the second resistor 3 are connected in series between VCC and GND, so that current always flows and the amount of consumed current increases.

In the present invention, a current flows through VCC when the H level is applied to the clock terminal 12, the first capacitor 8 is connected to GND through the first switch 9, and the second switch 10 is connected. Through the second capacitor 11
Is only connected to VCC.

This is H when the input terminal 1 is open.
The same result is obtained when the level is applied and when the L level is applied.

[0012]

FIG. 1 shows a first embodiment of the present invention. In this embodiment, one end of the first capacitor 8 is connected to VCC, and the other end is connected to the input terminal 1 or GND via the first switch 9. Also, the input threshold voltage is V
The input side of the first input buffer 4 set to CC / 2 or higher is connected to the connection point between the first capacitor 8 and the first switch 9, and the output side of the first input buffer 4 is the first side. It is connected to the output terminal 5. The second capacitor 11 having the same capacitance as the first capacitor has one end connected to GND and the other end connected to the input terminal 1 or VCC via the second switch 10. Also,
The input side of the second input buffer 6 whose input threshold voltage is set to VCC / 2 or lower is connected to the second capacitor 11 and the second capacitor 11.
Of the second input buffer 6 is connected to the second output terminal 7.

In the present embodiment, the first switch 9 connects the first capacitor 8 to GND when the H level is applied to the clock input terminal 12 and applies the L level to the clock input terminal 12. When operated, the first capacitor 8 operates so as to be connected to the input terminal 1 side. The second switch 10 has a clock input terminal 12
When the H level is applied to the
It is assumed that the second capacitor 11 is connected to CC and operates so as to connect the second capacitor 11 to the input terminal 1 side when the L level is applied to the clock input terminal 12. Further, the first switch 9 and the second switch 10 are generally composed of MOS transistors, but since the structure is not related to the essence of the present invention, details thereof will not be described here.

First, the case where the input terminal 1 is open will be described. In period 1 of FIG. 2, clock input terminal 1
When the H level is applied to 2, the first capacitor 8 is connected to GND via the first switch 9. During this time,
The L level is output from the first input buffer 4. On the other hand, the second capacitor 11 is connected to the second switch 10
To VCC during this time, and during this time, the H level is output from the second input buffer 6. Clock input terminal 1
When the L level is applied to the first capacitor 8 and the second capacitor
The capacitor 11 is short-circuited via the first current limiting resistor 2 and the second current limiting resistor 3. The first capacitor 8 and the second capacitor 11 have the same capacitance and therefore the amount of charge is also equal. Therefore, when these capacitors are short-circuited, the potential at the midpoint thereof becomes VCC / 2. This voltage is applied to the first input buffer 4 and the second input buffer 6. At this time, since the input threshold voltage of the first input buffer is set to VCC / 2 or higher, the L level is output from the first input buffer 4,
The input threshold voltage of the second input buffer 6 is VCC / 2.
Since it is set as follows, the H level is output. In this way, when the input terminal 1 is open, the L level is output from the first input buffer 4 and the L level is output from the second input buffer 6 regardless of whether the H level or the L level is input to the clock input terminal 12. H level is output. The output states of these input buffers 4 and 6 are output to the outside from the first and second output terminals 5 and 7.

A period 3 in FIG. 2 shows a case where the H level is applied to the input terminal 1. Clock input terminal 12
When the H level is applied to, the operation is the same as when the input terminal 1 is open, and the input of the first input buffer is L level.
The output of the second input buffer is at the H level and the output thereof is at the H level. When the L level is applied to the clock input terminal, while the clock input terminal 12 is at the H level, the first switch 9 and the first switch 9 are connected to the first capacitor 8 connected to the GND via the first switch 9. The H level is applied via the current limiting resistor 2 of 1 and the input terminal 1. Therefore, the charge charged in the capacitor 8 while the clock is at the H level is discharged through the first current limiting resistor 2 and the input terminal 1, the input of the first input buffer 4 becomes the H level, and its output Becomes H level. On the other hand, the second capacitor 11
Does not change because the H level is applied via the second switch 10 regardless of whether the clock input terminal 12 is at the H level or the L level. Therefore, the H level is always applied to the second input buffer 6, and the H level is output. Input terminal 1
When H level is H level and L level is applied to the clock input terminal 12, H level is output from both the first input buffer 4 and the second input buffer 6.

A period 2 in FIG. 2 shows a case where the L level is applied to the input terminal 1. Clock input terminal 12
When the H level is applied to, the operation is the same as when the input terminal 1 is open, and the input of the first input buffer is L level.
The output becomes L level, the input of the second input buffer becomes H level, and the output becomes H level. When L level is applied to the clock input terminal 12,
Since the L level is applied to the first capacitor 8 via the first switch 9 regardless of whether the clock input terminal 12 is at the H level or the L level, the state thereof does not change. Therefore, the L level is always applied to the first input buffer 4, and the L level is output. On the other hand, while the clock input terminal 12 is at the H level, the second switch 11, the second current limiting resistor 3 and the input terminal 1 are connected to the second capacitor 11 which is connected to VCC through the second switch 10. The L level is applied via.
Therefore, the charge charged in the second capacitor 11 while the clock input terminal 12 is at the H level is discharged through the second current limiting resistor 3 and the input terminal 1, and the input of the second input buffer 6 becomes It becomes L level, and its output becomes L level. When the input terminal 1 is at the L level and the L level is applied to the clock input terminal 12 in this way, the L level is output from both the first input buffer 4 and the second input buffer 6.

As described above, in this embodiment, the L level is output from the first input buffer 4 via the first output terminal 5 while the clock input terminal is at the H level, and the clock input terminal is at the L level. H / applied to input terminal 1
The H / L / L level is output according to the open / L level state. On the other hand, the H level is output from the second input buffer 6 via the second output buffer while the clock input terminal is at the H level, and is applied to the input terminal 1 while the clock input terminal is at the L level. H / Open / L
The H / H / L level is output according to the level state.

Next, the current consumption of this embodiment will be examined. In the present embodiment, the current flows to VCC when the H level is applied to the clock input terminal 12, the first capacitor 8 is connected to GND via the first switch 9, and the second capacitor is connected to GND via the second switch 10. 2 capacitor 11 is VC
Only at the moment when it is connected to C.

Here, the electrostatic capacitances of the first capacitor 8 and the second capacitor 11 are C, the charge stored in the first capacitor 8 is Q8, the charge stored in the second capacitor 11 is Q11, and the clock is The frequency of the clock applied to the input terminal 12 is represented by f.

When the input terminal 1 is open, the potential difference between both ends of the first capacitor 8 and the second capacitor 11 becomes VCC / 2 while the clock input terminal 12 is at the L level. = C · VCC / 2 (1) Q11 = C · VCC / 2 (2) When the clock input terminal 12 becomes H level, the potential difference between both ends of each capacitor becomes VCC, so Q8 ′ = C · VCC (3) Q11 ′ = C · VCC (4) Since the difference charge must be supplied from VCC, the charge Q flowing to VCC is Q = Q8′−Q8 + Q11 ′. -Q11 = C · VCC (5) If the frequency of the clock applied to the clock input terminal 12 is f, the charging / discharging described here is repeated f times per second. Therefore, the amount of charge flowing to VCC in one second, that is, the consumption current ICC is ICC = Qf = CVCCf (6)

When the H level is applied to the input terminal 1, the first capacitor 8 discharges the electric charge through the first current limiting resistor 2, so that the clock input terminal 12 becomes H level.
Every time the level is reached, the charge of Q = C · VCC must be charged. On the other hand, since the electric potential at one end of the second capacitor 11 is charged to VCC during the period when the clock is at L level, the second capacitor 11 can discharge the electric charge even if the H level that is equal to VCC is applied. There is no need to recharge. Therefore, the consumption current ICC is ICC = Qf = CVCCf (7), which is the same result as when the input terminal 1 is open.

When the L level is applied to the input terminal 1, the potential of the one end of the first capacitor 8 is equal to GND because the potential of one end of the first capacitor 8 is charged to GND while the clock is at the L level. Even if it is, the first capacitor 8 does not need to be charged because it does not discharge electric charge. On the other hand, since the second capacitor 11 discharges the electric charge through the second current limiting resistor 3, the electric charge of Q = C.VCC must be charged every time the clock input terminal 12 becomes H level. . Therefore, the consumption current ICC is ICC = Qf = CVCCf (8), and the same result as when the input terminal 1 is open and the H level is applied.

Now, suppose that C = 10 pf, VCC = 5 V, f
= 1 KHz, the current consumption ICC of this embodiment is ICC = 10 pf · 5 V · 1 KHz = 0.05 μA (9).

Although the first and second capacitors are each configured to be charged with the power supply voltage, the same operation as described above is performed even if each of them is short-circuited and discharged (not shown). .

In the first embodiment, the L level is output from the first input buffer 4 while the clock input terminal 12 is at the H level, and is applied to the input terminal 1 when the clock input terminal 12 is at the L level. H / L / L level is output according to the H / open / L level state.
The second input buffer 6 outputs H level while the clock input terminal is at H level, and the clock input terminal is at L level.
H / Open / applied to input terminal 1 when the level becomes
H / H / L levels are output according to the L level state. That is, in the first embodiment, the state that appears at the first output terminal 5 and the second output terminal 7 when the H level is applied to the clock input terminal 12 and when the L level is applied. Has the drawback of changing.

A second embodiment of the present invention is shown in FIG. In the present embodiment, the output of the first input buffer 4 is connected to the data input terminal of the first D-type flip-flop (hereinafter abbreviated as D-FF). The Q output terminal of the first D-FF is connected to the first output terminal 5, and the clock terminal is connected to the clock input terminal 12. On the other hand, the output of the second input buffer 6 is connected to the data input terminal of the second D-FF. The Q output terminal of the second D-FF is the second
Output terminal 7 and the clock terminal is connected to the clock input terminal 12. The other structure is the same as that of the first embodiment, and the description thereof is omitted.

First and second input buffers 4 and 6
When the clock input terminal 12 goes to the L level, the output corresponding to the state of the input terminal 1 is output. These states are the first and second D-F / F when the signal applied to the clock input terminal 12 next changes to the H level.
It is held by 13 and 14 and is output to the outside from the first and second output terminals 5 and 7. Therefore, the outputs of the first input buffer 4 and the second input buffer 6 do not appear outside while the H level is being applied to the clock input terminal 12, and always depend on the state of the input terminal 1. The status is output.

[0028]

As described above, the three-valued input buffer of the present invention has one end connected to VCC and the other end connected to the input terminal or GND through the first switch, and the first capacitor. The input terminal is connected to the connection point between the first capacitor and the first switch, and the input threshold voltage is VCC.
Connect the first input buffer set to ½ or more and the same capacitance as the first capacitor and connect one end to GND,
The input terminal is connected to the second capacitor whose other end is connected to the input terminal or VCC through the second switch, and the connection point between the second capacitor and the second switch, and the input threshold voltage is By configuring so as to have the second input buffer set to VCC / 2 or less, it is possible to provide a ternary input buffer semiconductor integrated circuit device with low current consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1 Input Terminal 2 1st Resistance 3 2nd Resistance 4 1st Input Buffer 5 1st Output Terminal 6 2nd Input Buffer 7 2nd Output Terminal 8 1st Capacitor 9 1st Switch 10 2nd Switch 11 Second capacitor 12 Clock input terminal 13 First D-type flip-flop 14 Second D-type flip-flop 15 Applied voltage waveform of input terminal 1 16 Clock input terminal waveform 17 Terminal voltage waveform of first capacitor 8 18 Terminal Voltage Waveform of Second Capacitor 19 Output Waveform of First Input Buffer 20 Output Waveform of Second Input Buffer

Claims (2)

[Claims] 1. A ternary input buffer having an input side connected to an input terminal and an output side connected to a first and a second output terminal, and a ternary input buffer having one end connected to a power supply VCC. A first capacitor whose other end is connected to the input terminal or GND through the first switch;
An input terminal is connected to the connection point between the first capacitor and the first switch, and the first input buffer whose input threshold voltage is set to VCC / 2 or higher, and the same capacitance as the first capacitor, and The input terminal is connected to a second capacitor whose one end is connected to GND and the other end is connected to the input terminal or VCC through the second switch, and the connection point between the second capacitor and the second switch. And a second input buffer having an input threshold voltage set to VCC / 2 or less, a ternary input buffer semiconductor integrated circuit device. 2. The output of the first input buffer is connected to the data input terminal of the first D-type flip-flop, the output terminal of the first D-type flip-flop is connected to the first output terminal, and the clock A first D-type flip-flop whose terminal is connected to the clock input terminal of the first D-type flip-flop, and an output of the second input buffer is connected to a data input terminal of the second D-type flip-flop, An output terminal of the second D-type flip-flop is connected to the second output terminal, and a clock terminal includes a second D-type flip-flop connected to a clock input terminal of the second D-type flip-flop. The ternary input buffer semiconductor integrated circuit device according to claim 1.