JPH0887885A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE: To obtain a compiled system memory where word lines and bit lines are arranged at fine pitch by assigning an insignificant bit of address to Y address and a significant bit to X address. CONSTITUTION: A Y address system comprises an address buffer 12 receiving a most insignificant bit address A0, Y decoders 0 and 1, Y switches 0-2, 0-3 receiving an output from the Y decoder 0, and Y switches 1-2, 1-3 receiving an output from the Y decoder 1. An X address system comprises address buffers 13, 14 receiving significant bit addresses A1, A2, an X predecoder 15 receiving outputs therefrom, and X main decoders 00, 01, 10, 11 receiving outputs from the X predecoder. The X main decoder 00 accesses a memory cell in the lowermost row and respective X main decoders correspond to respective rows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a high speed, high density compiled semiconductor memory circuit device suitable for a semi-custom LSI.

[0002]

2. Description of the Related Art Conventionally, a memory used in a CMOS gate array LSI, which is a representative of a semi-custom LSI, is often fixed. That is, several memory layout patterns of the number of words × the number of bits which the user is likely to desire have been prepared in advance and supplied to the user.

Further, a method called a compiled method, in which the layout pattern is generated by giving the number of words and the number of bits, is beginning to be adopted, but the number of words and the number of bits are rough, and the width is variable. Was small.

[0004]

In the above-mentioned prior art, it is rare that the user can supply the memory of the word number and the bit number desired by the user, and the user either uses a slightly larger memory or has the required number of words. Developed and manufactured a special configuration. Therefore, the chip cost is increased, and a slightly larger memory is used, so that the access time of the memory is deteriorated.

Japanese Unexamined Patent Publication (Kokai) No. 3-201298 proposes a semiconductor memory device in which an X address decoder is formed by a 4-input AND and corresponds to a memory cell. According to this, the step of the number of words can be made a multiple of the number n of memory cell columns instead of the power of 2 as in the conventional case, so that the step of the number of words can be made more dense.

However, in this method, for example,
When the X address is changed to 5 inputs, X of 5 inputs AND
Since it is necessary to change to an address decoder and it becomes difficult to efficiently arrange it corresponding to the memory cells due to the large number of elements, the variable width of the number of profitable words that can be supplied is narrow, and the memory of the number of words desired by the user is required. Could not be provided.

An object of the present invention is to provide a compiled type memory having a high memory density for a master slice type LSI such as a gate array, a fine number of words and bits, and a wide variable number of words and bits. To provide.

Another object of the present invention is to use a compiled type semiconductor with good production efficiency, in which when a layout pattern is generated by designating the number of words and the number of bits, there are few changes and common patterns and parts can be used. It is to provide a manufacturing method.

[0009]

The above-described object of the present invention is to assign the lower bits of an address to a Y address and the upper bits to an X address, and to specify a column of the memory mat at the Y address and a row of the memory mat at the X address. This can be achieved by configuring (column) selection, dividing the X decoder into two predecoders and a main decoder, and arranging the main decoders corresponding to the rows of the memory mat.

In the above structure, the structure of the main decoder is fixed regardless of the number of bits of the X address.

When the number of bits is 2 or more, the memory mats are arranged on both sides of the X main decoder.

Further, it is characterized in that memory cells of the same address are arranged next to each other in the memory mat, or memory cells of different columns are arranged next to each other in the memory mat.

Further, the address signal terminal and the data signal terminal are arranged on the same side of the memory module.

When the memory has two ports A and B, the address signal terminal and the data signal terminal of the A port and the address signal terminal and the data signal terminal of the B port are arranged on the opposite sides, respectively. Characterize.

[0015]

According to the present invention, the lower bits of the address are assigned to the Y address and the upper bits are assigned to the X address, the column of the memory mat is selected by the Y address, and the row (column) of the memory mat is selected by the X address. As a result, the memory mat addresses can be sequentially assigned in the row direction.
Therefore, even if the row corresponding to the higher-order address is deleted, the addresses of the memory mats become serial numbers and no missing teeth occur.

Further, the X decoder is divided into a predecoder and a main decoder, and the main decoder arranged corresponding to the rows of the memory mat is formed regardless of the number of words. It can be changed to efficiently handle a wide number of words.

Further, by separating the X decoder from the predecoder and the main decoder, the main decoders are arranged corresponding to the rows of the memory mat, so that the arrangement is regular,
When the number of words is increased or decreased, the row corresponding to the upper address and the main decoder can be added or deleted integrally, and it is possible to cope with the case where the number of words is not the nth power of 2.

When the number of columns is 2, the address of a certain row is allocated at addresses 2n and 2n + 1, so that the increment of the number of words corresponds to the number of columns and becomes 2 words.

Further, by arranging the memory cells of the same address next to each other in the memory mat, the arrangement in the bit width direction becomes regular, so that the bit width can be made in 1-bit steps. Moreover, since the memory cells of the same address are packed and arranged, the deterioration of the access time is prevented and the control at the time of writing becomes easy.

By arranging the memory cells of different columns next to each other in the memory mat, the arrangement in the bit width direction can be made regular, and the wiring regions connecting the Y switches are adjacent to each other even when the bit width is large. Can be high density.

When the memory has two ports A and B, the address signal terminal and the data signal terminal of the A port and the address signal terminal and the data signal terminal of the B port are arranged on the opposite sides. Since the memory module can be formed in a rectangular shape without wasting space, the memory density can be increased, which leads to higher speed and lower power consumption.

Further, when the number of bits is 2 bits or more, by disposing the memory mats on both sides of the X main decoder, it is possible to reduce variations in the decoded signal and obtain a high speed memory.

Furthermore, since it is not necessary to determine the type of main decoder in generating the layout pattern, it is possible to handle a large number of words and bit increments with a small number of memory components.
Program becomes easy.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a memory according to an embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows a configuration of 4 rows × 2 columns × 4 bits, that is, 8 words × 4 bits. In FIG. 1, in order to avoid complication, the writing system and the like are omitted and only the reading system is shown. Further, the left memory mat 16 and the Y switch 17 are similar to those on the right side, so only the frame is shown.

The Y address system has the least significant bit address A.
Address buffer 12 to which 0 is input, Y decoders 0 and 1 that receive the output, adjacent Y switches 0-2 and 0-3 that receive the output of Y decoder 0, and adjacent Y switch 1 that receives the output of Y decoder 1. -2 and 1-3.

The X address system has a high-order bit address A.
Address buffers 13 and 14 to which 1 and A2 are input, an X predecoder 15 that receives their outputs, and X main decoders 00, 01 and 1 that receive the output of the X predecoder 15.
It consists of 0 and 11. Each X main decoder 00 corresponds to each row so that the X main decoder 00 accesses the memory cell in the lowest row 18.

For example, when A2 and A1 are 1, 1 the memory cell in the top row 19 is selected and A0 is 1.
, The Y switches 1-2 and 1-3 are opened, so that the data in the memory cell 20 is D2 via the I / O circuit 2 and the data in the memory cell 21 is D3 via the I / O circuit 3. Obtained as.

To aid in understanding, FIG. 2 shows the block diagram of FIG. 1 and the address assignment of the memory cells. Allocating the address of the memory mat by assigning the lower bit of the address to the Y address and the upper bit to the X address, selecting the column of the memory mat with the Y address, and selecting the row of the memory mat with the X address. Can be serialized in the row direction.

Further, since the X decoder is composed of a predecoder and a main decoder, and only the structure of the predecoder is changed corresponding to the number of bits of the X address, and the main coder has the same structure, the row of the memory mat is the same. The main decoder can be arranged regularly according to. For this reason,
By deleting the row 19 and the X main decoder 11 corresponding to the higher address, the memory from address 0 to address 5 is obtained. That is, in this case, 3 rows x 2 columns x 4
It can be easily changed to a memory of bit = 6 words × 4 bits. In this way, a memory in which the number of words is not the nth power of 2 can be easily constructed. In the example of FIG. 2, since the number of columns is 2, the increment of the number of words is 2.

Although the configuration of FIG. 2 has a × 4 bit configuration, if a × 5 bit configuration is desired, one memory cell is added at each address of the left memory mat as shown in FIG. Then, the Y switch and the I / O circuit may be added correspondingly. On the contrary, in the case of reducing x3 bits by 1 bit, one memory cell may be reduced at each address of the memory mat on the right side, and the Y switch and the I / O circuit may be correspondingly reduced. Therefore, it can be seen that the number of bits can be set to 1.

Further, since the address signal terminal and the data signal terminal are arranged on the same side of the memory module, the memory module can be formed in a rectangular shape by reducing wasteful space.
High-density memory can be realized. This also leads to faster memory and lower power consumption.

Furthermore, since the memory mats are arranged on both sides of the X decoder, it is possible to reduce variations in the time required for the decoder signals to reach the memory mats, and it is possible to realize a high-speed memory.

As described above in detail, according to this embodiment, the memory density is high, the access time is fast, the power consumption is low, and the step size of the number of words and the number of bits is fine. A compiled memory can be obtained.

FIG. 4 shows the configuration of the memory of another embodiment of the present invention.
Will be described. FIG. 4 shows a structure of 16 rows × 4 columns × 4 bits, that is, 64 words × 4 bits. In FIG. 4, in order to avoid complication, the writing system and the like are omitted and only the reading system is shown. The memory mat on the left side, the Y switch, and the I / O circuit are omitted because they are similar to those on the right side.

The Y address system has a lower bit address A
Address buffers 41 and 42 to which 0 and A1 are input and Y decoders YD00, 01 and 10, which receive their outputs,
11, Y switch 0 for receiving the output of Y decoder YD00
-2 and 0-3, Y switches 1-2 and 1-3 that receive the output of the Y decoder YD01, Y switches 2-2 and 2-3 that receive the output of the Y decoder YD10, and Y switches that receive the output of the Y decoder YD11. It consists of 3-2 and 3-3. Each Y
The Y switches that receive the output of the decoder are arranged adjacent to each other.

The X address system has a high-order bit address A.
Address buffer 4 to which 2, A3, A4, A5 are input
3, 44, 45 and 46, an X predecoder 47 that receives their outputs, and X main decoders 0000 to 1111 that receive the outputs of the X predecoder 47. The X main decoders 0000 correspond to the respective rows so that the X main decoders 0000 access the memory cells in the lowest row 48.

For example, A5, A4, A3 and A2 are 1,
When 1, 1, 1, the memory cell in the top row 49 is selected, and when A1, A0 are 1, 1, the Y switches 3-2, 3-3 are opened, so that the data in the memory cell 50 is Is obtained as D2 via the I / O circuit 2, and the data in the memory cell 51 is obtained as D3 via the I / O circuit 3.

To aid in understanding, FIG. 5 shows the block diagram of FIG. 4 and the address allocation of the memory cells. Allocating the address of the memory mat by assigning the lower bit of the address to the Y address and the upper bit to the X address, selecting the column of the memory mat with the Y address, and selecting the row of the memory mat with the X address. Can be serialized in the row direction.

Further, since the X decoder is composed of a predecoder and a main decoder, and the main decoders are arranged in correspondence with the rows of the memory mat, for example, the row 49 corresponding to the higher address and the X main decoder 1111.
By deleting, the memory from addresses 0 to 59 becomes available. That is, in this case, 15 rows x 4 columns x 4
It can be easily changed to a memory of bit = 60 words × 4 bits.

As described above, it is possible to easily construct a memory in which the number of words is not the nth power of 2. In the example of FIG. 5, the number of columns is 4
Therefore, the number of word increments is four.

Although the configuration of FIG. 5 is a x4 bit configuration, if a x5 bit configuration is desired, one memory cell is added at each address of the memory mat on the left side as in the case of FIG. , Y switch and I / O circuit may be added correspondingly. On the contrary, in the case of reducing x3 bits by 1 bit, one memory cell may be reduced at each address of the memory mat on the right side, and the Y switch and the I / O circuit may be correspondingly reduced. Therefore, it can be seen that the number of bits can be set to 1.

As can be seen by comparing FIGS. 1 and 4, the address buffer, the X main decoder, the memory cell, the Y switch, and the I / O circuit have the same structure, and the X predecoder and the Y decoder have the same structure. Only different. That is,
Although there are two X addresses in FIG. 1 and four X addresses in FIG. 4, the configurations of the coders in the X main are the same, and only the number differs depending on the number of rows. Therefore, it is understood that if different types of X predecoders and Y decoders are prepared, it is possible to efficiently cope with a memory having a wide number of words simply by changing the types.

On the other hand, the above cited example (Japanese Patent Laid-Open No. 3-2
When the X decoder is integrally configured as in Japanese Patent Application No. 01298), when the number of X addresses changes from 2 to 4, the configuration also changes from 2 input AND to 4 input AND. Therefore, as the number of elements increases, it becomes difficult to arrange the memory mats corresponding to the rows, and the variable width of the number of words that can be supplied becomes narrow.

As shown in FIGS. 1 and 4, one Y
Since the two Y switches receiving the output of the decoder are arranged adjacent to each other, the memory cells having the same address are arranged next to each other in the memory mat. According to this, since the memory cells of the same address are collectively arranged, when the bit width is large, the division decoder is arranged to prevent the access time from deteriorating or control the power consumption reduction. Cheap. Also, control at the time of writing becomes easy.

As described above in detail, according to the present embodiment, the memory density is high, the access time is fast, the power consumption is low, and the step size of the number of words and the number of bits is fine. A compiled memory can be obtained.

Next, a procedure for generating the above-mentioned memory pattern will be described with reference to the flow of FIG.

First, the memory type such as 1 port or 2 port is designated, and the number of words or rows, the number of columns, and the bit width (data width) that determine the size and configuration of the memory are input. The number of rows = the number of words / the number of columns.

As a result, the compiler program is activated, and first, the number of address buffers is determined from the number of rows and the number of columns. For example, n of 2 as the number of words is 6
If it is not a power of (2 m power) <6 <(2 p power),
2 + 1 to satisfy m + 1 = p, that is, 2 ^ 3 =
The number of address buffers for 8 words, 3 are prepared.

Next, the type of Y decoder and the number to be arranged are determined from the number of columns. For example, in the case of FIG. 1, since there are two columns, two Y decoders each consisting of two inverters are used, and in the case of FIG.
And four Y decoders consisting of an inverter are used.

Next, the type of X predecoder and the number to be arranged are determined from the number of rows. For example, in the case of FIG. 1, since there are four rows, two predecoders each consisting of two inverters,
2 sets are used, and in the case of FIG. 4, there are 16 rows, so 2 inputs N
Two sets of four predecoders each consisting of an AND and an inverter are used.

Next, the number of Y switches and the number of I / O circuits are determined from the number of columns and the bit width. For example, in the case of FIG. 1, since 2 (columns) × 4 (bits) = 8, eight Y switches are used for left and right alignment, and four I / O circuits are used because it is 4 bits. In the case of FIG. 4, 4
Since (column) × 4 (bit) = 16, 16 Y switches are used for left and right alignment, and since it is 4 bits, I
Uses four / O circuits.

Next, the number of memory cells arranged in one column is determined from the bit width. For example, in the case of FIG. 1, since the width is 4 bits, two memory cells are arranged in one column on the right side. The same applies to the left side. Since FIG. 4 also has a 4-bit width, two memory cells are arranged in one column on both the right and left sides.

Next, the number of X main decoders and the corresponding number of memory cells arranged in the vertical direction are determined from the number of rows. For example, in the case of FIG. 1, since there are four rows, four main decoders and four memory cells are arranged correspondingly. In the case of FIG. 4, since there are 16 rows, 16 main decoders and 16 memory cells are arranged.

Then, based on the type and number of decoders and the like determined as described above, the layout of the memory in which each circuit element is arranged and wired according to the memory type configuration, that is, the configuration as shown in FIGS. Generate a pattern.

As described above, in the memory pattern of this embodiment, the structure of the address buffer, the X main decoder, the memory cell, the Y switch, and the I / O circuit is the same, but the structures of the X predecoder and the Y decoder are different. is there. In particular,
Since the basic configuration is a pattern in which X main decoders are regularly arranged in correspondence with rows, the number of words and bit width can be finely changed by simply determining the number of main decoders from the number of rows, and a desired memory pattern can be obtained. Can be easily generated, and the production of memory corresponding to a wide number of words can be made efficient.

FIG. 6 shows the configuration of the memory of another embodiment of the present invention.
Will be described. FIG. 6 shows a configuration of 4 rows × 2 columns × 4 bits, that is, 8 words × 4 bits. In FIG. 6, in order to avoid complication, the writing system and the like are omitted and only the reading system is shown. The memory mat on the left side, the Y switch, and the I / O circuit are omitted because they are similar to those on the right side.

The only difference from FIG. 1 is the wiring of the Y switch. That is, the Y switch 0 connected to the I / O circuit 2
-2 and 1-2 are arranged adjacent to each other, and Y switches 0-3 and 1-3 connected to the I / O circuit 3 are arranged adjacent to each other. Y switches 0-2 and 0-3 receive the output of Y decoder 0, and Y switches 1-2 and 1-3 receive the output of Y decoder 1. In this case, memory cells in different columns are arranged next to each other.

In FIG. 1, two wiring areas are required so that the line connecting the Y switches 0-2 and 1-2 and the line connecting the Y switches 0-3 and 1-3 are not short-circuited. In FIG. 6, Y
Switches 0-2 and 1-2, Y switches 0-3 and 1-3
Are adjacent to each other, the number of wiring areas connecting the Y switches is one. Therefore, even if the bit width is large, it is not necessary to increase the wiring area connecting the Y switches, and the density can be increased.

To facilitate understanding, FIG. 7 shows the block diagram of FIG. 6 and the address allocation of the memory cells. Since the wiring of the Y switch has changed, the address allocation of the memory cell has changed from FIG. 2, but the lower bit of the address is assigned to the Y address and the upper bit is assigned to the X address, and the column of the memory mat is selected by the Y address. , X addresses are used to select the rows of the memory mat, the addresses of the memory mats are sequentially assigned in the row direction.

Further, since the X decoder is composed of two predecoders and a main decoder and the main decoders are arranged corresponding to the rows of the memory mat, the row 70 corresponding to the upper address and the X main decoder 11 are arranged. By deleting, the memory from address 0 to address 5 becomes available. That is, in this case, 3 rows × 2 columns × 4 bits = 6
It can be easily changed to a memory of word × 4 bit structure. In this way, a memory in which the number of words is not the nth power of 2 can be easily constructed. In the example of FIG. 7, since the number of columns is 2, the number of word increments is 2.

Although the configuration of FIG. 7 has a x4 bit configuration, if a x5 bit configuration is desired, one column is added to the left memory mat as shown in FIG. A switch and an I / O circuit may be added correspondingly. On the contrary, in the case of reducing x3 bits by 1 bit, each column in the memory mat on the right side may be reduced by one and the Y switches and I / O circuits may be reduced correspondingly. Therefore, it can be seen that the number of bits can be set to 1.

Further, since the address signal terminal and the data signal terminal are arranged on the same side of the memory module, the memory module can be made rectangular without wasting space,
High-density memory can be realized. This also leads to faster memory and lower power consumption.

Further, since the memory mats are arranged on both sides of the X decoder, it is possible to reduce variations in the time required for the decoder signals to reach the memory mats, and it is possible to realize a high speed memory.

As described above in detail, according to the present embodiment, since the adjacent Y switches are connected to each other, the connection area can be further increased in density. Therefore, it is possible to obtain a compiled system memory having a high memory density, a high access time, a low power consumption, and a fine step size of the number of words and the number of bits.

The structure of a memory according to still another embodiment of the present invention will be described with reference to FIG. FIG. 9 shows a configuration of 4 rows × 2 columns × 4 bits, that is, 8 words × 4 bits.
However, FIG. 9 is an example of a memory having two ports A and B as read ports. In FIG. 9, in order to avoid complication, the writing system and the like are omitted and only the reading system is shown. The memory mat on the left side, the Y switch, and the I / O circuit are omitted because they are similar to those on the right side.

The structure of the A port section is the same as that in FIG. The configuration of the B port section is the same as that of the A port. The A port is arranged to be accessed from the lower side of the drawing, and the B port is arranged to be accessed from the upper side of the drawing. By arranging in this way, the memory module can be formed in a rectangular shape without generating unnecessary space, and a high-density memory can be realized. This also leads to faster memory and lower power consumption.

Further, it is possible to develop a 2-port memory into various configurations by the same idea as in FIG. 1 or 4. The address allocation of the memory cell in this case is the same as that in FIG. It is also possible to connect the Y switch as shown in FIG. The address allocation of the memory cell in that case is the same as in FIG.

As described above in detail, according to the present embodiment, the memory density is high, the access time is fast, the power consumption is low, and the step size of the number of words and the number of bits is fine. It is possible to obtain a read-out 2-port memory of the compiled method.

[0069]

According to the present invention, since the main decoder can be arranged so that the address allocation of the memory mats is made to correspond to the row serial numbers and the rows, the number of words and the number of bits of the memory circuit of the compiled system are provided. Has the effect of finely chopping.

Further, the memory density can be improved by the regular arrangement corresponding to the rows, the arrangement of the memories of different columns next to each other, the arrangement of two ports, and the like, so that a memory circuit suitable for a master slice type LSI such as a gate array can be provided.

According to the present invention, the predecoder whose configuration is changed and the main decoder whose configuration is not changed are separately arranged according to the number of bits of the X address. Therefore, a basic configuration in which a row and a main decoder have a one-to-one correspondence is provided. It can be maintained and can efficiently cope with the production of a wide number of words.

[Brief description of drawings]

FIG. 1 is a memory configuration diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the memory configuration of FIG. 1 and address allocation of memory cells.

FIG. 3 is a schematic diagram showing a configuration and a memory cell address allocation when the memory configuration of FIG. 2 is increased by 1 bit width.

FIG. 4 is a memory configuration diagram of another embodiment of the present invention.

5 is a schematic diagram showing the memory configuration of FIG. 4 and memory cell address allocation.

FIG. 6 is a memory configuration diagram of another embodiment of the present invention.

FIG. 7 is a schematic diagram showing the memory configuration of FIG. 6 and address allocation of memory cells.

8 is a schematic diagram showing a configuration and a memory cell address allocation when the memory configuration of FIG. 7 is increased by 1 bit.

FIG. 9 is a memory configuration diagram of two-port reading which is still another embodiment of the present invention.

FIG. 10 is a flowchart showing a pattern generation procedure for manufacturing the memory of the present invention.

[Explanation of symbols]

12, 13, 14 ... Address buffer, 0, 1 ... Y decoder, 15 ... X predecoder, 00, 01, 10, 11
... X main decoder, 20, 21 ... memory cell, 0-
2, 0-3, 1-2, 1-3 ... Y switch, I / O0,
I / O1, I / O2, I / O3 ... I / O circuit.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Hideo Hara 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Katsunori Koike 3-chome, Saiwaicho, Hitachi, Ibaraki 2-1 Hitachi Engineering Co., Ltd.

Claims (10)

[Claims] 1. A lower address bit is a Y address,
The upper bits of the address are assigned to the X address, the column of the memory mat is selected by the Y address, the row of the memory mat is selected by the X address, and the X decoder and the predecoder for receiving the output of the address buffer are selected. A compiled type semiconductor memory circuit device comprising a main decoder for receiving an output of the decoder, wherein the main decoder is arranged in a one-to-one correspondence with a row of the memory mat. 2. A lower address bit is set to a Y address,
The upper bits of the address are assigned to the X address, the column of the memory mat is selected by the Y address, the row of the memory mat is selected by the X address, and the X decoder receives the output of the address buffer and outputs the number of the upper bits. And a main decoder which receives the output of the predecoder and is not affected by the number of upper bits, and the main decoder is arranged in one-to-one correspondence with the row of the memory mat. Compiled semiconductor memory circuit device. 3. The semiconductor memory circuit device according to claim 1, wherein when the bit width is 2 bits or more, the memory mats are arranged on both sides of the main decoder. 4. The semiconductor memory circuit device according to claim 1, wherein memory cells having the same address are arranged next to each other in the memory mat. 5. A Y receiving an output of one Y decoder.
5. The semiconductor memory circuit device according to claim 4, wherein the switches are arranged next to each other. 6. The semiconductor memory circuit device according to claim 1, wherein the memory cells of different columns are arranged next to each other in the memory mat. 7. A Y switch connected to a certain I / O circuit is arranged next to each other.
The semiconductor memory circuit device described. 8. The semiconductor memory circuit device according to claim 1, wherein the address signal terminal and the data signal terminal are arranged on the same side of the memory module. 9. A memory read-out A port and a read-out B
In case of having two ports, the address signal terminal and the data signal terminal of the A port are the first of the memory module.
And the address signal terminal and the data signal terminal of the B port are arranged on the second side of the memory module, and the first side and the second side face each other. The semiconductor memory circuit device according to claim 1 or 2. 10. When a memory type that defines the number of ports, a word number or a row number, a column number, and a bit width according to the memory type are input, each circuit element is arranged and wired according to the following procedure. Generate a layout pattern,
A compiled semiconductor memory circuit device manufactured by the layout pattern. (A) The number of address buffers is determined from the number of rows (= number of words / number of columns) and the number of columns, (b) the number of columns to be arranged with the Y decoder type is determined from the number of columns, and (c) the X predecoder from the number of rows. The type and the number to be arranged are determined, (d) the number of columns, the number of Y switches and the number of I / O circuits are determined from the bit width, and (e) the number of memory cells arranged in one column is determined from the bit width. , (F) The number of main decoders and the number of corresponding memory cells are determined from the number of rows, and (g) the circuit elements determined as described above are arranged and wired according to the configuration of the memory type.