JPH0887491A - Vector computer - Google Patents

Abstract

PURPOSE: To efficiently hand over data at a connection between vector operation and scalar operation. CONSTITUTION: The vector computer is equipped with a control means 11 which performs execution control over vector and scalar operation instructions, vector registers 121 -12M, a vector arithmetic means 13, scalar registers 141 -14N, and a scalar arithmetic means 15, and the control means 11 has a means which performs execution control over a transfer instruction including vector discrimination information showing one end of a set of vector elements adjoining to a vector register at a transfer source (transfer destination) on it, scalar discrimination information showing one end of a set of scalar registers at the transfer destination (transfer source), and the number of vector elements as operands and is equipped with a block transfer means 16 which performs block transfer of the vector elements between the set of vector elements whose one end is indicated by the vector discrimination information and the set of scalar registers whose one end is indicated by the scalar discrimination information under control.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector computer having both a vector arithmetic unit and a scalar arithmetic unit and performing the same arithmetic operation to be performed on a large number of sets of data via the vector arithmetic unit.

[0002]

2. Description of the Related Art In a vector computer, a program to be executed generally has a repetitive operation (for example, a "DO loop described in FORTRAN") that composes the program at the time of compilation. It is vectorized for each))).

Further, in the execution process of the loop thus vectorized (hereinafter simply referred to as "vector loop"), the data to be operated stored in the main memory is included in the vector unit (vector processing device). When the vector operation is completed and the vector operation is completed, the content of the vector register storing the operation result is stored in the main memory.

However, in the process of executing such a vector loop, the total sum of the access times to the main memory at the start time and the end time of the loop has a large ratio to the time required for the vector operation related to the loop. If it occupies, the speeding up which is the purpose of vector operation will be impaired.

Further, as a method for increasing the speed in such a case, for example, if all the data to be operated and the operation result obtained in the middle of the vector loop can be stored in the vector register, the main memory is set in loop units. There is a method in which only the final result is stored in the main memory by passing data between the loops via the vector register without accessing the.

Further, a loop (hereinafter, simply referred to as a "scalar loop") including a statement for performing recursive reference (for example, an operation for performing vector regression calculation, sequential calculation, etc.) is generally a vector. Since it cannot be converted, calculation is performed via the scalar calculator.

However, the scalar arithmetic unit and the vector arithmetic unit are composed of separate hardware, and the scalar arithmetic unit cannot directly target the contents of the vector register built in the vector unit, and the vector arithmetic The instrument cannot directly operate on the contents of the scalar register built in the scalar unit (scalar processor).

Therefore, in the conventional vector computer,
An inter-register transfer instruction for directly transferring a single vector element (hereinafter simply referred to as “element”) between the vector loop and the scalar loop in order to enable data transfer between them. And a register-memory transfer instruction for transferring a plurality of elements to each other between these registers and the main memory, and by executing these instructions, the operation of the scalar loop subsequent to the vector loop is started. Transfers the contents of the vector register that stores the operation target to the desired scalar register prior to, or requests the contents of the scalar register that stores the operation target prior to the start of the operation of the vector loop that follows the scalar loop. Transfer to the vector register of.

Further, in such a vector computer,
It has an instruction to transfer the contents of the scalar register to all elements of the specified vector register.

[0010]

However, in such a conventional vector computer, when the data to be delivered between the vector loop and the scalar loop is composed of a plurality of elements, the above-mentioned register transfer instructions are individually executed. Must be executed for each element, and the transfer speed and the execution efficiency are reduced.

When the register-memory transfer instruction described above is used, data is temporarily transferred from the vector (scalar) register to a predetermined area of the main memory at the joint between the vector loop and the scalar loop. Further, data is transferred from the area to the scalar (vector) register.

However, the transfer of data from such a vector (scalar) register to the main memory requires a large overhead depending on the information amount of the data. In addition, the scalar unit has a cache memory for data to be operated, and in order to wait until a block of a predetermined size containing data to be transferred from the vector register or main memory is stored in the cache memory. The above-mentioned overhead has become even larger.

It is an object of the present invention to provide a vector computer that can efficiently transfer data at a joint between a vector operation and a scalar operation.

[0014]

FIG. 1 shows claims 1 to 4,
It is a principle block diagram of the invention as described in 7 and 8. Claim 1
According to the invention described in (1), a control means 11 constituting a control mechanism involved in execution of a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of individually holding vector data composed of a plurality of vector elements. Vector registers 12 _{1 to} 12 _M, and vector operation means 13 for performing vector operation on the vector data held in the plurality of vector registers 12 _{1 to} 12 _M under control logic.
A plurality of scalar registers 14 _{1 to} 14 _N that are logically or physically adjacent to each other and individually hold data corresponding to a single vector element, and a plurality of scalar registers 14 _{1 to} 14 _N In a vector computer including a scalar operation means 15 for performing a scalar operation on the generated data under control logic, the control means 11 includes a vector register which is a transfer source or a transfer destination, and a logical register on the vector register. Alternatively, the vector identification information indicating one end of a set of vector elements that are physically adjacent to each other, the scalar identification information indicating one end of a set of scalar registers to be a transfer destination or a transfer source, and the number of vector elements to be transferred. The vector register 12 is provided with a means for controlling the execution of the transfer instruction included as an operand.
A set of vector elements of which one end is indicated by the vector identification information among the vector elements whose storage areas are assigned to _{1 to} 12 _M , and a scalar register whose one end is indicated by the scalar identification information among the scalar registers 14 _{1 to} 14 _N The block transfer means 16 is provided for transferring blocks of vector elements equal in number to and from the set.

According to a second aspect of the present invention, the control means 11 constitutes a control mechanism for executing the vector operation instruction and the scalar operation instruction based on a predetermined control logic.
And a plurality of vector registers 12 _{1 to} 12 _M individually holding vector data composed of a plurality of vector elements,
A single vector element is arranged logically or physically adjacent to the vector operation means 13 for performing vector operation on the vector data held in the plurality of vector registers 12 _{1 to} 12 _M under control logic. A plurality of scalar registers 14 _{1 to} 14 _N that individually hold the data corresponding to
And a scalar operation means 15 for performing a scalar operation under control logic on the data held in the plurality of scalar registers 14 _{1 to} 14 _N.
1 includes first vector identification information indicating a vector register which is a transfer source or a transfer destination and one end of a set of vector elements which are logically or physically adjacent to the vector register, and other vector information. A second vector identification information indicating an end and a scalar identification information indicating one end of a set of scalar registers which is a transfer destination or a transfer source are included as an operand, and includes means for performing control related to execution of a transfer instruction. In the vector registers 12 _{1 to} 12 _M , a set of vector elements whose both ends are respectively indicated by the first vector identification information and the second vector identification information among the vector elements whose storage areas are allocated, and a scalar register One of 14 _{1 to} 14 _N performs block transfer between one end and a set of scalar registers indicated by the scalar identification information. It is characterized in that it comprises a sending means 21.

The invention according to claim 3 is predetermined.
Vector operation instructions and scalar operations based on control logic
Control means 11 constituting a control mechanism relating to the execution of instructions
And vector data consisting of multiple vector elements
Vector registers 12 held in₁~ 12_MWhen,
Multiple vector registers 12₁~ 12_MBe held in
Vector to perform vector operation on cuttle data under control logic
Is adjacent to the tor operation means 13 logically or physically
Data arranged according to a single vector element
A plurality of scalar registers 14 that individually hold₁~ 14_N
And a plurality of scalar registers 14₁~ 14_NHeld in
A scalar operator that applies scalar operations to data under control logic
In the vector computer including the stage 15, the control means 1
1 is a vector register that is the transfer source or transfer destination
And logical or physical on the vector register
A vector indicating one end of a set of vector elements adjacent to
Identification information and scalar destination that is the transfer destination or transfer source
The first scalar identification information indicating one end of the
Second scalar identification information indicating the other end of the
Includes means for controlling the execution of transfer instructions
Under control, vector register 12₁~ 12_MIn
One of the vector elements to which the memory area is allocated is
A set of vector elements indicated by Toru identification information and a scalar
Register 14 ₁~ 14_NBoth ends are the first
Indicated by the color identification information and the second scalar identification information
Block transfer between a set of scalar registers
It is characterized in that it comprises a block transfer means 31 for performing.

According to a fourth aspect of the present invention, the control means 11 constitutes a control mechanism for executing the vector operation instruction and the scalar operation instruction based on a predetermined control logic.
And a plurality of vector registers 12 _{1 to} 12 _M individually holding vector data composed of a plurality of vector elements,
A single vector element is arranged logically or physically adjacent to the vector operation means 13 for performing vector operation on the vector data held in the plurality of vector registers 12 _{1 to} 12 _M under control logic. A plurality of scalar registers 14 _{1 to} 14 _N that individually hold the data corresponding to
And a scalar operation means 15 for performing a scalar operation under control logic on the data held in the plurality of scalar registers 14 _{1 to} 14 _N.
1 is vector identification information indicating a vector register that is a transfer source or a transfer destination and one end of a set of vector elements that are logically or physically adjacent to the vector register, and a transfer destination or a transfer source. It includes a means for controlling the execution of a transfer instruction including a plurality of scalar identification information individually indicating a plurality of scalar registers as an operand, and under control, the vector registers 12 _{1 to} 12
_Of the vector elements whose storage areas are assigned to _M , a set of vector elements whose one end is indicated by vector identification information,
Among the scalar registers 14 _{1 to} 14 _N, the block transfer means 41 for performing transfer in vector element units is provided between each of the scalar registers indicated by a plurality of scalar identification information.

FIG. 2 is a block diagram showing the principle of the invention described in claims 5 and 6. According to a fifth aspect of the present invention, a control means 11 constituting a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and vector data composed of a plurality of vector elements are individually provided. A plurality of vector registers 12 _{1 to} 12 to hold
_M and vector operation means 13 for performing vector operation on the vector data held in the plurality of vector registers 12 _{1 to} 12 _M under control logic, are arranged logically or physically adjacent to each other, and are provided as a single unit. A plurality of scalar registers 14 ₁ to individually hold data corresponding to vector elements of
14 _N, and a scalar calculator 15 for performing a scalar operation under control logic on the data held in a plurality of scalar registers 14 _{1 to} 14 _N , the vector calculator has a controller 11 as a transfer source or a transferer. For executing a transfer instruction including, as an operand, vector identification information indicating a destination vector register and a vector element in which a storage area is allocated to the vector register, and scalar identification information indicating a transfer destination or a transfer source scalar register. Under the control, including the means for performing the related control, of the vector elements in which the storage areas are allocated to the vector registers 12 _{1 to} 12 _M , the scalar of the upper order or the lower order of the vector element indicated by the vector identification information is scalar. the registers 14 ₁ to 14 _N, and a scalar register indicated by the scalar identification information Characterized by comprising a transfer means 51 for transferring.

According to a sixth aspect of the invention, the control means 11 constitutes a control mechanism relating to the execution of the vector operation instruction and the scalar operation instruction based on a predetermined control logic.
And a plurality of vector registers 12 _{1 to} 12 _M individually holding vector data composed of a plurality of vector elements,
A single vector element is arranged logically or physically adjacent to the vector operation means 13 for performing vector operation on the vector data held in the plurality of vector registers 12 _{1 to} 12 _M under control logic. A plurality of scalar registers 14 _{1 to} 14 _N that individually hold the data corresponding to
And a scalar operation means 15 for performing a scalar operation under control logic on the data held in the plurality of scalar registers 14 _{1 to} 14 _N.
1 includes vector identification information indicating a vector register as a transfer source or a transfer destination and a vector element in which a storage area is allocated to the vector register, and scalar identification information indicating a scalar register as a transfer destination or a transfer source. The scalar register 14 ₁ includes means for controlling the execution of a transfer instruction included as an operand, and under control.
Among 14 to 14 _N , the vector element indicated by the vector identification information among the vector elements in which the storage areas are allocated to the vector registers 12 _{1 to} 12 _M for the higher order or the lower order of the scalar register indicated by the scalar identification information. And a transfer means 61 for performing transfer with

According to a seventh aspect of the present invention, in the vector computer according to any one of the first to third aspects, the control means 11 controls the number of vector elements, vector identification information and scalar identification information. , And means for individually correlating with a preset value and setting the number of vector elements subject to block transfer to “1” based on the result of the correlation.

The invention according to claim 8 is the vector computer according to any one of claims 1 to 3, wherein the control means 11 controls the number of vector elements, vector identification information, and scalar identification information. , Means for individually correlating with a preset value, setting the block transfer direction from a scalar register to a vector register based on the result of the correlation, and fixing the transfer source scalar register for each vector element It is characterized by including.

[0022]

In the vector computer according to the first aspect of the present invention, when the transfer instruction in which the operand includes the vector identification information, the scalar identification information, and the number of vector elements to be transferred, the control means 11 Such an instruction is decoded, and the operations of the vector registers 12 _{1 to} 12 _M , the vector arithmetic unit 13, the scalar registers 14 _{1 to} 14 _N , the scalar arithmetic unit 15 and the block transfer means 16 are controlled according to the result of the decoding. . The block transfer means 16
Under such control, the vector registers 12 ₁ to 12
_Of the vector elements whose storage area is allocated to _M , a set of vector elements whose one end is indicated by vector identification information,
Among the scalar registers 14 _{1 to} 14 _N , a block transfer of vector elements equal in number is performed between one end and a set of scalar registers indicated by the scalar identification information.

That is, since a plurality of vector elements are block-transferred between a desired vector register and a scalar register by a single instruction, data transfer between the scalar loop and the vector loop is performed by these registers. This is more efficient than the conventional example which is performed by repeatedly executing an instruction for transferring a single element directly or via the main memory.

In the vector computer according to the second aspect of the present invention, first vector identification information indicating a vector register as a transfer source or a transfer destination and one end of a set of vector elements on the vector register, and the first vector identification information The second vector identification information indicating the other end of the set is included in the operand instead of the vector identification information and the number of vector elements in the first aspect of the invention. The control means 11
A transfer instruction including such an operand is decoded in the same manner as in the first aspect of the invention, and each unit including the block transfer means 21 is controlled according to the result of the decoding.

Under such control, the block transfer means 21 has the first vector identification information and the second vector identification information at both ends of the vector elements whose storage areas are allocated to the vector registers 12 _{1 to} 12 _M. for a set of vector elements indicated by the information, the scalar registers 14 ₁ to
Block transfer is performed between 14 _N and a set of scalar registers whose one end is indicated by the scalar identification information.

That is, since a plurality of vector elements are block-transferred by a single instruction between the desired vector register and the scalar register, the data transfer between the scalar loop and the vector loop is performed by these registers. This is more efficient than the conventional example which is performed by repeatedly executing an instruction for transferring a single element directly or via the main memory.

In the vector computer according to the third aspect of the present invention, the first scalar identification information indicating one end of the set of scalar registers which is the transfer destination or the transfer source and the second scalar identification indicating the other end of the set. The information is included in the operand instead of the scalar identification information and the number of vector elements in the invention described in claim 1. The control means 11 claims a transfer instruction including such an operand.
Decryption is performed in the same manner as in the invention described in (1), and each unit including the block transfer means 31 is controlled according to the result of the decryption.

Under such control, the block transfer means 31 has the first scalar identification information and the second scalar identification information at both ends of the plurality of vector elements whose storage areas are allocated to the vector registers indicated by the vector identification information. Block transfer is performed with the scalar register indicated by the scalar identification information.

That is, since a plurality of vector elements are block-transferred by a single instruction between the desired vector register and the scalar register, the data transfer between the scalar loop and the vector loop is performed by these registers. This is more efficient than the conventional example which is performed by repeatedly executing an instruction for transferring a single element directly or via the main memory.

In the vector computer according to the invention described in claim 4, a plurality of scalar identification information individually indicating a plurality of scalar registers as a transfer destination or a transfer source are the scalar identification information in the invention described in claim 1 and It is included in the operand instead of the number of vector elements. Control means 11
Decodes a transfer instruction including such an operand in the same manner as the invention described in claim 1, and controls each unit including the block transfer means 31 according to the result of the decoding.

Under such control, the block transfer means 41 individually and for each of the plurality of vector elements having storage areas allocated to the vector register indicated by the vector identification information, a scalar register indicated by each scalar identification information. Transfer between.

That is, since a plurality of elements are collectively block-transferred between a desired vector register and a scalar register by a single instruction, data transfer between the scalar loop and the vector loop is performed by these elements. The efficiency is improved as compared with the conventional example in which a single element is transferred between registers directly or via main memory by repetitive execution of an instruction.

In the vector computer according to the invention described in claim 5, the operand includes the vector identification information and the scalar identification information in the same manner as in the invention described in claims 1 and 2, but the elements to be transferred are It does not necessarily include information indicating the number or the set of its elements. The control means 11 decodes the transfer instruction including such an operand in the same manner as in the invention described in claim 1, and controls each unit including the transfer means 51 according to the result of the decoding.

Under such control, the transfer means 51
Of the vector elements whose storage areas are allocated to the vector registers 12 _{1 to} 12 _M , _one of the high order or the low order of the vector element indicated by the vector identification information, among the scalar registers 14 _{1 to} 14 _N , Transfer is performed with the scalar register indicated by the scalar identification information.

That is, since the transfer of the high order or the low order of any element between the desired vector register and the scalar register is performed by a single instruction, the word of the information that is the target of the scalar operation and the vector operation. The data transfer between the scalar loop and the vector loop when the length and the arrangement on the register are different is more efficient than the conventional example in which a process for absorbing such a difference must be added separately. It

In the vector computer according to the invention described in claim 6, the operand includes the vector identification information and the scalar identification information as in the invention described in claims 1 and 2, but the elements to be transferred are It does not necessarily include information indicating the number or the set of its elements. The control means 11 decodes the transfer instruction including such an operand in the same manner as in the invention described in claim 1, and controls each unit including the transfer means 61 according to the result of the decoding.

Under such control, the transfer means 61
Of the scalar registers 14 _{1 to} 14 _N , the vector register 12 ₁ to
Of the vector elements whose storage area is allocated to 12 _M ,
Transfer is performed with the vector element indicated by the vector identification information.

That is, since the transfer between the desired vector register and the upper or lower order of the desired scalar register is performed by a single instruction, the word length of the information to be subjected to the scalar operation and the vector operation. The data transfer between the scalar loop and the vector loop when the arrangement on the register or register is different is more efficient than the conventional example in which a process to absorb such a difference must be added separately. .

In the vector computer according to the seventh aspect of the present invention, the control means 11 has the first to third aspects.
In the invention described in, the number of vector elements included in the operand, the first vector identification information, the second vector identification information, the first scalar identification information, the second scalar identification information, individually preset value And the number of vector elements to be block-transferred is set to "1" according to the result of the correlation.

That is, the vector register to be transferred,
The number of vector elements to be transferred is "1" when either the vector element or the scalar register is specific.
Is set to, the compatibility of the format of the instruction with the conventional transfer instruction for performing the transfer between the vector register and the scalar register for a single element is ensured.

In the vector computer according to the eighth aspect of the present invention, the control means 11 has the first to third aspects.
In the invention described in, the number of vector elements included in the operand, the first vector identification information, the second vector identification information, the first scalar identification information, the second scalar identification information, individually preset value The block transfer direction is set from the scalar register to the vector register according to the result of the correlation and the transfer source scalar register is fixedly set.

That is, the vector register to be transferred,
When either the vector element or the scalar register is specific, the contents of a single scalar register indicated by the scalar identification information is transferred to multiple vector elements located adjacent to the desired vector register. Therefore, compatibility of the format of the instruction with the conventional transfer instruction for performing such transfer is ensured.

[0043]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 3 is a diagram showing an embodiment corresponding to the invention described in claims 1 to 8.

In the figure, each field of the instruction register 70 is applied to a scalar unit 71, and the scalar unit is interconnected with a vector unit 72. The instruction register 70 has an instruction code field (hereinafter, “O”).
P ”. ), Vector register field (below,
Each referred to as a "V _i" or "V _l". ) And three general fields (hereinafter “S _j ”, “S _k ”, respectively)
It is called "S _l (or S _i )". ) Is set.

In the scalar unit 71, OP is given to the input of the instruction code register (OPR) 73 _S , the first input of the VU instruction sending control unit (VSC) 74 and the first input of the selector 75. V _i (S _i ) is given to one input of a vector register / address register (VRAR (hereinafter referred to as “VRAR”) 76 _S , and S _i and S _j
k is given to the first and second address inputs of the scalar register file (SR (hereinafter referred to as “SR”)) 77. S _l (V _l ) is given to the input of the address counter 78 _S , and its output is connected to the third address input of SR77. The first output of the SR77 is connected to the other input of VRAR76 _S, the output of which is connected to a second input of the selector 75. The second output of SR77 is selector 75
Connected to the third input of and the input of counting circuit 79 _S ,
Its output is connected to one input of a scalar register controller (SRC) 80. One output of the scalar register control unit 80 is connected to the control input of SR77. One output of the instruction code register 73 _S is the VU instruction sending control unit 7
4 is connected to the second input of the instruction code register 73 _S
The other output of is connected to the second input of the scalar register controller 80. The other output of the scalar register control unit 80 is connected to the control input of SR77, and the third output of SR77 is connected to the fourth input of the selector 75. One output of the VU command transmission control unit 74 is connected to the selection input of the selector 75.

In the vector unit 72, the output of the selector 75 is the instruction code register 73 _V , VRAR.
76 _V , element number register (NR) 81 and VR write register (VRWR) 82 are connected to the inputs, and the other outputs of the VU command sending control unit 74 are connected to the control inputs of these registers. The output of the instruction code register 73 _V is connected to one input of the vector register control unit (VRC) 83, and the output of the element number register 81 is the counting circuit 79.
It is connected to the other input of the vector register control unit 83 via _V. VRAR76 _V output vector register file (VR (hereinafter, referred to as "VR".)) Via the address counter 78 _V 84 connected to the address inputs, the output of the VR write register 82 is connected to an input of VR84. The first output of the vector register control unit 83 is connected to the control input of the VR 84, and its output is the S arranged in the scalar unit 71 via the register (R) 85.
Connected to the input of R77. Vector register control unit 8
The second output of 3 is connected to the control input of register 85,
The third output of the vector register control unit 83 is connected to the third input of the scalar register control unit 80.

Each of the above-mentioned units is connected to the corresponding input / output of a micro controller (not shown) that controls them based on the micro program control system. Further, the scalar arithmetic unit that performs an arithmetic operation on the data stored in the SR77 and the vector arithmetic unit that performs a vector arithmetic operation on the elements stored in the VR 84 are mounted in the scalar unit 71 and the vector unit 72, respectively. However, since it is not directly related to the present invention, its illustration and description are omitted here.

Further, regarding the correspondence between the present embodiment and the block diagrams shown in FIGS. 1 and 2, the instruction register 70 and the microcontroller (not shown) are the control means 11.
The VR 87 corresponds to the vector registers 12 _{1 to} 12 _M , and the vector calculator described above corresponds to the vector calculating means 1.
3, the SR 77 corresponds to the scalar registers 13 _{1 to} 13 _N , the scalar calculator described above corresponds to the scalar calculation means 15, the instruction code registers 73 _s , 73 _V , the VU instruction sending control unit 74, and the selector 75. , VRAR76 _s, 7
6 _V , address counter 78 _s , 78 _V , counting circuit 79
_s , 79 _V , the scalar register control unit 80, the element number counter 81, the VRWR 82, the vector register control unit 83, and the register 85 are block transfer means 16, 21, and 3.
1 and 41 and transfer means 51 and 61.

FIG. 4 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 1. The operation corresponding to the invention described in claim 1 of the present embodiment will be described below with reference to FIGS. 3 and 4. The above-mentioned microcontroller gives predetermined timing to each of the above-mentioned parts and monitors the state to control the overall operation. However, such operation will be described below except for matters worthy of special mention. Omit it.

In the present embodiment, as shown in FIG. 5A, in the field of the instruction register 70, V _i is set to the vector register number r _V which is the data transfer source (transfer destination), S _j is set to the scalar register number r _p in which the head pointer p of the element to be the transfer source (transfer destination) among the elements of the vector register is stored in advance, and S _k is the element of the data to be transferred. The number r _{n of the} scalar register in which the number n is stored in advance is set, and the number r _{s of the} leading scalar register which is the transfer destination (transfer source) is set in S _l .

When the instruction code "Request block transfer from vector register (scalar register) to scalar register (vector register)" is set to OP together with the operand having such a configuration, the scalar unit 71 causes the instruction code register The instruction code is held in 73 _s .

The scalar register control unit 80 integrally controls the following access to the SR 77 based on the instruction code held in the instruction code register 73 _S in this way.

The upper order of VRAR76 _s is V _i
The vector register number r _V set to is held. The SR 77 reads the head pointer p from the scalar register indicated by the number r _p described above, and the head pointer is held in the lower order of VRAR76 _s .

The above-mentioned number r _s is preset in the address counter 78 _s . Further, SR77 determines the number of elements n from the scalar register indicated by the number r _n described above.
Is read out, and the number of elements is preset in the counting circuit 79 _s .

The VU command transmission control unit 74 analyzes the above-mentioned command code, and gives the selection signal to the selector 75 based on the result, thereby giving the number of elements n to the vector unit 72.

On the other hand, in the vector unit 72, the element number n thus given is held in the element number register 81, and is further preset in the counting circuit 79 _V via the element number register.

Further, in the scalar unit 71, the VU command transmission control section 74 controls the selector 75 based on the result of the analysis of the above-mentioned command code to select the command code at a predetermined timing, and further, After the elapse of a predetermined time, the vector register number r _V held in the VRAR 76 _s and the head pointer p are selected and given to the vector unit 72 together.

In the vector unit 72, the instruction code thus given is held in the instruction code register 73 _V , the vector register number r _V and the head pointer p are held in VRAR 76 _V , and the VRA thereof is also held.
It is preset to the address counter 78 _V via R.

Upon completion of such a series of operations, the vector register control unit 83 causes the instruction code register 73 _V
The instruction code stored in the register 84 is analyzed, and based on the result, the access control of the VR 84 is performed in synchronization with the access control of the SR 77 performed by the scalar register control unit 80, and the opening / closing control of the register 85 is performed.

The operation relating to the data transfer between the SR 77 and the VR 84 performed under such control differs depending on the transfer direction of the data, and therefore will be described individually below.

When an instruction requesting data transfer from the vector register to the scalar register is given,
In the vector unit 72, the vector register control unit 8
Of the vector registers included in the VR 84, 3 outputs a read command at a predetermined timing with respect to the vector register element indicated by the number of the vector register held in the address counter 78 _v and the head pointer. The element read in response to such a read command is held in the register 85 and given to the scalar unit 71 under the control of the vector register control unit 83.

In the scalar unit 71, the element thus given is the register number held in the address counter 78 _s of the scalar registers included in the SR 77 under the control of the scalar register control unit 80. It is stored in the scalar register shown (FIG. 4).

In this way, the elements are stored in the scalar register.
When delivered, the address counter 78 _s, 78_VThe content of
Both incremented and counting circuit 79_s, 79_V
The contents of are decremented together. Scalar register control
The unit 80 and the vector register control unit 83 are respectively
Counting circuit 79_s, 79_VMonitor the contents of
Until it becomes "0", SR77, VR84, register 85
For each element, repeat the transfer for each element (FIG. 4, ...).
Control.

When the scalar register issues an instruction requesting data transfer to the vector register, the scalar unit 71 of the scalar register control unit 80 causes the address counter 78 of the scalar registers included in the SR 77. A read instruction of the scalar register indicated by the register number held in _s is output at a predetermined timing, and that timing is output by the VU instruction sending control unit 74.
To notify. When such notification is given, the VU command sending control unit 74 gives a selection signal to the selector 75, so that the data read from the SR 77 according to the above-mentioned read command (given to each element of the vector register is given. ) To the vector unit 72.

On the other hand, in the vector unit 72, VRW
The R 82 temporarily holds the individual elements provided from the scalar unit 71 as described above. When such an element is held in the VRWR 82, the vector register control unit 83, regarding the element indicated by the number of the vector register held in the address counter 78 _v and the head pointer among the vector registers included in the VR 84, Give a write command.

The elements held in the VRWR 82 are written in the vector register designated by the address counter 78 _V when such a write command is given (FIG. 4 (a)).

When such element-wise transfer is completed, the contents of the address counters 78 _s and 78 _V are incremented, and the contents of the counting circuits 79 _s and 79 _V are decremented. Furthermore, the above-mentioned transfer is repeatedly performed until the value of the counter circuit thus decremented becomes "0" (FIG. 4 (b), ...).

As described above, according to the present embodiment, the block transfer of a plurality of adjacent elements is surely performed between the desired vector register and the scalar register, and the inter-register transfer for transferring only a single element is performed. The transfer efficiency is improved and the overhead at the seam between the vector loop and the scalar loop is significantly reduced, as compared with the related art including instructions.

FIG. 6 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 2. Hereinafter, FIG. 3 and FIG.
The operation corresponding to the invention described in claim 2 of the present embodiment will be described with reference to FIG.

In this embodiment, as shown in FIG.
Field S of command register 70_kThe days that should be transferred
Number r of the scalar register that stores the number n of data elements_nTo
Instead, the last element of the multiple elements to be transferred is
Pointer p_eIs the number of the scalar register previously stored
Issue r_peIs set, but other fields V_i, S_j,
S_lFor the information set in, refer to the above-mentioned claim 1.
Since it is the same as the corresponding embodiment, its explanation will be given here.
Omit it. Scalar unit 71 and vector unit
Each part of the packet 72 is
Toll register (scalar register) to scalar register
Request block transfer to (vector register)
Command code is set to OP of the instruction register 70
In this case, please refer to "
Processing according to the first aspect of the invention described above.
The element-wise transfer is repeated as in the corresponding embodiment. did
Therefore, here is a description of the operation related to such transfer.
Is omitted. The microcontroller is based on the block described above.
S no matter which direction the transfer is, S _kNumber set to
r_pePointer p stored in the scalar register indicated by
_eValue and address counter 78_VHeld in lower order
If the two values match, the element-wise transfer is performed.
Abort.

Therefore, according to this embodiment, claim 1
Similar to the embodiment corresponding to the invention described in (1), the block transfer of a plurality of adjacent elements between the desired vector register and the scalar register is surely performed (FIG. 6 ,,
...), the transfer efficiency is improved as compared with the prior art, and the overhead at the joint between the vector loop and the scalar loop is significantly reduced.

In this embodiment, the pointer p mentioned above is used.
_Although the value of _e is compared with the value held in the address counter 78 _V to terminate the element unit, the present invention is not limited to such a configuration and, for example, precedes the start of the transfer operation. The difference between the value of the pointer p _e and the pointer p of the head element held in the lower order of VRAR76 _V is preset in the counting circuits 79 _s and 79 _V , and the embodiment corresponding to the invention according to claim 1 is provided. Similarly, censoring may be performed when the count values of these counting circuits become “0”.

FIG. 7 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 3. Hereinafter, FIG. 3 and FIG.
The operation corresponding to the invention described in claim 3 of the present embodiment will be described with reference to FIG.

In the present embodiment, as shown in FIG. 5 (3), in the field S _k of the instruction register 70, a pointer p _e indicating the last element is replaced with a plurality of scalar registers to be transferred. , The scalar register number r _se at the end is set, but the information set in the other fields V _i , S _j , and S _l is the same as that in the embodiment corresponding to claim 1 described above. The description is omitted here.

In each section of the scalar unit 71 and the vector unit 72, the instruction code "requesting block transfer from the vector register (scalar register) to the scalar register (vector register)" is sent to the OP of the instruction register 70 together with such an operand. When set, the element-by-element transfer is repeated in the same manner as in the embodiment corresponding to the invention described in claim 1 above, except for the "processing relating to the determination of the processing termination condition" described later. Therefore, the description of the operation related to such transfer is omitted here.

The microcontroller is based on the block described above.
S no matter which direction the transfer is, S _kNumber set to
r_seAnd address counter 78_sScalar register held by
The number of the star is compared, and if both match, the
Abort the transfer.

Therefore, according to this embodiment,
Similar to the embodiment corresponding to the invention described in (1), the block transfer of a plurality of adjacent elements between the desired vector register and the scalar register is surely performed (FIG. 7 ,,
...), the transfer efficiency is improved as compared with the conventional one, and the overhead at the joint between the vector loop and the scalar loop is significantly reduced.

In this embodiment, the above-mentioned number r_seWhen
Address counter 78_sOf the scalar register held in
The element-by-element censoring is performed by comparing with the number
However, the present invention is not limited to such a configuration, and for example,
The number r precedes the start of the sending operation _seAnd VRAR76_sIn
Number r of the held first scalar register_sTotal difference with
Number circuit 79_s, 79_VAnd preset to claim 1
As in the embodiment corresponding to the invention of
The censoring may be performed when the numerical value becomes “0”.

FIG. 8 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 4. Hereinafter, FIG. 3 and FIG.
The operation corresponding to the invention described in claim 4 of the present embodiment will be described with reference to FIG.

In the present embodiment, as shown in FIG. 5 (4), in the field of the instruction register 70, V _i is the data transfer source (transfer destination) in the same manner as the embodiment corresponding to claim 1.
The vector register number r _V is set to
The numbers r _s1 , r _s2 , and r _{s3 of the} scalar registers that are the transfer destinations (transfer sources) are individually set in _j , S _k , and S _l . Note that the numbers of these scalar registers may be the same or different.

In the scalar unit 71, when the instruction code "request block transfer from vector register (scalar register) to scalar register (vector register)" is set to OP together with the operand having such a configuration, the instruction The code register 73 _s holds the above-mentioned instruction code, and the upper order and the lower order of the VRAR 76 _s respectively have the vector register number r _V set to the above-mentioned V _i and a pointer of a predetermined head element. (Here, it is set to “0” for simplicity.) And are held.

Further, the address counter 78 _s has S
_The scalar register number r _s1 set to _j is preset, and “1” is preset in each of the counting circuits 79 _s and 79 _V.

The VU command transmission control section 74 analyzes the above-mentioned command code and selects the selector 7 based on the result.
By controlling 5, the instruction code is selected at a predetermined timing, and after the elapse of a predetermined time, the vector register number r _V held in VRAR76 _s and the pointer value of the first element are selected. And give them to the vector unit 72 together.

On the other hand, in the vector unit 72, the instruction code thus provided is the instruction code register 7
3 _V is held, and with the value of the pointer of the number r _V and the first element of the vector register is held in VRAR76 _V, the address counter 78 _V via the VRAR
Is preset to.

Upon completion of such a series of operations, the vector register control unit 83 causes the instruction code register 73 _V
The instruction code stored in the register 84 is analyzed, and based on the result, the access control of the VR 84 is performed in synchronization with the access control of the SR 77 performed by the scalar register control unit 80, and the opening / closing control of the register 85 is performed.

Regarding the transfer operation of the element unit between the SR 77 and the VR 84 performed under such control, the embodiment corresponding to the invention described in claim 1 mentioned above also in the transfer direction of both of the data. Therefore, the description thereof is omitted here.

The transfer for each element is completed (see FIG. 8).
) And the contents of the counting circuits 79 _s and 79 _V are both decremented, and the contents of the address counters 78 _s and 78 _V are both incremented to “0”. The scalar register control unit 80 and the vector register control unit 83
In this way, when it is detected that the contents of the counting circuits 79 _s and 79 _V have become “0”, the fact is notified to the microcontroller.

When the microcontroller recognizes such a notification, the instruction code registers 73 _s , 73 _V , V
The contents of the RAR 76 _s and the address counter 78 _V are not updated at all, and the counting circuits 79 _s , 7
"1" is preset again to 9 _V and the number of the scalar register is preset to the address counter 78 _s . Further, the microcontroller similarly repeats the element-by-element transfer for the scalar register numbers r _s2 and r _s3 set in S _k and S _l , respectively (FIG. 8, FIG.
…).

Therefore, according to the present embodiment, the elements adjacently arranged on the desired vector register are surely transferred individually to and from any scalar register, and transfer is performed only for a single element. Compared to the conventional example that has a register-to-register transfer instruction, the transfer efficiency is improved and the overhead at the joint between the vector loop and the scalar loop is significantly reduced, and at the same time, the scalar register to be the transfer destination or transfer source can be specified. It becomes possible to do it flexibly.

In the present embodiment, the valid scalar register numbers are individually set in the fields S _{j to} S _k . However, for example, when a nonexistent scalar register number is set, The transfer process may be terminated or the transfer process corresponding to the number may be suspended under the control of the microcontroller.

Further, in the present embodiment, the processing for setting "1" in the counting circuit 79 _V is directly performed by the microcontroller, but it may be set at the same time as the element number register 81. The given value “1” is passed through the selector 75 to the element register 8
1 may be further transferred to 1, and may be set in the counting circuit 79 _V via the element register 81.

Furthermore, in this embodiment, the counting circuits 79 _s ,
When the count value of 79 _V becomes "0", the transfer processing for the other scalar registers is restarted, but the present invention is not limited to such a configuration and, for example, does not use these counting circuits. A similar reboot could be done under the initiative of the microcontroller.

In this embodiment, the scalar register numbers are individually set in the fields S _{j to} S _k , but for example, in these fields, the scalar register numbers to be the transfer destinations (transfer sources) are set. You may arrange | position the bitmap corresponding to a number.

FIG. 9 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 5. Hereinafter, FIG. 3 and FIG.
The operation corresponding to the invention described in claim 5 of this embodiment will be described with reference to FIG.

In this embodiment, as shown in FIG. 5 (5), in the field of the instruction register 70, V _i is set to the vector register number r _V which is the data transfer source (transfer destination), S _j is given a scalar register number r _p indicating the pointer p of the vector register element, and S _l is set to the transfer destination (transfer source) scalar register number r _s, but S _k Is not set at all.

In the scalar unit 71, together with the operand having such a configuration, an instruction code "request transfer from the upper (lower) order of the vector register (scalar register) to the scalar register (upper (lower) order of the vector register)" Is set to OP, it is pointed to by the pointer p among the elements of the vector register indicated by r _V based on the procedure substantially similar to the embodiment corresponding to the invention described in claim 1. Only things are transferred.

However, regarding the process of such a transfer operation, the counting circuits 79 _S and 79 _V and the element number register 8
"1" is preset to 1 under the control of the microcontroller, and the vector register control unit 83 accesses only the upper order (or the lower order) to the VR 84 based on the instruction code held in the instruction code register 73 _V. Is different from the embodiment corresponding to the invention described in claim 1.

As described above, according to this embodiment, as shown in FIG.
As shown in (b), data is reliably transferred between the upper or lower order of the elements arranged on the desired vector register and an arbitrary scalar register.

Therefore, in this embodiment, the register length, the data word length, and the arrangement of the data are set between the SR77 in which the general-purpose registers and the floating point registers are mixed and the vector register which is used for both the integer operation and the floating point operation. Data is efficiently transferred by absorbing the differences.

Regarding such data transfer, for example, the lengths of the vector register and the scalar register are n bits and m (<n) bits, respectively, and the vector unit 72 performs the same operation as the scalar unit 71. This is effective when the integer operation based on the method is performed on the upper (lower) order as the operation target, and the overhead at the joint between the vector loop and the scalar loop is reduced, and the operation efficiency is improved.

In the present embodiment, the vector register control unit 83 commands the VR 84 to access only the upper order (or lower order), but the present invention is not limited to such a configuration. For the word length and arrangement of the data held in the register 85 or effectively output from the register in synchronization with such a command,
It may be variably set in conjunction with a command given to the VR 84.

Further, in the present embodiment, the transfer target is limited to a single element, but in the present invention, if the number of elements can be surely given by the contents of a desired register or main memory, a plurality of elements can be transferred. It is also possible to apply to perform the same transfer for the element of.

FIG. 10 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 6. The operation corresponding to the invention described in claim 6 of the present embodiment will be described below with reference to FIGS. 3, 5 and 10.

In this embodiment, the parameter set in the field of the instruction register 70 is the same as that of the embodiment corresponding to the invention described in claim 5, as shown in FIG. 5 (6), and Between the vector register and the scalar register indicated by such parameters, a single element is transferred according to a procedure substantially similar to that of the embodiment corresponding to the invention described in claim 5.

However, regarding the process of such transfer operation, the scalar register control unit 80 instructs the SR77 to access only the upper order (or the lower order) based on the instruction code held in the instruction code register 73 _s. In addition, the vector register control unit 83 is different from the embodiment corresponding to the invention according to claim 1 in that the vector register control unit 83 commands access in parallel for both the upper order and the lower order.

As described above, according to this embodiment, as shown in FIG.
As shown in (b), data is reliably transferred between the upper or lower order of the desired scalar register and the element of any vector register.

Therefore, in this embodiment, the length of the M register is larger than the length (n bits) of the vector register used for the double precision floating point operation, and is used for the extended double precision floating point operation. For scalar registers, when double-precision decimal point arithmetic is performed on that scalar register, data is efficiently passed only to the upper (lower) order that is the target of the arithmetic, and at the joint between the vector loop and scalar loop. The overhead is reduced and the calculation efficiency is improved.

In the present embodiment, the scalar register control unit 80 sends the SR77 an upper order (or a lower order).
However, the present invention is not limited to such a configuration. For example, the word length and arrangement of data held in the register 85 or effectively output from the register are given to the SR77. The variable setting may be performed in conjunction with the command that is issued.

Further, in the present embodiment, the transfer target is limited to a single element, but in the present invention, if the number of elements is surely given by the contents of a desired register, main memory, etc., a plurality of elements can be transferred. It is also possible to apply to perform the same transfer for the element of.

The operation of this embodiment corresponding to the invention of claim 7 will be described below. In the present embodiment, as shown in FIG. 5 (7), in the field of the instruction register 70, the number of a predetermined specific scalar register (for example, one which is not mounted in the scalar unit 71) is designated as S _k . r _n ′
Is set, and the same settings as those in the embodiment corresponding to the invention described in claim 1 are made in the other fields.

Further, each part is contracted based on such settings.
Elements similar to the embodiment corresponding to the invention described in claim 1
Repeat each transfer, but prior to the start of such a transfer
Then, the microcontroller is_kNumber r set to
_n′ Is the number of the specific scalar register
If you know, the counting circuit 79_sGives the number of elements to "1", and
The number of elements is set to the element number register 8 via the gate circuit 75.
1 and counting circuit 79 _VGiven to.

As described above, according to the present embodiment, when a specific number is given as the number of the scalar register which gives the number of elements to be transferred, the vector register and the scalar are provided for a single element as in the conventional example. Data can be passed to and from the register.

Therefore, since the instruction code of the conventional instruction that realizes such a transfer can be used as it is, it is possible to save the instruction code allocation, and the format of the operand is compatible with the conventional instruction. The data transfer mode can be expanded while maintaining the above.

Further, with respect to a program coded by using such a conventional instruction, the vector computer to which the present embodiment is applied is subjected to extremely slight modification,
Alternatively, it is executed by regenerating without any modification.

The operation of this embodiment corresponding to the invention of claim 8 will be described below. In the present embodiment, as shown in FIG. 5 (8), in the field of the instruction register 70, the number of a predetermined specific scalar register (for example, a register that is not mounted in the scalar unit) is set in S _k . r _n ′ is set, and other fields are set similarly to the embodiment corresponding to the invention described in claim 1. However, the number r _V set in V _i indicates a vector register which is only a transfer destination, and the number r _s set in S _l indicates a head scalar register which is only a transfer source.

Further, each unit repeats the transfer from the scalar register to the vector register for each element based on the above setting, in substantially the same manner as the embodiment corresponding to the invention described in claim 1. However, the microcontroller refers to the number r _n 'set in S _k each time such element-wise transfer is completed, and if the number is the number of the specific scalar register described above, the address counter 78 _s
The process of incrementing the contents of is omitted.

Therefore, according to this embodiment, when a specific number r _n ′ is given as the number of the scalar register which gives the number of elements to be transferred, a desired single scalar register is provided as in the conventional example. The contents of is passed to all (or some of several) elements of the desired vector register.

Therefore, since the conventional instruction code for realizing such delivery can be used as it is, the instruction code allocation can be spared and the operand format can be compatible with the conventional instruction. The data transfer form can be expanded.

Further, with respect to a program coded by using such a conventional instruction, the vector computer to which the present embodiment is applied is subjected to extremely slight modification,
Alternatively, it is executed by regenerating without any modification.

In the embodiments corresponding to the inventions described in claims 7 and 8, the number of the scalar register not mounted in the scalar unit 71 is set as the specific scalar register number r _n ′. However, the present invention is not limited to such numbers. For example, all the bits are “1” in one of a plurality of arranged scalar registers such as a scalar unit installed in many vector computers in recent years. When a zero register fixedly set to "0" is included, the content of the zero register is not set to an arbitrary value and cannot be applied as an operand that specifies a variable. A number indicating such a zero register may be set.

Further, in general, "0" is often assigned to the number indicating such a zero register, and undefined fields in the operands of the instruction are generally expanded in future. In many cases, it is recommended to set "0" to correspond to.

Therefore, in the vector computer adapted to such a recommendation, compatibility with the present embodiment is assured with respect to the conventional instruction in which the field S _k is undefined, and the conventional object code is not changed at all. It is executed as it is.

In each of the above embodiments, the selector 7
5 is an SR under the control of the VU command transmission control unit 74 in accordance with the command code, the vector register address, and the number of elements.
The data read from 77 is time-division-multiplexed and given to the vector unit 72, but the present invention is not limited to such a configuration. Unit 72
A dedicated transmission path may be provided between and.

Further, in each of the above-mentioned embodiments, the scalar unit 71 and the vector unit 72 are provided with the instruction code registers 73 _s , 73 _V , VRAR76 _s and 7 _V , respectively.
6 _V , address counters 78 _s , 78 _V, and counting circuits 79 _s , 79 _V are provided, but these may be single as long as there is no timing restriction.

Further, in each of the above-described embodiments, the transmission line for each element between the vector register and the scalar register is separated into the transmission line via the selector 75 and VRWR 82 and the transmission line via the register 85. The present invention is not limited to such a configuration, and these transmission lines may be integrated.

Further, in each of the above-described embodiments, the scalar register control unit 80 and the VU instruction sending control unit 74 are separately provided and mounted in the scalar unit 71, and the vector register control unit 83 is mounted in the vector unit 72. However, the present invention is not limited to such a configuration, for example,
These parts may be partly or wholly merged, and the mounting positions may be the scalar unit 71,
It may be set in any of the vector units 72.

Further, in each of the above-described embodiments, the numbers of vector registers and scalar registers are set as literals in V _i and S _l of the operand fields, and S _k is a desired variable (for example, The number of the scalar register in which the number of elements n) is set is set as a literal, but the present invention is not limited to such an operand format. For example, V _i and S _l include vector registers and scalar registers. The number of the scalar register in which the number is set or the area on the main memory may be set, or the number of elements n or the like may be directly set in S _k as a literal.

[0128]

As described above, in the inventions according to claims 1 to 4, a plurality of elements are collectively block-transferred between a desired vector register and a scalar register by a single instruction.

According to the fifth aspect of the invention, the transfer of the high order or the low order of any element is performed by a single instruction between the desired vector register and the scalar register.

According to the sixth aspect of the invention, the transfer between the desired vector register and the high order or low order of the scalar register is performed by a single instruction. According to the invention described in claim 7, a vector register to be transferred,
The number of vector elements to be transferred is "1" when either the vector element or the scalar register is specific.
Is set to, and only single elements are transferred.

According to the invention described in claim 8, when any one of the vector register, the vector element and the scalar register to be transferred is specific, the content of the single scalar register indicated by the scalar identification information is desired. Is transferred to the vector elements located adjacent to the vector register of.

That is, as compared with the conventional example, the data transfer between the scalar loop and the vector loop is more efficient, and the difference in the word length of the data to be transferred and the arrangement on the register are more efficient. Traditional transfer instructions and instructions that absorb and transfer between a vector register and a scalar register for a single element or transfer the contents of a single scalar register to adjacent elements on a vector register Format compatibility is ensured.

Therefore, in the vector computer to which the present invention is applied, when the data to be passed between the vector loop and the scalar loop is composed of a plurality of elements, the upward compatibility with the conventional example is ensured and The overhead related to delivery is reduced and the operation speed and performance are improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the invention according to claims 1 to 4, 7 and 8.

FIG. 2 is a principle block diagram of the invention described in claims 5 and 6.

FIG. 3 is a diagram showing an embodiment corresponding to the invention described in claims 1-8.

FIG. 4 is a diagram explaining an operation of the present embodiment corresponding to the invention described in claim 1.

FIG. 5 is a diagram showing contents of operands in each embodiment.

FIG. 6 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 2;

FIG. 7 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 3;

FIG. 8 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 4;

FIG. 9 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 5;

FIG. 10 is a diagram for explaining the operation of this embodiment corresponding to the invention described in claim 6;

[Explanation of symbols]

11 control means 12 vector register 13 vector operation means 14 scalar register 15 scalar operation means 16, 21, 31, 41 block transfer means 51, 61 transfer means 70 instruction register 71 scalar unit 72 vector unit 73 instruction code register (OPR) 74 VU Instruction sending controller (VSC) 75 Selector 76 Vector register / address register (VRA
R) 77 scalar register file (SR) 78 address counter 79 counting circuit 80 scalar register control unit (SRC) 81 element number register (NR) 82 VR write register (VRWR) 83 vector register control unit (VRC) 84 vector register file ( VR) 85 register (R)

Claims (8)

[Claims] 1. A control means constituting a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the logical register on that vector register. Or, vector identification information indicating one end of a set of vector elements that are physically adjacent to each other, scalar identification information indicating one end of a set of scalar registers to be a transfer destination or a transfer source, and the number of vector elements to be transferred. Has a means for controlling the execution of a transfer instruction including as an operand, and under the control, one of vector elements having a storage area allocated to the vector register, one end of which is indicated by the vector identification information. And a block of one of the scalar registers whose one end is represented by the scalar identification information, the block transfer means for performing block transfer of vector elements equal to the number. Vector calculator. 2. A control means forming a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the logical register on that vector register. Or, first vector identification information indicating one end of a set of vector elements that are physically adjacent to each other, second vector identification information indicating the other end of the set, and a set of scalar registers as a transfer destination or a transfer source. Of the vector element in which a storage area is allocated to the vector register under the control, and both ends of the vector element are the scalar identification information indicating one end of A block is provided between a set of vector elements indicated by the first vector identification information and the second vector identification information and between the set of scalar registers of which one end is indicated by the scalar identification information among the scalar registers. A vector computer comprising block transfer means for transferring. 3. A control means constituting a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the logical register on that vector register. Or, vector identification information indicating one end of a set of vector elements that are physically adjacent to each other, first scalar identification information indicating one end of a set of scalar registers that is a transfer destination or a transfer source, and the other end of the set. A second scalar identification information and a means for controlling the execution of a transfer instruction included as an operand, wherein, under the control, one of the vector elements having a storage area allocated to the vector register has the vector identification Block transfer is performed between a set of vector elements indicated by information and a set of scalar registers of which both ends are indicated by the first scalar identification information and the second scalar identification information, respectively, of the scalar register. A vector computer comprising block transfer means. 4. A control means forming a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the logical register on that vector register. Execution of a transfer instruction that includes, as operands, vector identification information indicating one end of a set of vector elements that are physically adjacent to each other or a plurality of scalar identification information indicating individually a plurality of scalar registers as a transfer destination or a transfer source Of the vector register having a storage area allocated to the vector register under the control, a set of vector elements having one end indicated by the vector identification information, and a scalar register of the vector register. Among them, the vector computer is provided with a block transfer means for transferring in a vector element unit with respect to each scalar register indicated by the plurality of scalar identification information. 5. A control means constituting a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the storage area allocated to the vector register. And a vector identification information indicating the attached vector element, and a scalar identification information indicating a scalar register which is a transfer destination or a transfer source as an operand, including means for performing control relating to execution of a transfer instruction, and under the control A vector element having a storage area allocated to the vector register, for a higher order or a lower order of the vector element indicated by the vector identification information, a scalar register indicated by the scalar identification information in the scalar register. A vector computer characterized by comprising a transfer means for transferring. 6. A control means forming a control mechanism for executing a vector operation instruction and a scalar operation instruction based on a predetermined control logic, and a plurality of vectors individually holding vector data composed of a plurality of vector elements. A register, a vector operation means for performing vector operation on the vector data held in the plurality of vector registers under the control logic, logically or physically adjacent to each other, and into a single vector element. In a vector computer including a plurality of scalar registers that individually hold corresponding data, and a scalar operation unit that performs a scalar operation on the data held in the plurality of scalar registers under the control logic, in the control unit, Is the source or destination vector register and the storage area allocated to the vector register. And a vector identification information indicating the attached vector element, and a scalar identification information indicating a scalar register which is a transfer destination or a transfer source as an operand, including means for performing control relating to execution of a transfer instruction, and under the control A vector element indicated by the vector identification information among vector elements having a storage area allocated to the vector register for the higher order or the lower order of the scalar register indicated by the scalar identification information among the scalar registers, A vector computer characterized by comprising a transfer means for transferring. 7. The vector computer according to any one of claims 1 to 3, wherein the control means sets the number of vector elements, the vector identification information, and the scalar identification information to preset values and individual values. Correlate to
A vector computer including means for setting the number of vector elements to be block-transferred to "1" based on the result of the correlation. 8. The vector computer according to any one of claims 1 to 3, wherein the control means sets the number of vector elements, vector identification information, and scalar identification information to preset values and individual values. Correlate to
A vector computer comprising means for setting the direction of block transfer from a scalar register to a vector register based on the result of the correlation, and fixedly setting a transfer source scalar register for each vector element.