JPH0887400A - Multiplier, adder and subtracter - Google Patents

Abstract

PURPOSE: To constitute the multiplier, adder and subtracter in a compact device and speed up the operation of multiplication, addition, and subtraction by performing addition of a 3rd operand C simultaneously with partial multiplication of 1st and 2nd operands A and B. CONSTITUTION: The 1st and 2nd operands A and B are inputted to a multiplication array 301 and multiplied. When a secondary Booth's algorithm is used as multiplication algorithm, 12 partial products are added by a Wallace tree which is composed of full-adders and obtains the sum of partial products of the same weight (same digit). The 3rd operand C is also inputted to the multiplication array 301 and the values of the respective digits of the operand C are added directly to the partial products of the same weight by the adders of a Wallace tree corresponding to the respective digits of the operand C. Consequently, the multiplication array 301 calculates an arithmetic operation result A×B+C of multiplication, addition, and subtraction in carry save form. A final adder converts the arithmetic operation result A×B+C of multiplication, addition, and subtraction, found in the carry save form into a binary number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a multiplier / subtractor for performing A * B + C calculation. Another invention relates to an improvement in a barrel shifter that shifts data by a specified amount in an arithmetic unit or the like.

[0002]

[Prior art]

(Multiplier / Adder / Subtractor) In scientific and technological calculations, computer graphics, signal processing, etc., it is necessary to process enormous amounts of operations at high speed. Matrix calculations are frequently performed in such applications. Many of the operations can be reduced to multiplicative addition / subtraction that performs A × B + C. Therefore, a high-speed multiplying / subtracting arithmetic unit is required. In particular, a digital signal processor (DSP), which requires high-speed arithmetic performance, is equipped with a multiplication / subtraction arithmetic unit composed of hardware.

FIG. 8 is a block diagram showing an example of a conventional multiplication / subtraction arithmetic unit. In the figure, the binary multiplicand A
The multiplier that finds the product of the multiplier B and the multiplier B is, for example, a multiplication array 101 that executes multiplication by a known Booth algorithm, and a sum output group Fss of the multiplication array 101.
And a final adder 102 for arranging the carry output group Fcc (multiplication intermediate value) in the form of a binary number. The output P (= (A
× B)) and the binary addition value (or subtraction value) C to be added (or subtracted) are added (or subtracted) by the adder 103 to obtain (A × B) + C. There is.

FIG. 9 shows the configuration of a multiplication array 101 for performing multiplication by Booth's algorithm. It consists of a booth recorder 101a for recoding (re-encoding) a multiplicand A, a multiplicand A and a multiplier B. A partial product generation circuit 101b that generates a partial product and a carry save adder group for partial product addition (for example, Wallace tree) 101c that cumulatively adds the weighted partial products are configured.

The partial product generation circuit 101b generates a partial product according to the following equation, for example, when executing the primary Booth algorithm.

[0006] Here, the multiplicand A is an n-bit binary number (= a _n ,
_{a n-1, ..., a} 1, a 0), the multiplier B is an n-bit binary number _{(= b n, b n-} 1, ..., a b _1, b _0). i means the i-th multiplication step.

Further, in the case of the secondary Booth's algorithm, a partial product represented by the following equation is generated.

[0008] P = A / B In the secondary Booth's algorithm, n is reduced to n / 2 and the addition amount of partial products is reduced. A cubic Booth algorithm is also known in which the number of partial product additions is n / 3. Note that Booth's algorithm is well known, and other algorithms can be used as an algorithm for multiplication to generate a partial product.
The Booth algorithm is not detailed.

FIG. 10 illustrates the partial product generation circuit 101b and the partial product addition carry save adder group 101c. The partial product generation circuit 101b outputs, for example,
An example is shown in which partial products of the 12-bit multiplicand A and multiplier B are weighted and arranged as numerical values. In the figure, a black circle indicates a partial product. The array of partial products is a 12-bit multiplicand A, a 12-bit multiplier B,
According to the above, there are 24 bits in the row direction and 12 bits in the column direction, and the same column indicates the same digit. Note that the partial products b0 a0, b0 a1, ..., B11 a11 shown in the figure are added for convenience of explanation, and are not related to the subscripts added to the values of the above expressions. I want to.

The carry save adder group 101c cumulatively adds the partial products of the respective columns while carrying the carried carry to the next stage and saving the carry. A carry save adder (CPA) arranged in a so-called tree structure, for example, a binary tree or a wallace tree is used for this cumulative addition.

FIG. 11 shows the carry-save adder group 101c for partial product addition, which corresponds to one column (b0) indicated by the dotted line in FIG.
a11, b1 a10, ..., B11a0) is shown, which is a group of adders having a Wallace tree structure and which is responsible for addition. The carry save adder 4w forming the tree corresponds to four inputs and one carry input, and five 1
It has one sum output and two carry outputs. 1st stage, 3
Partial products b0 a11, b1 a11, ..., B11 a0 of the same digit (same weight) are input to the respective inputs of the carry save adder 4w. The sum of each partial product is the second and third stages of the tree structure.
The signal propagates through a plurality of adders 4w of stages and is output to a carry propagation adder (CPA: carry-propagate adder) not shown.
In the figure, the carry input from the Wallace tree (not shown) of the one lower digit to each adder 4w and the carry output to the Wallace tree (not shown) of the digit one above are shown by triangular arrows. It is shown. The Wallace trees of other digits (columns) also include adders according to the number of inputs of partial products, and are similarly configured by the array.

FIG. 12 shows a configuration example of the carry save adder 4w. The adder 4w includes a first logic circuit group for obtaining a carry output Cout from four inputs d0 to d3,
A second logic circuit group which obtains the sum S from the sum of the four inputs d0 to d3 and the carry input from the lower digit, the carry resulting from the four inputs d0 to d3 and the four inputs d0 to d.
And a third logic circuit group for obtaining a carry output CC from the carry input Cin from the lower digit.

In this way, the partial product generation circuit 101b
The plurality of partial products for the multiplicand A and the multiplier B generated by are subjected to addition processing by the carry save adder group for partial product addition (for example, Wallace tree) 101c so that the carry propagates to the upper digit. It Sum output of each digit,
The carry output is given from the multiplication array 101 to the final adder 102 constituted by the carry propagation adder, and the final addition is carried out so that the carry propagates to the upper digit, and the product P is arranged in the form of a binary number. . Then, the product P and the number of additions C are added by the adder 103, and the calculation result of A × B + C is obtained.

FIG. 13 shows an example of the configuration of another multiplier. In FIG. 13, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and the description of those parts will be omitted. In this example, FIG.
The multiplier / adder shown in (1) is configured by connecting the multiplier and the adder, while the multiplier and the adder are connected via the bus or the bypass line, so that the independent multiplier and the adder can be connected. The configuration is used to perform multiplication, addition, and subtraction operations. With this configuration, addition and multiplication can be performed independently in addition to multiplication, addition and subtraction, so that there is an advantage that the degree of freedom in calculation is large. For this reason,
Most general-purpose microprocessors including many general-purpose DSPs are equipped with an arithmetic unit having such a configuration.

A problem with the above-described multiplier adder / subtractor of the type in which the multiplier and the adder are connected in series is that the addition is performed after the end of the multiplication, so that the operation is performed by an independent multiplier and the adder respectively. , There is no big difference in the execution time of the calculation.

FIG. 14 shows an example of a multiplier / adder / subtractor (floating point type) in which such a problem is improved. According to this configuration, the multiplication, addition, and subtraction operations can be executed in a time equivalent to the execution time required for multiplication or addition, which will be described below.

In FIG. 14, the multiplication array 201 multiplies the supplied mantissa part Fa of the first operand A and the supplied mantissa part Fb of the second operand B. Multiplication array 2
As described above, 01 is composed of a group of carry save adders (CSA) connected in a tree shape, and a partial product is obtained in a carry save form (sum component Fss, carry component Fcc). This example is shown in FIG. The digit alignment shifter 202 is a barrel shifter for performing digit alignment of the mantissa part Fc of the third operand C to be added. The final adder 903 has a multi-bit sum component Fss,
A carry propagation adder for carrying carry addition of three inputs of carry component Fcc and mantissa Fc of operand C. The product Fa × Fb of the mantissa parts of the first and second operands obtained by the carry save form (sum component Fss, carry component Fcc) is converted into a binary number, and the mantissa part Fc of the third operand is converted. Add. The leading 1 detection circuit 204 determines the number of shifts required for normalization.
The normalization shifter 205 is a barrel shifter for normalizing the calculation result Fbb, and the rounding circuit 906 rounds the calculation result Fbb.

Next, the operation processing operation in this multiplier / subtractor will be described. First, the mantissa parts Fa and Fb of the first and second operands A and B are input to the multiplication array 201 and multiplication is performed. The product is obtained by the carry save form (sum component Fss, carry component Fcc).
The mantissa part Fc of the operand C is input to the digit alignment shifter, and digit alignment is performed in parallel with the multiplication process. Digit alignment is performed by shifting by | Ea + Eb-Ec |. Here, Ea, Eb, Ec are the exponent parts of the operands A, B, C. The product (sum component Fss, carry component Fcc) and operand Fc are added by a 3-input adder to obtain a binary addition / subtraction result Fbb. The multiplication / subtraction result Fbb is normalized and further rounded.

In this way, the final addition (Fss + Fcc) for performing multiplication in the multiplication array 201 and digit shift in the digit shifter 202 in parallel to obtain a product.
By executing the addition of the and the operand Fc at once using the 3-input adder 203, the multiplication / subtraction operation can be executed within the same execution time as the addition and the multiplication.

However, there is another problem in the multiplier / adder / subtractor having the above configuration. That is, the digit shifter 202 that performs digit alignment, the three-input adder 203 that adds the product sum component Fss, the carry component Fcc, and the operand Fc, and the preceding 1 detection circuit 204 that calculates the shift number for the normalization shift. , About 160 bits (IEEE75
4 standard floating point double precision) is required. For this reason, the amount of hardware is increased, and the increase in execution speed is also hindered. (Barrel shifter) By the way, in such an arithmetic unit, a barrel shifter is used to shift data by a necessary amount (digit number).
In the barrel shifter, the shift amount is generally designated by a power of two. Further, in order to minimize the wiring area, the structure is as shown in FIG.

That is, when the number of bits in the data input is 2 ⁿ , the barrel shifter is realized by using n stages of 2-input 1-output selectors as shown in FIG.
When this shifter operates, the transistor pair corresponding to the signal passing path is turned on, so that power is consumed in n × 2 ⁿ pairs of transistors. Also, since the operating speed of the barrel shifter is largely controlled by the number of transistor pairs on the path through which the signal passes,
In the conventional configuration, the operation speed is determined by the delay time due to the n-stage transistor pair.

Generally, a computer system is required to have a rightward shift function and a leftward shift function for a so-called data bit shift operation. Therefore, as shown in FIG. 28, a barrel shifter to the left and a barrel shifter to the right are separately provided, and the left and right shift directions of data are selected by the selector.

However, in this structure, the amount of wiring is remarkably increased. Therefore, as shown in FIG.
By adding a bit order inversion circuit that reverses the bit order before and after the barrel shifter that only shifts to the left or right in a single direction, bit shifting in both left and right directions is realized while suppressing an increase in the amount of hardware. Is proposed. In this case, the decrease of the operation speed due to the bit order inversion circuit becomes a big problem.

Therefore, it is difficult to meet all the needs of a large-scale integrated circuit such as high speed, low power consumption, and area saving, and the circuit is properly used according to the place of use.

[0025]

[Problems to be Solved by the Invention]

(Multiplication / subtraction device) As described above, in the conventional multiplication / subtraction system, it takes a long time to execute an operation. Also, in order to execute the multiplication / subtraction operation at high speed, an adder with a very large bit width
A lot of hardware such as a detector is required, and this point hinders the speedup.

Therefore, it is an object of the present invention to provide a multiplication / addition / subtraction arithmetic unit which can realize a high-speed multiplication / subtraction arithmetic operation with a relatively small hardware configuration. (Barrel Shifter) In the above-described conventional barrel shifter technology, the requirements that are generally contradictory to each other, such as high speed, low power consumption, and area saving, have to be compromised to some extent. That is, in the barrel shifter in the conventional configuration, unlike the circuit like other adders,
Since almost all of the selector circuits constituting the shifter operate, power consumption tends to increase. The operating speed is also required to be high. Furthermore,
In the barrel shifter, the wiring area occupies a large area, which can be a decisive factor for the circuit area of the arithmetic circuit in a microprocessor or the like. In addition, in order to make the above-mentioned multiplier / subtractor compact and realize high-speed operation, it is required that the barrel shifter used therein also has a compact structure and high-speed operation.

Therefore, another object of the present invention is to satisfy the three requirements of the barrel shifter, which are contradictory area saving, high speed, and low power consumption, at a high level.

[0028]

[Means for Solving the Problems]

(Multiply-adder / subtractor) In order to achieve the above object, the fixed-point multiplier-adder / subtractor of the present invention comprises a multiplication value obtained by multiplying input first and second operands, and an input third operand. A fixed-point multiplication-adder / subtractor that performs addition or subtraction, and a partial product generation circuit that generates a plurality of partial products corresponding to the first and second operands according to a predetermined multiplication algorithm, and addition of the plurality of partial products When,
A multiplication array that performs addition or subtraction of the third operand by a plurality of adder groups arranged in a tree structure, subtracts the output, and outputs a plurality of weighted multiplication intermediate values;
A carry propagation type adder for adding the plurality of intermediate values for multiplication to obtain a multiplication / subtraction value.

Further, in order to achieve the above object, the floating-point multiplying / subtracting device of the present invention adds the multiplication value obtained by multiplying the input first and second operands with the input third operand. Alternatively, in a multiplicative adder / subtractor of a floating-point operation that performs subtraction, a partial product generation circuit that generates a plurality of partial products corresponding to respective values of the mantissa part of each of the first and second operands according to a predetermined multiplication algorithm; The value of the exponent part of the third operand is equal to the value of the exponent part of the product of the first and second operands.
A shift circuit that performs digit alignment of the mantissa value of the operand, an addition of the plurality of partial products, and digit alignment of the first and second digit values of the mantissa value of the third operand.
The addition or subtraction of the value of each digit of the lower digit in the value represented by the number of digits assigned to the product of the mantissa part of the operand of is performed by a group of adders arranged in a tree structure. A multiplying array for outputting a plurality of weighted intermediate intermediate values, a carry propagation adder for adding the plurality of intermediate intermediate values to obtain a multiplying / subtracting value of a lower digit, and the third digit aligned Of the mantissa value of the operand of
Add the value of the upper digit exceeding the value represented by the number of digits assigned to the operation of the mantissa product of the first and second operands and the carry output of the carry propagation adder. And an increment adder for obtaining an upper digit output value, and means for bit-combining the upper digit output value and the lower digit multiplication, addition, and subtraction values to obtain a final multiplication, addition, and subtraction value.

As a group of adders constituting the above-mentioned multiplication array, a carry-save adder for dividing a sum into a sum component and a carry component to obtain it, an SD adder for adding using a redundant number, a PD adder, and a full addition It is possible to use a container or the like. (Barrel shifter) To achieve the above object, the barrel shifter of the present invention has at least a data input, a data output, and a control input, and a barrel shifter that shifts the input data by the number of bits designated by the control input and outputs the shifted data, From the supplied input data consisting of 1 (integer) bits, 1 signal shift means for outputting 4 bit signals and 1 for selecting 1 from the 4 bit signals output by each signal shift means. Selecting means and decoding means for decoding the supplied control input to give a control signal for instructing each selecting means a bit signal to be selected. The th signal shift means is 0 bit, n (integer) bit, m (integer) bit, m + n for the i th bit signal of the input data. Tsu DOO is adapted to output four-bit signal at a position obtained by shifting the bit position,
It is characterized by the following. The signal shift means and the select means are cascade-connected by a required number of stages according to the number of bits of input data and the range of the number of shift bits to be handled. It should be noted that normally n and m use powers of two.

Further, the bidirectional shift barrel shifter of the present invention is provided in a barrel shifter which has at least a data input, a data output, and a control input, and shifts and outputs the input data by the number of bits designated by the control input. From the input data consisting of 1 (integer) bits, 1 first signal shift / bit order inversion means for outputting four bit signals and 4 output by each of the first signal shift / bit order inversion means. From the l first selecting means for selecting one from one bit signal and the l outputs inputted from the l first selecting means,
L signal shift means for outputting four bit signals,
From the l second select means for selecting one out of the four bit signals output by each signal shift means and the l output input from the l second select means,
L second signal shifts / outputting 4 bit signals /
Bit order inversion means, l third select means for selecting one from the four bit signals output by each of the second signal shift / bit order inversion means, and decoding of the supplied control input And a control signal generation means for giving a control signal for instructing a bit signal to be selected to each selection means, and the i-th first signal shift / bit order inversion means of the above l first signal shift / bit order inversion means. The signal shift / bit order inversion means has a relationship of no change, bit order inversion, o (integer) bit shift, bit order inversion and o (integer) bit shift with respect to the i-th bit signal of the input data. Four bit signals are output, and the i-th signal shift means among the l signal shift means does not shift the input i-th bit signal, p (integer) + q (integer) bits, p (Form ) Bits, q (integer) bits, and four bit signals at the bit position shifted positions are output, and the i-th second signal shift / of the l second signal shift / bit sequence inversion means is output. The bit order inversion means has four bits in a relationship of no change, bit order inversion, r (integer) bit shift, r (integer) bit shift and bit order inversion with respect to the i-th bit signal of the input data. It is characterized by outputting a signal. The signal shift means and the select means can be connected in cascade for the required number of stages.

[0032]

[Action]

(Multiply Adder / Subtractor) In the present invention, in the present invention, first, the mantissa parts Fa and Fb of the operands A and B are input to the multiplication array and multiplication is performed. The multiplication array is composed of carry save adders connected in a tree shape, and the product is obtained by the carry save form. The mantissa part Fc of the operand C is input to the digit adjustment shifter, and Fa,
Digit alignment is performed in parallel with the multiplication process of Fb. Digit alignment is performed by shifting by | Ea + Eb-Ec |. Here, Ea, Eb, Ec are the exponent parts of the operands A, B, C. Digit alignment shift result F
The c shift is divided into a portion Fc low having the same digit as each digit of (Fa × Fb) and a higher portion Fc high. Fc low is input to the multiplication array and added together with the partial product, and the product is obtained in the carry save form (sum component Fss, carry component Fcc). The sum component Fss and the carry component Fcc are added by the final adder to obtain the lower side Fbb low of the multiplication / subtraction operation result. Further, Fc high is incremented by the carry value of the final addition, and the higher-order side Fbb high of the multiplication / subtraction calculation result is obtained.
Is required. Further, the increment result is input to the leading 1 detection circuit, and the number of shift steps required for the normalization shift is calculated. Based on this result, the multiplication / subtraction operation result F
bb (bit combination of Fbb high and Fbb low) is normalized and rounded. (Barrel shifter) When the bit length of the input data is L, in the first configuration of the barrel shifter of the present invention, a number L corresponding to each bit of the input data is obtained by cascade-connecting the required number of signal shift means and select means. However, the control signal from the control signal generating means for operating the selecting means from the given number of shift bits is supplied to the selecting means at each bit position arranged in parallel. At this time, since the selecting means arranged in parallel are operated by the same control signal, only one control signal generating means is required for each selecting means in the vertical direction. By these means, the bit position of the input data is sequentially changed in each signal shift means + select means, and finally the result obtained by shifting the desired number of bits is obtained. Here, considering the case where L = 2 ⁿ (n is an integer), in the configuration using the conventional 2-input 1-output select means, there are n stages in total from the input of a signal to the output. It will pass the selection means,
With the configuration according to the present invention, it suffices to pass through n / 2 stages (n / 2 + 1 stages when n is an odd number) of the selection means, so that speeding up and reduction in power consumption can be achieved. Furthermore, since the normal signal shift means and the select means are vertically stacked with respect to the bit string of the input data, the conventional 2-input 1-output selector is used in the wiring connecting these means. In contrast, two sets are required, whereas the configuration according to the present invention requires only one set. Moreover, since the switching probability of the transistor can be reduced by 25% on average, the power consumption can be further reduced. Further, the number of elements used in the selecting means is increased when the configuration other than 4 inputs and 1 output such as 8 inputs and 1 output is used as compared with the case where the selecting means having 2 inputs and 1 output is used. On the other hand, when the 4-input 1-output select means is used, the same result is obtained, and the increase in hardware can be minimized.

The second aspect of the barrel shifter of the present invention
In the above configuration, a signal shift / bit order inversion means and a select means that are connected in cascade so that a large shift bit number can be shifted after performing bit order inversion on the side closer to the data input is the bit length of the input data. Only L are provided in parallel, and subsequently, the signal shift means + select means in the first configuration are cascade-connected by a required number of stages, and finally, a bit order inversion is performed after a large shift bit number shift. Connect signal shift / bit order inversion means as possible. At this time, the control signal generation means generates a control signal in accordance with two different amounts of shift bits, and also generates a control signal in accordance with the shift of a certain shift bit amount and the presence / absence of bit order inversion. What is produced is used for the first and last selector stages of the shift in this configuration. First, when bit order inversion is not performed, only the bit positions are shifted in the first and last selector stages, and the bit shift in a certain direction is performed as a whole. Then, when bit order inversion is performed in the first and last stages,
The input data is first bit-reversed and then subjected to a bit shift operation by a predetermined amount, and finally the bit order is re-inverted once again, whereby a shift operation in the reverse direction is realized. At this time, for the same reason as in the first configuration, the number of selector stages through which the signal passes is significantly reduced compared to the configuration in which the bit inversion mechanism is provided before and after the shifter using the conventional 2-input 1-output selector. To do.
Therefore, speeding up of the shift operation and low power consumption can be achieved. Furthermore, the number of bits of input data is 2 ⁿ (n
Is an integer), 2 ⁿ wirings are normally arranged in parallel to the bit string of the input data in order to perform bit order inversion, and an increase in the wiring area causes an increase in the shifter circuit area. in the arrangement according to the present invention, the wiring of the 2 ⁿ duty, 2 ^n-1 and 2 it is possible to share as a wiring for performing the ^n-2 bit shifting, the area of the wiring region 2 ^n-1 and 2 It can be reduced by ^n-2 lines. Also,
At this time, the maximum length of the wiring laid parallel to the input data bit string matches the horizontal length of the input data bit string, but in the conventional configuration, the bit order is reversed before the maximum bit length is shifted. In the worst case, the wiring length through which the signal must pass is the horizontal length of the input data bit string plus the length by which the bit position moves due to the shift. Can reduce the load capacity. Since the wiring for reversing the bit order is provided, it is possible to perform the operation of changing the bit order before and after the shift or simply reversing the bit order.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the multiplier / subtractor of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a fixed-point multiplication / addition device according to a first embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG.

The fixed point multiplication adder / subtractor of this embodiment uses an adder group of a tree structure for cumulatively adding the weighted partial products of the operands A and B in the multiplication array 301. Add or subtract C,
The addition result is arranged in the form of a binary number by the final adder 102 which is a carry propagation adder.

FIG. 2 shows an example of the structure of the multiplication array 301. First, as in the conventional example shown in FIG. 9, two supplied operands A and B are multiplied. The multiplication array 301 uses, for example, a quadratic Booth algorithm, and has a quadratic Booth recorder 301a, a partial product generation circuit 301b, and a carry save adder group for partial product addition (for example, Wallace tree) 301c. ,,. Two
When performing 4-bit fixed point arithmetic, 12 partial products are generated by the second order Booth's algorithm,
It is added by a carry save adder group having a tree structure. The product is
It is calculated by the carry save form (sum component Fss and carry component Fcc).

FIG. 3 illustrates the partial product generation circuit 301b and the carry save adder group 301c for partial product addition. In FIG. 3, parts corresponding to those in FIG. 10 are designated by the same reference numerals. This drawing conceptually shows an example in which partial products of, for example, a 12-bit multiplicand A and a multiplier B output from the partial product generation circuit 101b are weighted as numerical values and arranged. In the figure, a black circle indicates a partial product. The array of the partial products is 24 bits in the row direction and 12 bits in the column direction according to the multiplicand A of 12 bits and the multiplier B of 12 bits, and the same column indicates the same digit. The partial products b0 a0, b0 a1,
..., b11a11 are added for convenience of explanation. In the array of this partial product, the operand C (= c11, c10,
,, c1, c0) are aligned and arranged. In the case of subtraction, the complement of operand C is added (the same applies hereinafter).

The carry save adder group 301c cumulatively adds the partial products of the respective columns while carrying the carried carry to the next stage and saving the carry. For this cumulative addition, a carry save adder (CPA) arranged in a so-called tree structure is used.
), For example, a binary tree or a Wallace tree is used.

FIG. 4 shows the carry-save adder group 301c for partial product addition, which corresponds to one column (b0 a1) indicated by the dotted line in FIG.
, B1 a10, ..., b11 a0)
The adder group of a Wallace tree structure is shown. The carry save adder 4w forming the tree is the same as that shown in FIG. 12, and one sum output corresponding to five inputs of four inputs and one carry input, It has two carry outputs. The carry save adder 3w is a full adder having one sum output and one carry output corresponding to the three inputs. For each input of the three carry save adders 4w in the first stage, partial products b of the same digit (same weight)
0 a11, b1 a11, ..., B11 a0 are added. The c11 of the operand C or its complement is input to the adder 3w in the second stage. The sum of each partial product is the second of the tree structure.
Stage and third stage multiple adders 4w propagate to operand C
Is added to the final adder 102, which is a carry propagation adder (CPA) (not shown).
In the figure, the carry input to the adders 4w and 3w from the Wallace tree (not shown) of the next lower digit and the carry output to the Wallace tree (not shown) of the next upper digit are triangular. It is indicated by an arrow. Wallas of other digits
The tree is also provided with an adder of a number corresponding to the number of inputs of the partial product and an adder for adding the operand C to the partial product, and is similarly configured by the array portion (number of digits).

As described above, the most important and characteristic point of the multiplication array 301 is that it is possible to input another value Ci from the outside as shown in FIG. It is possible to perform addition (or subtraction by addition of complement of c) at the same time as addition of partial products in the array. In FIG. 4, the full adder is inserted into a tree-structured adder group (Walrus tree) to realize external input. It should be noted that inserting the full adder has no effect on the critical path of the present multiplying array.

The final adder 102 is a carry save
A carry propagation adder that converts the array output output in the form (carry component Fcc, sum component Fss) into a binary number, for example, outputs 48 bits corresponding to the inputs of 24-bit operands A and B is there. As a group of adders constituting the multiplication array, in addition to the carry-save adder that finds the above sum by dividing it into a sum component and a carry component, an SD adder, a PD adder that adds using a redundant number, It is possible to use a full adder or the like.

Next, the operation of the main adder / subtractor will be described. First, the first and second operands A and B are the multiplication array 3
01 is input and multiplication is performed. When the secondary Booth's algorithm is used as the multiplication algorithm, 12 partial products are added by the Wallace tree configured by the full adder 4w to obtain the sum of partial products of the same weight (same digit). . The Wallace tree is provided for each digit, and the carry portion in the tree of a certain digit is added sequentially in the tree of the next stage. On the other hand, the third operand C is also input to the multiplication array 301, and the value of each digit of the operand C is directly added to the partial product of the same weight by the adder of the Wallace tree corresponding to each digit of the operand C. As a result, the multiplication / subtraction operation result A × B + C is calculated in the carry save form from the multiplication array. The final adder converts the multiplication / subtraction operation result A × B + C obtained by the carry save form into a binary number.

Thus, the addition of the third operand C is performed at the same time as the addition of the partial products for obtaining (A × B) in the multiplication array 301, so that the product (A × B) of the first and second operands is obtained. Adder 10 for adding the third operand C
3, 203 can be omitted. As a result, it is possible to realize a multiplier / adder / subtractor arithmetic unit that is faster and saves hardware.

Next, the second embodiment will be described. By using the above-mentioned fixed-point multiplication / subtraction device as the mantissa arithmetic unit of the floating-point multiplication / subtraction device, it is possible to obtain a floating-point multiplication / subtraction device that also has high speed and reduced hardware. FIG. 5 is a block diagram showing the mantissa arithmetic unit of the floating point adder / subtractor showing such an example.

In the figure, the multiplier / adder is a multiplication array 401, a final adder 402, a digit alignment shifter 403, an incrementer (incremental adder) 404, a leading 1 detection circuit 40.
5, a normalization shifter 406, and a rounding circuit 407. In the case of a floating-point multiplication adder / subtractor that performs the operation of A × B + C, the value of C may be larger than the value of the product (A × B). Therefore, in this configuration, the binary value representing the product (Fa × Fb) of the mantissa parts of the operands A and B and the binary value representing the mantissa part Fc of the operand C have a common digit width (lower bit Fc low). For the portion, addition processing (Fa × Fb + Fc low) is performed using the multiplication array 401. For the part of the digit width (higher-order bit Fc high) where Fc exceeds the digit width of the binary value representing (Fa × Fb), it is Fc high as it is.
Is output. However, addition processing (Fa x Fb + Fc low
), The incrementer 40
Add "1" to Fc high by 4. Then, in the normalization shifter, (Fa × Fb + Fc low) and Fc high or Fc high + incremented by carry
By inputting 1 and, the binary value display of Fa × Fb + Fc with aligned digits is obtained, and corresponding to the detection result of the preceding 1 which determines the leading bit position (digit) which becomes “1” in Fc high. Normalize. Then, the rounding circuit 407 performs a prescribed rounding process.

Next, each part will be described. The multiplication array 401 receives two normalized operands A
And the mantissa parts Fa and Fb of B are multiplied. The multiplication array 401 has the same configuration as the multiplication array 301 shown in FIG. For example, a secondary booth algorithm is used, and a secondary booth recorder, a partial product generation circuit, and a carry save adder group for partial product addition (for example, Wallace Tree) as shown in FIG. , Composed by. When performing a double-precision operation, 27 partial products are generated, each of these partial products is added by the Wallace tree, and the product is carried by the carry save form (carry component Fcc, sum component Fss). It is calculated.

FIG. 6 is a block diagram of a Wallace tree using the carry save adder 4w in the second embodiment. Four
It is composed of a carry save adder 4w arranged in stages and a carry save adder 3w inserted therebetween. As described above, the carry save adder 4w corresponds to four inputs, one carry input, and five inputs.
It has one sum output and two carry outputs. The carry save adder 3w has one sum output and one carry output corresponding to the three inputs.

The most important and characteristic point of this multiplication array 401 is that other values can be input from the outside like the Wallace tree shown in FIG. , Wallace Tree) can be added at the same time as the addition of partial products in an array of adders. In Figure 6, the Wallace tree has 3
Corresponding to one input, a full adder 3w having one sum output and one carry output was inserted to enable input from the outside. Even if the full adder 3w is inserted in the Wallace tree,
It has no effect on the critical path for the computation time of the multiplication array 301.

The digit alignment shifter 403 performs digit alignment between the normalized mantissa part Fc of the third operand C and the product (Fa × Fb) obtained in the multiplication array 401, for example, of 106 bits. It is a barrel shifter. In the digit alignment shifter 403, the value obtained from the exponent part of the three operands as the number of shift steps | Ea + Eb−E
c | is input, and the mantissa part F of the operand C is input correspondingly.
c is shifted. As mentioned above, Ea, Eb, Ec
Are the exponents of operands A, B, and C, respectively.

Digit adjustment shift result of mantissa Fc Fc shif
t is divided into a portion Fc low having the same digit as each digit of the product (Fa × Fb) and a higher portion Fc high. Fc low is input to the multiplication array 401, and Fc hi
gh is input to the incrementer 404.

The final adder 402 is a carry save
It is a 106-bit carry propagation adder that converts the array output (sum component Fss, carry component Fcc) output in the form into a binary number Fbb low. Fbb low is input to the normalization shifter 106. The carry cc is also input to the incrementer 404.

The incrementer 404 is a 53b-bit incrementer for calculating the upper part Fbb high of the multiplication / subtraction operation result. In incrementer 404, Fc
high + 1 is obtained, and either Fc high + 1 or Fc high is selected according to the carry CC value of the final adder 402,
Output as Fbb high. In the leading 1 detection circuit 405,
Fbb high is input and the position of the leading "1" is detected.
The output value Snorm is input to the normalization shifter 406 as the number of normalization shift steps.

The normalization shifter 406 is a barrel shifter for normalizing the multiplication / subtraction operation result Fbb (bit combination of Fbb high and Fbb low). 53 bits wide leading 1
The output Fn shifted to the left by the output Snorm of the detection circuit 405 is obtained. The rounding circuit 407 is, for example, IEEE 7
According to the H.54 standard, the output Fn is rounded to obtain the final calculation result Fmac.

Next, a more detailed operation of the (floating point) multiplier adder / subtractor in the second embodiment will be described with reference to FIGS. FIG. 7 shows the flow of data signals in the multiplier / subtractor.

First, the normalized mantissa part Fa of the first operand A and the normalized mantissa part Fb of the second operand B are normalized.
Is input to the multiplication array 401 and multiplication is performed. Since the second-order Booth's algorithm is used in this embodiment, 27 partial products are added by the Wallace tree (FIG. 6) constituted by four stages of 4-2 compactors (adders 4w). . On the other hand, the normalized mantissa part Fc of the third operand C is input to the digit alignment shifter 403, and digit alignment is performed in parallel with the multiplication processing of Fa and Fb in the multiplication array 401. The digit alignment is performed by shifting by | Ea + Eb−Ec | based on Ea, Eb, and Ec which are exponents of the operands A, B, and C, respectively. The digit alignment shift result Fc shift is a portion Fc lo that has the same digit as each digit of the product (Fa × Fb).
w and the upper part Fc hi that exceeds the digit width of the product (Fa × F)
split into gh and.

Fc low is input to the multiplication array 401,
The partial product is added in the Wallace tree, and the lower part of the multiplication / subtraction operation result is obtained in the carry save form (sum component Fss, carry component Fcc). These sum component Fss and carry component Fcc are added to the final adder 4
02 is added to calculate the lower part Fbb low of the operation result of binary addition / subtraction. At this time, when a carry-over occurs, the carry output CC of the final adder 402 is input to the incrementer 404 so that the bit width of Fc high can be covered by the carry-over.

On the other hand, the upper part Fc high of the digit alignment shift result Fc shift is input to the incrementer 404.
Fc high + 1 is generated from Fc high. In the incrementer 404, Fc high + 1 is selected when the carry CC value of the final adder 402 is "1", and Fc high is selected when the carry CC value is "0". The selected Fc high + 1 or Fc high is output as the upper part Fbbhigh of the multiplication / subtraction operation result. Also,
The output Fbb high of the incrementer 404 is input to the preceding 1 detection circuit 405, and the number of shift steps Snorm required for the normalized shift is calculated. Multiplication addition / subtraction operation result Fbb
high and Fbb low are bit-combined and normalized shifter 1
At 06, the number of shift steps is shifted by Snorm and normalized. The normalized normalization result Fn is rounded by the rounding circuit 107 for lower bits (sticky) less than the number of significant digits according to, for example, IEEE-754, and a multiplication / subtraction operation result Fmac is obtained.

As described above, by performing the addition of the third operand C by the multiplication array 401, conventionally, a digit shifter 202 and an adder 203, which constitute a multiplication / subtraction device, which required a bit width of about 160 bits. , Leading one detector 204
It is possible to obtain a configuration in which the bit width of the arithmetic module etc. is reduced. As a result, it is possible to realize a higher calculation speed for multiplication, addition and subtraction. (Barrel Shifter) Next, the improvement of the barrel shifter used for shifting data in an arithmetic unit such as a multiplier / subtractor will be described. A first embodiment will be described with reference to FIG. In this figure, the input / output data length is 16 bits, and the shift amount is a 4-bit binary value b8 b4 b2 b.
The functional block diagram of the unidirectional barrel shifter specified in 1 is shown. In this example, by selecting whether or not the shift of 8, 4, 2, 1 bits is performed, the shift by the designated shift amount is realized. 8-bit and 4-bit shifts are performed by a pair of signal shift means and 4-input 1-output select means. Similarly, 2-bit and 1-bit shifts are realized by a pair of shift stages and 4-input 1-output select means.

FIG. 17 is a 4-input 1-output selecting means for shifting 8 bits + 4 bits in the first stage shown in FIG. 16 and a selector control signal generating means for generating a control signal for properly operating the selecting means. The example of composition of is shown. In order to form the 16-bit length shifter shown in FIG. 16, another mechanism corresponding to 2 bits + 1 bit shift is connected in cascade. Here, the 2-bit shift amount instruction signal input to the selector control signal generation means is decoded to make one set of p-channel and n-channel transistors conductive among the transistors of the 4-input 1-output transmission gate type selector. Thus, the appropriate one of the signals supplied by the signal shifting means is transmitted to the next stage or output. About this shifter, 1 by the shift amount control input
Consider the case where a 3-bit shift is instructed. When the shift amount of 13 bits is expressed by a binary value, it becomes (1101), so it is sufficient to perform 8-bit, 4-bit and 1-bit shifts. Considering this in FIG. 16, first, in the first 8-bit + 4-bit shift stage, a total of 12 bits are shifted, and in the subsequent 2-bit + 1-bit shift stage, 1-bit shift is performed. Therefore, a 13-bit shift is realized in both stages. For example, the data in bit 16 at the data input has a bit position of 1 in the first 8 bit + 4 bit shift stage.
It is shifted to the right by 2 bits and the bit position is moved to a position corresponding to the 4th bit. Then 2 bits + 1
In the bit shift stage, as a result of shifting rightward by 1 bit, the bit position (16) finally input
The data appears at the third bit position, which is shifted to the right by 13 bits from.

FIG. 18 shows the structure of the signal shift means and the select means in the 8-bit + 4-bit shift stage shown in FIG.

In addition, FIG. 24 shows a conventional configuration of 8
The connection form of the signal shift means and the select means in the case of independently performing the bit shift and the 4-bit shift is shown. In this case, the area occupied by the wirings of the signal shift means in the vertical direction is 8 (shown as the height of 8 wirings in the figure) + 4 (also shown as the height of 4 wirings). ) = 12 wirings, but the wiring area for 12 wirings is also obtained in the configuration of FIG. 18 according to the present invention. Therefore, the area occupied by the signal shift means is changed (increased) by changing the configuration. There will be no. Further, comparing the circuit shown in FIG. 19 in which the 4-input 1-output selecting means of the present invention is configured with a transmission gate with the circuit shown in FIG. 25 having the equivalent conventional structure, the selector operates. Although the number of control signal lines for increasing the number is increased from eight in the conventional configuration to eight in the configuration of the present invention, the number of transistors is exactly the same, and the hardware is not increased except for the control signal lines. Absent.

19 and 25, considering the paths from the input of the data signal to the output of the data signal, the data signal passes through two transistor pairs in the conventional configuration. Since only one transistor pair is passed in the configuration according to, the impedance in the signal path is reduced to half, and the delay time at the time of passing the signal is reduced, and at the same time, the power consumption in the transistor pair is reduced. Become.

That is, in the first embodiment of the barrel shifter of the present invention, although the number of control signal lines of the selector is slightly increased, the speed of the shifter is increased at the cost of increased hardware for generating the control signal. In addition, low power consumption can be achieved.

FIG. 20 shows a modification of the combination of bit shift amounts executed in one selector stage in the first embodiment, that is, 8 bit / 1 bit shift and 4 bit / 2 bit shift. By equalizing the load capacities in the respective selecting means by making the total number of wirings, that is, the lengths of the horizontal wirings in the signal shifting means as shown in FIG. In the case where a buffer circuit for signal enhancement is used before and after the selector stage, the application of facilitating the design of load capacity sharing is possible.

FIG. 21 shows a second embodiment of the barrel shifter of the present invention. This embodiment is a bidirectional barrel shifter in which the input / output data length is 16 bits, the shift amount is designated by a 4-bit binary value, and the shift direction is designated by a 1-bit signal. In this example, selector stages that perform bit order inversion + 8 bit shift, 2 bit shift + 1 bit shift, 4 bit shift + bit order inversion in order from the data input side to the data output side are signal shift / bit. It is connected subsequently to the forward / reverse means or the signal shift means.

FIG. 22 shows an example of the configuration of the selecting means and selector control signal generating means including the bit order inversion shown in FIG. Instead of combining two types of shift amounts in the first embodiment of the barrel shifter of the present invention,
The feature is that the shift amount of each kind and the bit order inversion operation are combined to form one stage. Then, in the configuration shown in FIG. 21, after the block for performing the bit order inversion + 8 bit shift shown in FIG. 22 is installed at the first stage, 2 bits + 1 using the configuration shown in FIG. 17 in the first embodiment. Cascade the blocks that perform bit shifting. Finally, in the configuration shown in FIG. 21, the entire bidirectional barrel shifter is configured by installing a functional block having a function of performing a 4-bit shift and then reversing the bit order. That is, the characteristics of using the 4-input 1-output select means are the same as those in the first embodiment.

The data flow in the bidirectional shifter shown in FIG. 21 will be described. For example, consider the case of shifting 13 bits to the right. Figure 21
In the shifter shown in FIG. 3, assuming that the signal shift means is configured so that the shift is performed to the right when the bit order is not reversed, first, in the first bit order inversion + 8 bit shift stage, Only bit shift right is performed. Then, after the right shift of 1 bit is performed in the next 2-bit + 1-bit shift stage, only the 4-bit right shift is executed in the last 4-bit shift + bit forward inversion stage, so that a total of 13 bits is obtained. The right shift of is realized. In other words, by not using the bit order inversion mechanism installed in the first stage and the last stage of this shifter, it is indicated that the shift is to the right, which is the default shift direction of this shifter. Becomes a 13-bit shift by 8 bit shift + 4 bit shift + 1 bit shift.

Here, it will be described how the data whose bit position in the input data is at the 16th bit flows by the operation of shifting the shifter 13 bits to the right. In, the bit position of the 16th bit data is moved to the 8th bit by the operation of only the 8 bit shift. Subsequently, the data is shifted right by 1 bit in the 2 bit + 1 bit shift stage, and the bit position becomes the 7th bit. Then, in the last 4-bit shift + bit order inversion means, only 4-bit shift is performed, and finally the data appears at the position of the third bit. It can be seen that the data is shifted from the initial position of the 16th bit to the position of the 3rd bit which is shifted by 13 bits.

The operation of 13-bit left shift will be described. In this case, both the bit order inversion mechanism at the first stage and the last stage operate. First, in the bit order inversion + 8 bit shift stage of the first stage, the bit order of the input data is inverted and then right shifted by 8 bits. This gives, for example,
The data originally in the 0th bit moves to the position of the 7th bit. Then, the bit position is moved to the 6th bit by right shifting by 1 bit in the 2 bits + 1 bit shift stage. In the final 4-bit shift + bit order inversion stage, the bit order is reversed after right-shifting the sixth bit data by 4 bits. As a result, the position of the 6th bit is logically moved to the position of the 2nd bit and then to the position of the 13th bit by bit order inversion. A left shift of the 0 bit position data to the 13 bit position is achieved.

FIG. 23 shows a configuration example of the signal shift / bit order inversion means shown in FIG. It can be seen that 16 wiring spaces are required in the vertical direction. At this time, the signal path having the maximum wiring capacitance is b in FIG.
It is input from 0 and output to x15, which is exactly the width of the input data string.

FIG. 26 shows a signal shift / function having the same function.
An example in which the bit-order inversion means is configured by using the conventional 2-input 1-output select means is shown. In this case, the signal reversing means for performing only the bit order reversal already requires 16 wiring areas in the vertical direction. Furthermore, since a wiring space for 8 lines is added for performing 8-bit shift, a total of 24 wiring spaces are required. That is, from the viewpoint of the area of the wiring region required for the signal shift / bit order inversion means, the one using the barrel shifter of the present invention can be made smaller. Further, in the conventional configuration shown in FIG. 26, the longest signal path from the input of a signal to the output thereof is the path from b0 in the figure to z7 via y15. However, as compared with the one shown in FIG. 23 according to the present invention, an additional wiring length from y15 to z7 is added. Therefore, by using the barrel shifter of the present invention, the propagation distance of the signal can be shortened, and the shift operation can be speeded up.

[0072]

【The invention's effect】

(Multiply-adder / subtractor) As described above, in the multiplier-adder / subtractor of the present invention, the multiplier-adder / subtractor (A
XB + C), the third operand C is added at the same time as the partial product addition in the multiplication array for multiplying the first and second operands A and B. Compared with the adder / subtractor, it is possible to reduce the bit width of the arithmetic modules such as the shifter, adder, and leading 1 detector that compose the adder-subtractor, and to make the arithmetic module more compact. Can be converted. (Barrel shifter) By using a selector for performing shift, which has four inputs and one output, as compared with the conventional one having two inputs and one output, a transistor pair of a signal path through which an input data signal is shifted and output is output. It is possible to reduce the number of H.sub.2 to about 1/2 as compared with the conventional configuration, and the time required for passing a signal is shortened. Therefore, speeding up of the shift operation and reduction of power consumption of the transistor can be achieved.

Further, the invention can be similarly applied to the shift in both the left and right directions using the bit-order inversion mechanism, and it is possible to reduce the wiring area and at the same time achieve low power consumption and high-speed operation. Of course, by using the barrel shifter of the present invention, it becomes possible to execute the bit inversion operation of an arithmetic unit such as a multiplier at high speed and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of multiplication, addition and subtraction according to the present invention.

FIG. 2 is a block diagram showing a configuration of a multiplication array in the multiplication / subtraction device according to the present invention.

FIG. 3 is an explanatory diagram illustrating addition of a partial product by a Wallace tree and a third operand.

FIG. 4 is an explanatory diagram showing a configuration example of a Wallace tree by an adder group.

FIG. 5 is a block diagram showing a configuration of a floating point multiplication adder / subtractor according to the present invention.

FIG. 6 is an explanatory diagram showing a configuration example of a Wallace tree by an adder group.

FIG. 7 is an explanatory diagram for explaining the operation of the floating point multiplication adder / subtractor according to the present invention.

FIG. 8 is a block diagram showing a configuration example of a conventional multiplying / subtracting device.

FIG. 9 is a block diagram showing a configuration of a multiplication array in a conventional multiplication / subtraction device.

FIG. 10 is an explanatory diagram illustrating addition of partial products by a Wallace tree.

FIG. 11 is an explanatory diagram showing a configuration example of a Wallace tree by an adder group.

FIG. 12 is a logic circuit diagram showing a configuration example of an adder 4w (4-2 compactor).

FIG. 13 is a block diagram showing another configuration example of a conventional multiply-add / subtract arithmetic unit.

FIG. 14 is a block diagram showing a configuration example of a conventional floating point multiplication adder / subtractor.

FIG. 15 is a block diagram showing a configuration example of a Wallace tree in the multiplication array 201.

FIG. 16 is a configuration diagram of a 16-bit length unidirectional barrel shifter showing the first embodiment of the barrel shifter of the present invention.

FIG. 17 is a block diagram showing a configuration example of a selection unit, a selector control signal generation unit and a peripheral circuit used in the first embodiment.

FIG. 18 shows a 16-bit length barrel shifter according to the present invention,
The block diagram which shows the structural example of 8-bit + 4-bit signal shift means.

FIG. 19 is a block diagram showing a configuration example of 4-input 1-output selecting means according to the present invention.

FIG. 20 is a block diagram showing an example in which the configuration of the first embodiment of the barrel shifter is changed in consideration of load distribution.

FIG. 21 is a block diagram showing a configuration example of a 16-bit long bidirectional barrel shifter which is a second embodiment.

FIG. 22 is a block diagram showing a configuration example of a selection unit, a selector control signal generation unit, and a peripheral circuit used in the second embodiment.

FIG. 23 is a block diagram showing a configuration example of 8-bit signal shift / bit order inversion means of a 16-bit length bidirectional barrel shifter in the second embodiment.

FIG. 24 is a block diagram showing a configuration example of 8-bit and 4-bit signal shifting means of a 16-bit length barrel shifter in a conventional barrel shifter configuration.

FIG. 25 is a block diagram showing a configuration example of a 2-input 1-output selecting unit in a conventional configuration.

FIG. 26 is a block diagram showing a configuration example of bit order inversion means and 8-bit signal shift means of a 16-bit long bidirectional barrel shifter in a conventional configuration.

FIG. 27 is a block diagram showing a configuration example of a conventional unidirectional barrel shifter.

FIG. 28 is a block diagram showing an example in which a bidirectional barrel shifter is configured by selecting outputs of independent left and right shifters.

FIG. 29 is a block diagram showing a configuration example of a bidirectional barrel shifter in which a bit order inversion mechanism that reversely arranges bits of input data is arranged before and after the unidirectional barrel shifter in the conventional configuration.

[Explanation of symbols]

 101, 201, 301, 401 Multiplying array 202, 403 Digit adjustment shifter 102, 203, 402, Final adder 404 Incrementer 204, 405 Leading 1 detection circuit 205, 406 Normalization shifter 206, 407 Rounding circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G06F 17/10

Claims (8)

[Claims] 1. A multi-point adder / subtractor of fixed-point arithmetic for performing addition or subtraction between a multiplication value obtained by multiplying input first and second operands and an input third operand, which is a predetermined multiplication. According to an algorithm, a partial product generation circuit that generates a plurality of partial products corresponding to the first and second operands, an addition of the plurality of partial products, and an addition or subtraction of the third operand are performed in a tree structure. A multiplying array for outputting a plurality of weighted intermediate values of multiplication performed by a plurality of adder groups arranged in a plurality of groups, and a carry propagation type adder for adding the plurality of intermediate values of multiplication to obtain a multiplication / subtraction value A multiplicative adder / subtractor, comprising: 2. A multiplicative adder / subtractor of a floating point operation for adding or subtracting a multiplication value obtained by multiplying an input first and second operand and an input third operand, the mantissa thereof A partial arithmetic unit for generating a plurality of partial products corresponding to respective values of the mantissa of each of the first and second operands according to a predetermined multiplication algorithm; and addition of the plurality of partial products, A multiplication array that performs addition or subtraction of the mantissa value of the third operand by a plurality of adder groups arranged in a tree structure, and outputs a plurality of weighted multiplication intermediate values; A carry-propagation adder for adding a multiplication intermediate value to obtain a multiplication addition / subtraction value, and a multiplication addition / subtraction device. 3. A multiply-adder / subtractor for floating-point arithmetic, which performs addition or subtraction between a multiplication value obtained by multiplying input first and second operands and an input third operand, the multiplication being a predetermined multiplication. A partial product generation circuit for generating a plurality of partial products corresponding to respective mantissa values of the first and second operands according to an algorithm; and a value of an exponent part of the third operand for the first and second operands. Two
A shift circuit that performs digit adjustment of the mantissa value of the third operand so as to be equal to the exponent value of the product of the operands, the addition of the partial products, and the digit-adjusted third operation. A multiplication array that performs addition or subtraction with a part or all of the mantissa value of the operand of by a plurality of adder groups arranged in a tree structure and outputs a plurality of weighted intermediate intermediate values; A carry propagation adder for adding the plurality of intermediate values for multiplication to obtain a multiplication / subtraction operation value, and a multiplication / subtraction device. 4. A multiply-adder / subtractor of a floating-point operation for performing addition or subtraction between a multiplication value obtained by multiplying input first and second operands and an input third operand, wherein the predetermined multiplication is performed. A partial product generation circuit for generating a plurality of partial products corresponding to respective mantissa values of the first and second operands according to an algorithm; and a value of an exponent part of the third operand for the first and second operands. Two
A shift circuit that performs digit adjustment of the mantissa value of the third operand so as to be equal to the exponent value of the product of the operands, the addition of the partial products, and the digit-adjusted third operation. Addition or subtraction of the value of each digit of the lower digit in the value represented by the number of digits assigned to the operation of the product of the mantissas of the first and second operands of the value of the mantissa of the operand And a multiplication array that outputs a plurality of weighted multiplication intermediate values by a plurality of adder groups arranged in a tree structure, and the plurality of multiplication intermediate values are added to obtain the addition, subtraction value of the lower digit. The carry propagation adder to be obtained, and the number of digits assigned to the operation of the product of the mantissa parts of the first and second operands among the mantissa values of the third operand that have been aligned. The value of the upper digit that exceeds the value And the carry output of the carry propagation type adder,
An increment adder for adding to obtain an upper digit output value, and a means for bit-combining the upper digit output value and the lower and upper digit addition and subtraction values to obtain a final multiplication, addition and subtraction value. vessel. 5. A carry-save adder that divides a sum into a sum component and a carry component as an adder group that constitutes the multiplication array, an SD adder that adds using a redundant number, a PD adder, 6. The adder / subtractor according to claim 1, wherein any one of full adders is used. 6. A barrel shifter which has at least a data input, a data output and a control input, shifts the input data by the number of bits designated by the control input, and outputs the shifted data, from the supplied l (integer) bits. From the input data
L signal shift means for outputting four bit signals, l select means for selecting one from the four bit signals output by each signal shift means, and decoding the supplied control input , A control signal generation means for giving a control signal for instructing a bit signal to be selected to each selection means, wherein the i-th signal shift means of the l signal shift means is the i-th bit of the input data. The barrel shifter is characterized in that it outputs 0 bits, n (integer) bits, m (integer) bits, m + n bits, and 4 bit signals at positions where bit positions are shifted with respect to the signal. 7. A barrel shifter which has at least a data input, a data output, and a control input, and shifts and outputs the input data by the number of bits designated by the control input, and from the supplied l (integer) bits. From the input data
L first signal shifts / outputting 4 bit signals /
Bit order inversion means, and l first first signals selecting one from four bit signals output by each of the first signal shift / bit order inversion means
Selecting means, l signal shifting means for outputting four bit signals from the l outputs inputted from the l first selecting means, and four bit signals outputted by each signal shifting means. From the l second select means for selecting one from among the 1 second outputs, and the l second outputs for outputting four bit signals from the l outputs inputted from the l second select means. A signal shift / bit order inversion means, and one third third one selecting one from the four bit signals output by each of the second signal shift / bit order inversion means.
Selection means and control signal generation means for decoding the supplied control input to give a control signal for instructing each selection means of a bit signal to be selected. The i-th first signal shift / bit order inversion means of the bit order inversion means does not change, bit order inversion, o (integer) bit shift, bit order inversion, and i-th bit signal of the input data. o
(Integer) bit shift, which outputs four bit signals, and the i-th signal shift means of the l signal shift means does not shift the input i-th bit signal, p (integer) + q (integer) bits, p (integer) bits, q (integer) bits, and outputs four bit signals at positions where bit positions are shifted, and the l second signal shift / bit order The i-th second signal shift / bit order inversion means of the inversion means does not change, bit order inversion, r (integer) bit shift, r (integer) bit shift with respect to the i-th bit signal of the input data. A bidirectional shift barrel shifter, which outputs four bit signals that are in a relationship of: and bit order inversion. 8. The barrel shifter according to claim 6, wherein the signal shift means and the select means are connected in cascade for a required number of stages.