JPH088721A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device which can reduce power consumption while keeping its high speed operation by correcting the high level of a next-stage drive signal into a low potential level lower than a high power potential toy a degree equal to the threshold voltage or a MOS transistor TR and then supplying the drive signal of a corrected level to a circuit of the next stage. CONSTITUTION:A next-stage drive signal NDVx is set at Vcc (the base-emitter voltage of a bipolar TR Th1) while an input signal IN changes to a low level from a high level. Under such conditions, the MOS TR Tm4 and Tm5 are turned on and therefore the potential of a corrected next-stage drive signal NDV rises higher. However the Tm4 is turned off when the signal NDV is set at a prescribed potential since the signal NDV is supplied to the gate of the Tm4. Thus the supply of a charging current is discontinued to a circuit 2 of the next stage. As a result, a MOS TR Tm11 is turned off so that the leak current due to the Tm11 can be eliminated. Furthermore the amplitude of the signal NDV is minimized and the power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a so-called bi-MO in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate.
The present invention relates to an S type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A bi-MOS type circuit is a circuit that takes advantage of the characteristics of both high speed of a bipolar transistor, low power consumption of a MOS transistor, and high density mounting.
It has been widely adopted in semiconductor integrated logic circuits, semiconductor integrated memories, and the like.

FIG. 5 is a circuit diagram showing a general example (first example) of this type of semiconductor integrated circuit device.

This semiconductor integrated circuit device has a high power supply potential V
The first drive is performed between the cc point and a low power supply potential point (ground potential point GND), and is formed by a P-channel type MOS transistor Tm1 and an N-channel type MOS transistor Tm2 and inverts the level of the input signal IN to perform the first drive. A CMOS inverter for outputting a signal, an N-channel type M for receiving an input signal IN at a gate and outputting a second drive signal from a source
The drive unit 11 is composed of the OS transistor Tm3 and the resistor element R1 having one end connected to the source of the MOS transistor Tm3 and the other end connected to the ground potential point GND, and the collector receives the high power supply potential Vcc and the first drive signal is applied to the base. N that outputs the next stage drive signal NDVx from the receiving emitter
A PN-type bipolar transistor Tb1 and an NPN-type bipolar transistor Tb2 whose collector is connected to the emitter of the bipolar transistor Tb1 and the drain of the MOS transistor Tm3, and whose base receives the second drive signal and whose emitter is connected to the ground potential point GND. And a bi-MOS composite circuit 1 including an output buffer section 12
x, a P-channel type MOS transistor Tm11 which receives the high power supply potential Vcc at the source and a next stage drive signal NDVx at the gate, and a MOS transistor Tm at the drain.
And a next-stage circuit 2 including a CMOS-type inverter including an N-channel MOS transistor Tm12 having a gate connected to the drain and a source connected to the ground potential point GND and receiving the next-stage drive signal NDVx at the gate. I have.

Next, the operation of this semiconductor integrated circuit device will be described.

First, the process of shifting the level of the input signal IN from a high level to a low level will be described. The output potential of the inverter constituted by the MOS transistors Tm1 and Tm2, that is, the base potential of the bipolar transistor Tb1 increases. As a result, the level of the next-stage drive signal NDVx rises while maintaining a level lower than the base potential of the bipolar transistor Tb1 by the base-emitter voltage VF, and the potential rises from the high power supply potential Vcc to the VF level.
The bipolar transistor Tb1 is turned off at the level lowered by just that, and the supply of current to the next stage circuit 2 is stopped. Therefore, the high level of the next stage drive signal NDVx is (Vcc-V
Equal to F). Further, since the MOS transistor Tm3 is turned off and the resistor R1 pulls down the base of the bipolar transistor Tb2, the bipolar transistor Tb2
Turn off.

Next, a process in which the level of the input signal IN shifts from a low level to a high level will be described.

[0008] The output potential of the inverter formed by the MOS transistors Tm1 and Tm2, that is, the base potential of the bipolar transistor Tb1, falls, and the bipolar transistor Tb1 turns off. At the same time, the MOS transistor Tm3 turns on and the bipolar transistor Tb2
To supply a base current to the bipolar transistor T.
b2 is turned on to lower the potential of the next-stage drive signal NDVx.

As described above, the Bi-MOS composite circuit 1x performs an inverter operation to drive the next stage circuit 2.

By modifying the bi-MOS composite circuit 1x,
FIG. 6 shows an example (second example) of a semiconductor integrated circuit device when the next-stage circuit is a semiconductor memory.

The bi-MOS composite circuit 1y of the semiconductor integrated circuit device includes a driving unit 11a including MOS transistors Tm1 and Tm2 and including a CMOS inverter for inverting the level of an input signal IN, and a collector connected to a power supply potential Vc.
N which receives the output signal of the inverter of the drive unit 11a at the base receiving c and outputs the next stage drive signal NDVx from the emitter
A PN-type bipolar transistor, and an N of which the drain is connected to the emitter of the bipolar transistor Tb1 and the source is connected to the ground potential point and whose gate receives the input signal IN.
And an output buffer unit 12a formed of a channel type MOS transistor Tm6. The next stage circuit 2a includes a word line WL transmitting a next stage drive signal NDVx.
And bit lines BL1 and BL2 forming a pair with each other, and two inverters IV1 and IV2 forming a memory holding unit, connected between the memory holding unit and bit lines BL1 and BL2 and transmitted to the word line WL at the gate. Next stage drive signal NDV
A pair of P-channel type MOS transistors T receiving x
m13 and Tm14 (for example, refer to Japanese Patent Application No. 5-200847) and bit lines BL1 and BL
It has a configuration including resistors R11 and R12 for precharging L2 to the high power supply potential Vcc level.

Next, the operation of the semiconductor integrated circuit device will be described.

First, the process of shifting the level of the input signal IN from a high level to a low level will be described. The output potential of the inverter constituted by the MOS transistors Tm1 and Tm2, that is, the base potential of the bipolar transistor Tb1 increases. On the other hand, the MOS transistor Tm6 turns off. As a result, the level of the next-stage drive signal NDVx changes from the base potential of the bipolar transistor Tb1 to the base level.
The bipolar transistor Tb1 is turned off when the potential drops by the emitter-to-emitter voltage VF and rises, and the potential drops by VF from the high power supply potential Vcc.
The supply of the charging current to the word line WL of the next stage circuit 2a is stopped. Therefore, the high level of the next-stage drive signal NDVx of the word line WL is equal to (Vcc-VE). At this time, MO
The S transistors Tm13 and Tm14 are turned off, and writing / reading of data to / from the memory cell MC is stopped.

Next, a process in which the level of the input signal IN shifts from a low level to a high level will be described.

The output potential of the inverter constituted by the MOS transistors Tm1 and Tm2, that is, the base potential of the bipolar transistor Tb1 decreases, and the bipolar transistor Tb1 turns off. At the same time, the MOS transistor Tm6 is turned on, and the potential of the next-stage drive signal NDVx of the word line WL is reduced.

At this time, the MOS transistors Tm13,
Tm14 turns on, and writing and reading of data to and from memory cell MC are performed.

FIG. 7 shows another modified circuit (third example) of the bi-MOS composite circuit 1x.

The output buffer section 12b of the bi-MOS composite circuit 1z has an NPN type bipolar transistor T.
b1 and a PNP-type bipolar transistor Tb3, which is a complementary type drive unit 11b.
Are also deformed accordingly. The basic operation is the same as in the first example, and a description thereof will be omitted.

[0019]

These conventional semiconductor integrated circuit devices include bi-MOS composite circuits 1x, 1y, 1z.
The high level of the next stage drive signal NDVx output from
cc-VF), and this next-stage drive signal NDVx
P-channel type M of the next stage circuit 2 or 2a receiving the gate at the gate
Since the high power supply potential Vcc is supplied to the sources of the OS transistors Tm11, Tm13, and Tm14, the base-emitter voltage VF of the bipolar transistor is determined by the band gap of the semiconductor (eg, Si). On the other hand, since the threshold voltage of the MOS transistor can be set arbitrarily, the P-channel MOS transistors Tm11, Tm13, Tm14 of the next-stage circuits 2, 2a
Is lower than the base-emitter voltage VF, the MOS transistors Tm11, Tm13, Tm that should be turned off at the high level of the next stage drive signal NDVx
The m14 does not turn off completely, resulting in an increase in power consumption and a risk of malfunction.

In order to solve the above problems, bi
-If a P-channel type MOS transistor is inserted in parallel with the bipolar transistor of the output buffer section of the MOS composite circuit, the input capacitance increases and the signal amplitude becomes larger than necessary, which impairs high-speed operation and consumes power. There is a problem that power consumption increases.

An object of the present invention is to reliably turn off the P-channel MOS transistor of the next-stage circuit by the high level of the next-stage drive signal, limit the signal amplitude, and reduce power consumption while maintaining high-speed operation. It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing and preventing malfunction.

[0022]

According to the present invention, there is provided a semiconductor integrated circuit device according to the present invention, wherein a drive section for generating a drive signal having a high power supply potential in response to an input signal, and a collector receiving the high power supply potential. An output buffer including an NPN-type bipolar transistor for receiving a drive signal at a base and outputting a high-level next-stage drive signal lower than the high power supply potential by a base-emitter voltage when the drive signal is at a high level from an emitter A bi-MOS composite circuit having a unit;
A next-stage circuit including a P-channel type first MOS transistor having a threshold voltage smaller than the base-emitter voltage of the bipolar transistor, receiving the high power supply potential at the source, and receiving the next-stage drive signal at the gate. Having a threshold voltage of the same level as that of the first MOS transistor, a source receiving the high power supply potential, and a gate receiving the next-stage drive signal at the gate.
Including the channel-type second MOS transistor, the high level of the next-stage drive signal is corrected to a level lower than the high power supply potential by the threshold voltage of the second MOS transistor to correct the high level of the first MOS transistor. An output potential correction unit that supplies the gate is provided.

The output potential correction section includes an inverter for inverting the level of the next-stage drive signal from the output buffer section, and a series connection between the high power supply potential point and the next-stage drive signal output terminal of the output buffer section. And a P-channel type second and third MOS transistor having a gate receiving the next-stage drive signal and the output signal of the inverter, respectively, and further configured as a circuit. The substrate potential of the second MOS transistor is used as its source potential, and the substrate potential of the third MOS transistor is used as its source potential.

[0024]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor integrated circuit device shown in FIG. 5 in that the bi-MOS composite circuit 1 is used.
In x, the source receives the high power supply potential Vcc and the gate receives the next-stage drive signal NDVx from the output buffer unit 12, which is smaller than the base-emitter voltage VF of the bipolar transistor Tb1 of the output buffer unit 12 and the next-stage circuit 2 P-channel MOS transistor Tm11 having a threshold voltage VTP equivalent to (equal to) P-channel MOS transistor Tm11, and an inverter IV1 inverting the level of the next-stage drive signal NDVx from the output buffer unit 12. , A source is connected to the drain of the MOS transistor Tm4, the gate receives the output signal of the inverter IV1 and the source receives the next-stage drive signal NDVx, and the P-channel type MOS transistor Tm5 is provided. Next stage drive signal from section 12 The high level of DVx high power supply potential Vc
threshold voltage VT of the MOS transistor Tm4 with respect to c
Next-stage drive signal N corrected by correcting P to a lower level
Output as DV, and MOS transistor T of the next stage circuit 2
an output potential correction unit 13 that supplies the output potential to the gate of m11;
This is in that the bi-MOS composite circuit 1 is used.

Next, the operation of this embodiment will be described.
However, from the output buffer section 12 (Vcc-V
The operation of the drive unit 11 and the output buffer unit 12 in the process of outputting the next-stage drive signal NDVx of the level F) and the process of transition of the input signal IN from the low level to the high level are the same as those in the first embodiment. Since they are the same, description of this part is omitted.

During the transition of the input signal IN from the high level to the low level, the next stage drive signal NDVx becomes (Vcc-V
F), the threshold voltage VTP of the MOS transistor Tm4 is smaller than the base-emitter voltage VF of the bipolar transistor Tb1, so that the MOS transistor Tm4 is on, and the output signal of the inverter IV1 is low level. Since the MOS transistor Tm5 is turned on, the MOS transistor Tm5 is turned on.
5, the potential of the corrected next-stage drive signal NDV further rises. However, since the corrected next stage drive signal NDV is also supplied to the gate of the MOS transistor Tm4, the corrected next stage drive signal N
When the potential of DV becomes (Vcc-VTP), the MOS transistor Tm4 is turned off, and the supply of the charging current to the next stage circuit 2 is stopped. Therefore, the corrected high level of the next stage drive signal NDV becomes (Vcc-VTP), and the source-gate voltage of the MOS transistor Tm11 of the next stage circuit 2 having the same threshold voltage VTP as the MOS transistor Tm4 is Since it becomes equal to the threshold voltage, the MOS transistor Tm11 is just turned off.

That is, not only the leakage current due to the MOS transistor Tm11 is eliminated, but also the next-stage drive signal ND
The amplitude of V can be suppressed to a necessary minimum, so that high-speed operation can be maintained, power consumption can be reduced, and malfunction can be prevented. This is the same as when the next-stage circuit to be driven is the next-stage circuit 2a of the semiconductor memory shown in FIG.

When the drive signal NDVx falls below a predetermined potential in the process of the input signal IN shifting from the low level to the high level, the output signal of the inverter IV1 becomes the high level and the MOS transistor Tm5 is turned off. Therefore, by setting the threshold voltage of the inverter IV1 to an appropriate value, the output potential correction unit 1 in this process
The influence of 3 can be eliminated.

FIG. 2 is a circuit diagram of an output potential correction unit according to a second embodiment of the present invention.

In this embodiment, the high power supply potential Vc is applied to the source.
The output signal of the inverter IV1 is supplied to the gate of the MOS transistor Tm4 receiving c, and the next-stage drive signal NDVx is supplied to the gate of the MOS transistor Tm5 whose drain is the output terminal of the corrected next-stage drive signal NDV. The substrate potentials of the MOS transistors Tm4 and Tm5 are set to their own source potentials.

No matter which gate of the MOS transistors Tm4 and Tm5 is supplied with the output signal of the inverter IV1,
It is clear from the description of the operation of the first embodiment that the operation and effect remain unchanged.

The MOS transistors Tm4, Tm5
By setting each of the substrate potentials of the MOS transistors Tm4 and Tm5 to its own source potential, an increase in threshold voltage due to the substrate effect of these MOS transistors Tm4 and Tm5 can be prevented and the MOS transistors Tm4 and Tm5 can be stabilized.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

This embodiment is an application of the first embodiment of the present invention shown in FIG. 1 to the conventional semiconductor integrated circuit device shown in FIG. 6, and is applied to a bi-MOS composite circuit 1y. The output potential correction unit 13 is provided to form the bi-MOS composite circuit 1a.

The operations of the driving section 11a and the output buffer section 12a are the same as those of the prior art shown in FIG.
And the coupling operation with the bipolar transistor Tb1 are the same as those of the first embodiment, and the description of the operation of this embodiment will be omitted. The effect of this embodiment is, of course, the same as that of the first embodiment.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

This embodiment is obtained by applying the first embodiment of the present invention shown in FIG. 1 to the conventional semiconductor integrated circuit device shown in FIG. 7, and is applied to a bi-MOS composite circuit 1z. An output potential correction unit 13 is provided to form a bi-MOS composite circuit 1b.

The operation of the driving section 11b and the output buffer section 12b of this embodiment is the same as that of the prior art shown in FIG. 7, and the operation of the output potential correction section 13 and its bipolar transistor T
Since the connection operation with b1 is the same as in the first embodiment, the description of the operation is omitted. The effect of this embodiment is the same as that of the first embodiment.

In the third and fourth embodiments, the output signal of the inverter IV1 can be applied to the gate of the MOS transistor Tm4 of the output potential correction section 13, and the next stage drive signal NDVx can be applied to the gate of Tm5. However, the threshold voltage can be stabilized by using the substrate potentials of the MOS transistors Tm4 and Tm5 as their own source potentials.

Further, in the above-described first to fourth embodiments, the next-stage circuit driven by the corrected next-stage drive signal NDV is a CMOS inverter type next-stage circuit shown in FIGS. 2 and the next-stage circuit 2a of the semiconductor memory type shown in FIG. 6, or any other type of circuit, the MOS transistors Tm11, Tm13 and Tm14 of these next-stage circuits 2 and 2a. Any circuit including a considerable MOS transistor may be used. Further, in these embodiments, the output potential correction sections 13 and 13a are incorporated in the bi-MOS composite circuits 1, 1a and 1b, but they may be independent circuits.

[0043]

As described above, according to the present invention, the collector is smaller than the base-emitter voltage of the NPN type bipolar transistor of the output buffer section which receives the high power supply potential and outputs the next stage drive signal from the emitter, and the source. Has a threshold voltage of the same level as the P-channel type MOS transistor of the next stage circuit which receives the high power supply potential at the gate and receives the high power supply potential at the source, and the above next stage drive signal at the gate. Output potential correction including a P-channel type MOS transistor for receiving and correcting the high level of the next stage drive signal to a potential lower than the high power supply potential by the threshold voltage of this MOS transistor and supplying it to the next stage circuit. By providing the part, the P-channel type MOS transistor of the next-stage circuit is surely turned off, and
Since the leakage current due to the OS transistor can be eliminated and the amplitude of the next-stage drive signal can be minimized, there is an effect that high-speed operation can be maintained, power consumption can be reduced, and malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output potential correction unit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a first example of a conventional semiconductor integrated circuit device.

FIG. 6 is a circuit diagram showing a second example of a conventional semiconductor integrated circuit device.

FIG. 7 is a circuit diagram showing a third example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1, 1a, 1b, 1x, 1y, 1z Bi-MOS composite circuit 2, 2a Next stage circuit 11, 11a, 11b Drive unit 12, 12a, 12b Output buffer unit 13, 13a Output potential correction unit BL1, BL2 Bit line IV1 , IV11, IV12 Inverter MC Memory cell R1, R2, R11, R12 Resistance Tb1-Tb3 Bipolar transistor Tm1-Tm6, Tm11-Tm14 WL Word line

Claims (7)

[Claims] A driving unit for generating a driving signal having a high power supply potential level in response to an input signal; receiving the high power supply potential at a collector; receiving the driving signal at a base; A bi-MOS composite circuit having an output buffer unit including an NPN-type bipolar transistor for outputting a high-level next-stage drive signal that is lower by a base-emitter voltage than the high power supply potential when is at a high level; A next-stage circuit including a P-channel type first MOS transistor having a threshold voltage smaller than the base-emitter voltage of the transistor and having the source receiving the high power supply potential and the gate receiving the next-stage drive signal; In the integrated circuit device, the first MOS
A second MOS transistor of a P-channel type having a threshold voltage of the same level as that of the transistor, receiving the high power supply potential at the source and receiving the next-stage drive signal at the gate, and setting the high-level of the next-stage drive signal to the high level; A semiconductor integrated circuit device, comprising: an output potential correction unit that corrects a power supply potential to a level lower by a threshold voltage of the second MOS transistor and supplies the level to a gate of the first MOS transistor. 2. An inverter for inverting the level of a next-stage drive signal from an output buffer unit, and an output potential correction unit connected in series between a high power supply potential point and a next-stage drive signal output terminal of the output buffer unit. 2. The semiconductor integrated circuit device according to claim 1, wherein said circuit comprises a P-channel type second and third MOS transistor whose gates receive the next-stage drive signal and the output signal of said inverter, respectively. 3. The substrate potential of the second MOS transistor of the output potential correction unit is used as its source potential, and the substrate potential of the third MOS transistor is used as its source potential.
13. The semiconductor integrated circuit device according to claim 1. 4. An NPN-type first bipolar transistor for outputting a next-stage driving signal from an emitter by receiving a high power supply potential at a collector, receiving a driving signal at a base, and a collector comprising the first bipolar transistor. A CMOS type inverter having an NPN-type second bipolar transistor connected to the emitter of the transistor and having the emitter connected to the low power supply potential point, and a drive unit for inverting the level of an input signal to make a precursor drive signal And a source receiving the input signal at the gate and connecting the source and the drain to the base and the collector of the second bipolar transistor.
2. The semiconductor integrated circuit device according to claim 1, wherein the circuit includes a channel type MOS transistor and a resistance element connected between a base and an emitter of the second bipolar transistor. 5. An NPN type bipolar transistor, wherein the output buffer section receives a high power supply potential at the collector, receives a drive signal at the base, and outputs a next stage drive signal from the emitter.
An N-channel MOS transistor having a gate receiving an input signal and having a source connected to a low power supply potential point and a drain connected to the emitter of the bipolar transistor is provided. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a circuit provided with a CMOS type inverter as a drive signal. 6. An NPN-type first bipolar transistor for receiving a high power supply potential at a collector, receiving a drive signal at a base and outputting a next-stage drive signal from an emitter, and connecting the collector to a low power supply potential point. And an emitter connecting the emitter to the emitter of the first bipolar transistor.
A circuit including an NP-type second bipolar transistor, a drive unit, a CMOS-type inverter that inverts the level of an input signal to obtain the drive signal, and a gate that receives the input signal and a source thereof is the low power supply potential. 2. A circuit comprising an N-channel type MOS transistor connected to a point and having a drain connected to the base of the second bipolar transistor, and a resistor connected between the emitter and the base of the second bipolar transistor. The semiconductor integrated circuit device described. 7. A next stage circuit includes a storage unit, a bit line transmitting read data and write data of the storage unit, a word line transmitting a next stage drive signal, and a gate connected to the word line. An access P which connects a source and a drain between the bit line and the signal input / output terminal of the memory holding unit.
2. The semiconductor integrated circuit device according to claim 1, which is a semiconductor memory including a channel type first MOS transistor.