JPH088667A - Demodulating circuit - Google Patents

Abstract

PURPOSE:To prevent the increase of reception error regardless of the quick rise of the reception level by limiting the amplitude of the reception signal inputted to an automatic gain control circuit by a limiter circuit. CONSTITUTION:The modulated signal which comes from a radio frequency circuit part (RF part) and is reduced to an intermediate frequency is inputted to an automatic gain control circuit (AGC) 6 through a limiter circuit 1, and the output of this AGC 6 is inputted to an orthogonal demodulation circuit 7. In this case, the limiter circuit 1 is provided for the purpose of preventing the AGC 6 from being saturated even in the case of the large change of the reception level in a short time and has the amplitude limit value set to such value by a limiter output limit value control circuit 3 that a gain variable amplification part 4 of the AGC 6 is not saturated. That is, input/output characteristics of the limiter circuit 1 are linear in the case of the output level lower than the amplitude limit value; but if the input signal of the limiter circuit 1 exceeds the amplitude limit value, the output level is limited to this amplitude limit value or lower.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit having an automatic gain control circuit, and more particularly to a demodulation circuit improved so as to prevent the automatic gain control circuit from becoming saturated so as to prevent an increase in reception errors.

[0002]

2. Description of the Related Art Phase modulation is often used in a wireless system for modulating digital data and transmitting the data wirelessly. This phase modulation is a carrier
Is a modulation method for modulating the phase of a carrier wave having a high frequency of GHz order in a system having a high transmission rate or a system using a plurality of frequencies such as a mobile phone.

FIG. 6 shows an example of a general configuration of a receiving system of a wireless system using such phase modulation.
In FIG. 6, the receiving system 11 includes a radio frequency circuit section (RF section) 8 for selecting and amplifying a signal having a desired frequency among signals received from the antenna 12 and converting the signal to an intermediate frequency (IF). An intermediate frequency circuit section (IF section) 9 for converting a signal from (IF) to a baseband, and a detection circuit 10 for extracting the original signal by detecting the modulated wave.

By the way, in such a receiving system, as described above, when the carrier wave is as high as GHz order, the receiving level varies depending on the condition of the transmission path in the wireless section.
The cause of this reception level fluctuation is propagation conditions such as surrounding buildings and terrain, and changes in conditions due to movement of the receiver, and is generally known as a phenomenon called fading.

Therefore, conventionally, an automatic gain control circuit (AGC) is provided in the IF section 9 in the reception system of this type of radio system, and even if the reception level changes, the AGC causes the detection circuit 10 to operate. The level of the input modulated wave is controlled to be as constant as possible.

FIG. 7 shows a configuration example of an intermediate frequency circuit section (IF section) 9 provided with this AGC. In FIG. 7, an automatic gain control circuit (AGC) 6 is provided with a level detecting section 5, It is composed of a variable gain amplifier 2 and a gain controller 4,
The received signal level is adjusted by this AGC 6, and the level of the modulation signal output from the quadrature demodulation circuit 7 is controlled so as to always be a level suitable for the detection circuit 10.

FIG. 8 shows an operation example of the AGC 6 described above. In FIG. 8, (a) is an input waveform of the AGC 6,
(B) shows the control gain of the AGC 6, and (c) shows the output waveform of the AGC 6.

As described above, by using the AGC 6, the modulation wave level input to the detection circuit 10 is kept substantially constant even if the reception level fluctuates, thereby reducing the detection error in the detection circuit 10. it can.

Here, the AGC is required to have a wide gain variable range, excellent linearity over the entire dynamic range, and to be able to reduce errors during detection in the detection circuit 10 in the subsequent stage.

However, if the reception level changes greatly in a short time, the AGC 6 may not follow the target in time, and the reception error in the detection circuit 10 at the subsequent stage may increase. Especially when the reception level is low (AGC
Considering a case in which the gain of No. 6 becomes large), the gain control unit 4 of the AGC 6 inputs an excessive signal to the variable gain amplifying unit 2 to cause the variable gain amplifying unit 2 to operate. Cause saturation. Generally, the AGC 6 is designed to perform linear amplification, and if saturation occurs due to excessive input, it takes some time to return to linear operation region operation. In other words, even if the level detection unit 5 detects the output level over and the gain control unit 4 tries to reduce the gain of the variable gain amplification unit 2, the output of the AGC 6 cannot immediately follow and is restored with a time constant peculiar to the circuit. It will be.

This phenomenon is shown in FIG. In FIG.
(A) is an input waveform of AGC6, (b) is a control gain of AGC6, (c) is an output waveform of AGC6. In the figure, the reception level sharply changes at point D, and saturation of the AGC 6 occurs. When the AGC 6 causes such saturation, the output of the AGC 6 cannot immediately recover from the saturated state of the AGC 6 as shown in the figure, and as a result, a reception error occurs for a while and the entire demodulation circuit continues to be in an unreceivable state. There is a problem.

[0012]

As described above, when a sudden change in the reception level occurs in the demodulation circuit, the AG
There is a problem that C falls into a saturated state, and a reception error continues until the saturated state is restored.

Therefore, an object of the present invention is to provide a demodulation circuit capable of reducing the reception error even if the reception level changes abruptly.

[0014]

To achieve the above object, the present invention detects the level of a received signal received,
In a demodulation circuit including an automatic gain control circuit that controls the amplitude of the received signal to a constant value by controlling the amplification gain of the received signal in accordance with the detection level, the reception circuit is provided before the automatic gain control circuit. A limiter circuit for limiting the amplitude of the signal is provided.

[0015]

According to the present invention, the limiter circuit provided in the preceding stage of the automatic gain control circuit limits the amplitude of the received signal input to the automatic gain control circuit so that the automatic gain control circuit will not be saturated, whereby , Reducing reception errors even if there is a sudden change in reception level. Here, the limiter circuit varies its amplitude limit value in accordance with the control gain of the automatic gain control circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a demodulation circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a main part of an embodiment of a demodulation circuit according to the present invention. This FIG. 1 shows an intermediate part for converting a signal from the intermediate frequency (IF) to the base band explained in FIG. 8 shows a portion corresponding to the frequency circuit portion (IF portion) 9, that is, a portion corresponding to FIG. 7 described as a conventional example. In FIG. 1, the same parts as those in FIG. 7 are designated by the same reference numerals.

In FIG. 1, a radio frequency circuit section (RF
The modulation signal dropped to the intermediate frequency from the section 8) (see FIG. 6) is passed through the limiter circuit 1 to the automatic gain control circuit (AG
C) 6 and the output of this AGC 6 is input to the quadrature demodulation circuit 7.

Here, the limiter circuit 1 is provided in order to prevent the AGC 6 from being saturated even when the reception level greatly changes in a short time. The limiter circuit 1 is provided with a limiter output. The limit value control circuit 3 sets the amplitude limit value to a value at which the variable gain amplifying section 4 of the AGC 6 is not saturated.

That is, the input / output characteristics of the limiter circuit 1 are
The output level below the amplitude limit value is linear, and when the input signal of the limiter circuit 1 exceeds the amplitude limit value, its output level is limited to a level below the amplitude limit value.

Here, the limiter output limit value control circuit 3 is
Information about the amplitude limit value of the limiter circuit 1 is received from the gain control unit 4 of the AGC 6, and the limiter circuit 1 is based on this information.
Set the amplitude limit value of.

FIG. 2 shows an input / output characteristic example of the variable gain amplifying section 2 of the AGC 6. In FIG. 2, the horizontal axis is the input level,
The vertical axis represents the output level. In this example, the parameter has three types of gains, a, b, and c. As shown in the figure, when the gains are a, b, and c, the slopes are different, but the output saturation level s becomes the same level. Also,
The input level that causes saturation for each gain is V
I1, VI2 and VI3.

FIG. 3 shows an example of input / output characteristics of the limiter circuit 1. In FIG. 3, the horizontal axis represents the input level and the vertical axis represents the output level. As is clear from FIG. 3, the output level with respect to the input level is the limited output level (V0 in the figure).
1, V02, V03) is linear.

Now, between the limit output level of the limiter circuit 1 and the input level that causes saturation of the variable gain amplifying section 2, when the gains are a, b, and c, V01≤VI1, V.
If the relationship of 02 ≦ VI2 and V03 ≦ VI3 is guaranteed,
Even if the input level increases rapidly, the limiter circuit 1
The signal level input to C6 is limited to a level at which the variable gain amplifying section 2 of the AGC 6 does not saturate.

FIG. 4 shows an example of the signal waveform of each part of the circuit shown in FIG. 1 in which the characteristics of FIGS. 2 and 3 are added. In FIG. 4, (a) is an input waveform of the limiter circuit 1, (b) is an output waveform of the limiter circuit 1, and (c) is an output waveform of the AGC 6. In FIG. 4, the gain of the AGC 6 is initially c, and the input level of the limiter circuit 1 rapidly increases at the point h. However, due to the operation of the limiter circuit 1, the gain c is increased in the subsequent section g.
It is suppressed to the amplitude corresponding to.

In the section j after the time sufficient for switching the AGC 6 and the gain has elapsed, the output of the limiter circuit 1 switches to the one corresponding to the gain b. Here, this section j is A
It is set longer than the transition time required to change the gain of GC6. The operation control of the limiter circuit 1 is performed by the limiter output limit value control circuit 3 of FIG.

FIG. 5 shows a specific configuration example of the limiter circuit 1 shown in FIG. In FIG. 5, an npn transistor 22 having a collector connected to a power supply 35 and an npn transistor 23 having an emitter coupled thereto has a collector connected to the power supply 35 via a load resistor 21.

The emitters of the transistors 22 and 23, which are emitter-junctioned, are connected via a current source 31 to a power source 3
6 is connected.

The collector of the transistor 23 is further connected to the base of the transistor 24, the collector of the transistor 24 is connected to the power source 35, and the emitter thereof is connected to the anode of the diode 29 and the base of the transistor 25.

The collector of the transistor 25 is connected to the power source 35.
The emitter is connected to the emitter of the npn transistor 27 and serves as the output terminal 41 of the limiter circuit 1.

The cathode of the diode 29 is the diode 3
The base of the transistor 27 is connected to the current source 32 via 0, and the current source 32 is connected to the power source 36.

The output terminal 41 is connected to the base of the transistor 23 to form a voltage follower. Therefore, in this example, the gain of the limiter circuit 1 is 1.

Further, the collector of the base of the transistor 24, the base of the output terminal 41, and the emitter of the transistor 24 are connected to the power supply 36 via the control voltage source 33, respectively.
The output limiting circuit of the limiter circuit qn1 includes the transistor 26, the collector of which is connected to the base of the transistor 27, the base of which is connected to the output terminal 41 and the emitter of which is connected to the power supply 36 through the control voltage source 34. Are configured. Next, the operation of this circuit will be briefly described. When the level of the signal input to the input terminal 40 is equal to or lower than the output limit value, the signal is directly output from the output terminal 41 at the same level.

When the input level of the signal input to the input terminal 40 increases and the output level output from the output terminal 41 increases accordingly, the transistor 26 turns on in the positive direction and the base voltage of the transistor 24 increases. Is controlled so that it does not rise further, and as a result, output 41
Limit the voltage value (amplitude) of. The output limit value in this case is determined by the control voltage source 33.

On the other hand, when the input level increases in the negative direction, the transistor 28 is turned on and the base voltage of the transistor 27 is controlled so as not to drop further, and as a result, the voltage value (amplitude) of the output 41 is limited. . The output limit value in this case is determined by the control voltage source 34.

In the above configuration, the control voltage sources 33, 34
Are controlled by the limiter output limit value control unit 3 shown in FIG. The control voltage sources 33 and 34 are simple D
It can be easily configured by an A / A converter or the like.

[0037]

As described above, according to the present invention,
Since the limiter circuit provided before the automatic gain control circuit is configured to limit the amplitude of the received signal input to the automatic gain control circuit, even if a sudden increase in the received level occurs, the automatic gain in the demodulation circuit The control circuit does not fall into a saturated state, which makes it possible to prevent an increase in reception errors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a demodulation circuit according to the present invention.

FIG. 2 is a diagram showing an example of input / output characteristics of the variable gain amplifying section shown in FIG.

FIG. 3 is a diagram showing an input / output characteristic example of the limiter circuit shown in FIG.

FIG. 4 is a diagram showing an example of signal waveforms of respective parts of the circuit shown in FIG. 1 in which the characteristics of FIGS. 2 and 3 are added.

5 is a circuit diagram showing a specific configuration of the limiter circuit shown in FIG.

FIG. 6 is a block diagram showing a general configuration example of a reception system of a conventional wireless system using phase modulation.

7 is a block diagram showing a conventional example of the intermediate frequency circuit unit (IF unit) shown in FIG.

8 is a waveform diagram illustrating the operation of the automatic gain control circuit (AGC) of the intermediate frequency circuit unit (IF unit) shown in FIG.

9 is a waveform diagram for explaining a problem in the operation of the automatic gain control circuit (AGC) of the intermediate frequency circuit unit (IF unit) shown in FIG.

[Explanation of symbols]

 1 limiter circuit 2 variable gain amplifier circuit 3 limiter output limit value control circuit 4 gain control section 5 level detection section 6 automatic gain control circuit (AGC) 7 quadrature demodulation circuit 8 radio frequency circuit section (RF section) 9 intermediate frequency circuit section ( IF part) 10 Detection circuit 11 Reception system 12 Antenna

Claims (2)

[Claims] 1. An automatic gain control circuit for detecting the level of a received signal received, and controlling the amplification gain of the received signal corresponding to the detected level to control the amplitude of the received signal constant. In the demodulation circuit, a limiter circuit for limiting the amplitude of the received signal is provided in the preceding stage of the automatic gain control circuit. 2. The demodulator circuit according to claim 1, wherein the limiter circuit has a variable amplitude limit value corresponding to a control gain of the automatic gain control circuit.