JPH0886665A - Absolute value encoder - Google Patents

Abstract

PURPOSE: To realize an errorless detection by providing a circuit for detecting first and second binary serial codes divided by N and operating the exclusive OR thereof thereby outputting an incremental signal. CONSTITUTION: In order to obtain incremental signals 1A, 1B, output signals DA2-DA5 and DB2-DB5 are inputted to an logic operation circuit 6 comprising EX-OR gates G1-G6. The gates G1-G4 output operation output signals DG1-DG4 while the gate G6 outputs the incremental signal 1A in response to the output signals DG3, DG4 and the gate G5 outputs the signal 1B in response to the DG1, DG2. At the variation point of any one of the output signals DA2, DB2, DA3, DB3, other three signals are in a stable region and thereby only one variation point is present in each dived region. Since the 1B is obtained through division by four signals and employed for judging the region of other signal, errorless reading is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute value encoder using a serial code represented by a binary code of 0 and 1 (herein referred to as a binary serial code).

[0002]

2. Description of the Related Art Conventionally, absolute value encoders have used a code plate for arranging a plurality of tracks having different numbers of slits to form a binary code having a desired number of bits. In this method, however, the number of tracks depends on the number of bits. However, there is a problem in that it is difficult to reduce the size of the absolute value encoder due to the increase of.

Therefore, for example, an absolute value encoder using a M-series random number code and provided with a code plate in which a binary serial code is arranged on a single track has been proposed. This type of absolute encoder has 2 ⁿ divisions corresponding to the desired resolution.
The serial code is engraved on the code plate in the form of a slit or the like, and n
Since the detection element is configured to read the code string to obtain the absolute position data, there is a read error in the detection value in the boundary area (unstable area) of the division value (minimum reading unit) of the binary serial code. The problem arises.

In order to solve this problem, two sets of n detecting elements are prepared by dividing them into an A group and a B group, the detecting elements of the A group and the detecting elements of the B group are arranged with a phase difference, and a boundary is provided. For the purpose of discriminating a region (unstable region), an incremental code track divided into 2 × 2 ⁿ pieces of this serial code is separately provided on the code plate, and this incremental code is detected by another detection element, and this detection is performed. Using the results, select the stable region of the detection value by the detection element of group A or group B,
A configuration for obtaining a detection value without reading error is known.

[0005]

As described above, in the conventional absolute value encoder provided with the binary serial code on a single track, in order to obtain absolute position data without reading error,
In addition to the 2 ⁿ binary serial codes, 2 × 2 ⁿ incremental codes must be provided on a different track, and a complicated area for discriminating a stable region based on the read incremental code is required. However, there is a problem in that a different data conversion circuit is required.

In this case, since the number of divisions of the additional incremental tracks is twice the number of divisions of the serial code, the pitch of the slits formed on the code plate becomes half. Generally, when the pitch of the slits is narrowed, the distance between the code plate and the detection element must be narrowed, which is mechanically limited, and it is difficult to realize a small size and high resolution.

Therefore, an object of the present invention is to provide an absolute value encoder which reads a plurality of codes from a code plate provided with a binary serial code and outputs absolute position data indicating the absolute position of the read position. In order to obtain 4N-divided absolute position data, a 4N-divided binary serial code track and a 2 × 4N-divided incremental track for boundary area discrimination are not formed on the code plate, but two different N
Forming a split binary serial code on the code plate, providing an absolute value encoder with less mechanical restrictions and no read error, and taking advantage of the characteristics of two different serial codes,
An object of the present invention is to provide an absolute value encoder capable of generating an incremental signal based on a signal detected by these two serial codes.

[0008]

A feature of the present invention for solving the above-mentioned problems is that 4N divisions in which a plurality of continuous codes are read from a code plate provided with a binary serial code and absolute position data is output. In the absolute value encoder, the code plate is provided with first and second code tracks, and first and second detectors for reading absolute position data from these code tracks are provided.

In the first code track, the reading results of consecutive K + 1 codes (in this case, integer values of 2 or more satisfying 2 ^K-1 <N ≦ 2 ^K ) have different contents, and
It is given a first N-split binary serial code created under the condition that the sum of any two read binary values will not be 2 ^{K + 1} -1.

On the other hand, on the second code track, a second N-ary binary serial code and a second N-ary divided serial signal are created by exclusive ORing the N incremental signals.
N divided binary serial codes are attached.

The first and second N-division binary serial codes thus created have the following relationship.
That is, even though they are binary serial codes of the same division, the serial codes themselves are different, and the change points of these two serial codes do not overlap each other, that is, at the change point (edge) of one serial code, The other serial code is characterized in that the signal is in the stable region.

By the way, the exclusive OR of the signals X, Y, and Z (in this specification, the operation symbol is *).
It is generally known that when X * Y = Z holds, Y * Z = X and Z * X = Y also hold. Therefore, since the second N-divided binary serial code is created by calculating the exclusive OR of the first N-divided binary serial code and the incremental signal, it is arbitrary on the first code track. To generate an incremental signal by arranging the detection element at the position of ## EQU1 ## and arranging the detection element on the second code track at a position opposite to the detection element and taking the exclusive OR of the detection signals from the respective detection elements. You can

According to the present invention, the incremental signal is output by providing the circuit means for detecting the first and second N-divided binary serial codes as described above and calculating the exclusive OR of these.

[0014]

The first and second N-divided binary serial codes are binary serial codes of the same division, but the serial codes themselves are different, and the two serial codes do not have their change points overlapping with each other. That is, at the change point (edge) of one serial code, the other serial code is in the stable region, and the exclusive logic of the corresponding codes of these two sets of N-divided binary serial codes is taken. Since the incremental signal obtained by the above method and the change point of the serial code are synchronized, detection without reading error can be performed without using a complicated conversion circuit.

Further, although the obtained absolute position data is 4N-divided, the serial code formed on the code plate only needs to be N-divided. Therefore, compared with the case where the 4N-divided serial code is formed on the code plate, It is possible to widen the distance from the detection element, and it is possible to realize a small size and high resolution.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing the configuration of a rotary type absolute value encoder 1 according to the present invention. The absolute value encoder 1 includes a code plate 2 fixed to a rotating shaft of a detection object (not shown), a light source 3 disposed on one side of the code plate 2, and a code plate 2 for reading absolute position data. Detecting elements SA1 to SA6 for optically reading the code of the code plate 2 by receiving light from the light source 3 through a slit representing a binary cyclic serial code formed in the code plate 2 as described later. And a reader 4 having SB1 to SB5.

As shown in FIG. 2, in this embodiment, the code plate 2 is provided with a first code track T1 and a second code track T2 concentrically, and each code track T1, T2 is divided into eight equal parts.

Each of the divided segments is constructed so that the white portion (transparent portion) is "1" and the black portion (light-shielding portion) is "0" to optically display eight binary cyclic serial codes. ing. Further, since the present embodiment is a rotary type absolute value encoder, it is necessary to circulate these binary serial codes.

The first code track T1 to the attached is in which eight divisions of the code plate 2 ⁽² 2 <8 ≦ 2 ³ from K = 3) first of 2
The binary cyclic serial code FA has the following meaning: “Absolute K + 1 = 4 pieces of absolute position data represented by four codes have different contents, and the sum of arbitrary two read binary values is 2 ^{3 + 1} −.
It doesn't become 1. An example created under the condition "" is [11110100] in this embodiment. This first binary cyclic serial code FA is a white portion (transparent portion) on the first code track T1 of the code plate 2 of the absolute value encoder 1.
Is formed as a slit having "1" as a black portion (light-shielding portion) of "0" (see FIG. 2).

On the other hand, in the second code track T2 of the code plate 2, the binary serial code FA obtained by exclusive ORing the first binary cyclic serial code FA and the same number of incremental codes as the second serial code FA It is designated as a binary cyclic serial code FB.

In this embodiment, a serial code [0101110] is prepared by preparing an incremental code [10101010] starting from "1" and taking the exclusive OR of this and the first binary cyclic serial code FA. As the second binary cyclic serial code FB.

When the "0" start incremental code is used, the result of [10100001] is obtained, but even if this is used, there is no problem at all.

First and second binary cyclic serial codes FA, F
B is arranged on each of the code tracks T1 and T2 in the following correspondence relationship (see FIG. 2). T1 (FA) 11110101 T2 (FB) 010111110

The reading device 4 comprises detection elements SA1 to SA6 and detection elements SB1 to SB5, and each detection element SA1 to SA6 for reading the code of the first code track T1.
Are arranged along the first code track T1 as shown in FIG. Here, the detection elements SA1, SA2, SA
4, the output from SA6 is used as a signal forming the first absolute position data. On the other hand, the second code track T2
Each of the detection elements SB1 to SB5 for reading the code of
As shown in FIG. 2, the outputs from the detection elements SB1, SB2 and SB5, which are arranged along the second code track T2, are used as signals constituting the second absolute position data.

In FIG. 3, the arrangement intervals of the respective detection elements are shown in detail when the minimum reading unit of each code track is λ.

Here, a general example of the arrangement of the detection elements will be described with reference to FIGS.

[0028] Figure 4, ^K (2 ^K-1 <satisfy N ≦ 2 ^K K, K is an integer of 2 or more) indicates the minimum, ie the basic arrangement of the detection element in the case of K = 2. The detection element SA1 is arranged at an arbitrary position on the first code track T1, and the detection element SB1 is arranged on the second code track T2 facing the position.
Is arranged. Pitch λ than the detection elements SA1 and SB1
The detection elements SA2 and SB2 are arranged at positions shifted by 1/2.
The detection element S is arranged at a position further deviated from the pitch by 3 / 4λ.
A3 and SB3 are arranged. The detection elements SA4 and SB4 are arranged at a position deviated from the detection element SA4 by a pitch λ / 2, and the detection element SA5 is arranged at a position deviated by λ / 2 from the detection element SA4. That is, in this case, the first detector SA is K + 3.
= 5 detection elements SA1 to SA5, and the second detector SB is K + 2 = 4 detection elements SB1 to SB4.

Then, the detection elements SA1 to SA4 and S
B1 to SB4 are used to create two incremental signals with a phase difference λ / 4 divided into 2N pieces.
The detection elements SA1, SA3, SA5 are the first code tracks T
Absolute position data is read from the code of 1 and the detection element SB
1, SB2, SB4 are used to read the absolute position data from the code of the second code track T2.

When the value of ^K satisfying 2 ^K-1 <N ≦ 2 ^K is increased, the first code track T1 is pitched with respect to the detection element SA5 and the second code track T2 is pitched with respect to the detection element SB4. One detection element is placed at a position shifted by mλ according to the value of K.
All you have to do is to place additional pairs.

This will be described with reference to FIG. In FIG. 5, the value of m described above is 1 ≦ m and m ≦ −2 when the rightward direction is (+) and the leftward direction is (−). However,
When m = -2, the detection element groups are densely packed, and therefore it is actually preferable that m ≦ -3.

The additional arrangement of the detection elements is as follows: m = 1, 2, 3,
, Or m = −3, −4, −5, ... May be added only in one direction, but the basic element group is arranged at the center where the light amount distribution is relatively stable. Then, centering around this basic element group, m = -3, 1, -4, 2, -5, 3, ...
.. and so on, and add the added detection element
It is preferably used as a detecting element for reading the absolute position data from the code of each track.

The outputs from the detection elements arranged as shown in FIG. 2 are waveform-shaped by the waveform shaping circuit 5 shown in FIG. 1 and output as output signals DA1 to DA6 and DB1 to DB5.

FIG. 6 shows the waveform of the output signal obtained by each detecting element when the code plate 2 is rotated once.

Returning to FIG. 1, the incremental signal I
To obtain A and IB, output signals DA2 to DA5 and DB
2 to DB5 are input to a logical operation circuit 6 including Ex-OR gates G1 to G6. Ex-OR gate G1
Calculation output signals DG1 to DG4 are output from G4 to G4. From the Ex-OR gate G6, the operation output signal DG3,
Incremental signal IA is obtained in response to DG4, and E
Operation output signals DG1 and DG2 are output from the x-OR gate G5.
In response to another incremental signal IB. The waveforms of the operation output signals DG1 to DG4 and the incremental signals IA and IB are shown in FIG.

Here, if the operation of exclusive OR of α and β is generally expressed as α * β, an incremental signal DG1 divided into N = 8 by DA2 * DB2 is obtained, and DA3 * DB3 Incremental signal DG3 divided into N = 8 with a λ / 2 phase shift from DG1
It can be seen from FIG. 6 that Furthermore, DG1 * DG
With 2, the incremental signal IB (= DO5) divided into 2N = 16 is obtained.

At this time, four output signals DA2, DB
Looking at the relationship between 2, DA3, and DB3, at a change point (edge) of a certain arbitrary signal, the waveforms of the other three signals are in the stable region of "H" or "L" level. When these four signals are divided at the changing points of each signal, there is only one changing point in each divided area.

Therefore, any one of the detection elements SA2, SB2, SA3, SB3 for detecting these four signals is at the boundary between the light transmitting portion of the slit of the code plate 2 and the light blocking portion, that is, the output level is 0. Even if there is an unstable region where it cannot be determined whether it will be (L) or 1 (H), erroneous data will not be output.

Further, 2N = 1 by these four signals.
The incremental signal divided into 6 is IB (DO
Since it is 5), it is possible to perform detection without a read error by discriminating the areas of other signals by the incremental signal IB, that is, by switching according to the logic of the incremental signal IB.

A set of output signals DA1, DA2, DA4, D detected by the detection elements SA1, SA4, SA6.
A6 and another set of output signals DB1, DB2, D detected by the detection elements SB1, SB2, SB3, SB5.
A secreter 7 is provided to select either B3 or DB5 in response to the level of the incremental signal IB.

The secreter 7 includes input terminals A1 to A of the first group.
4 and the second group of input terminals B1 to B4, and the respective output signals are input to these input terminals as shown in FIG.

The secreter 7, as shown there, generally has two inputs An, Bn and a terminal G
In this configuration, four sets of selection circuits are provided which take out the input An as the output Yn when the level of the incremental signal IB applied to the input is “L” and take out the input Bn as the output Yn in the opposite case. .

From the above description, the incremental signal I
When the level of B is “L”, in each selection circuit,
Output signals DA1, DA2, DA4, DA6 input to the input terminals A1 to A4 of the first group are output terminals Y1, Y.
2, Y3, Y4 to absolute position data DO1, DO2, D
It is output as O3 and DO4. On the other hand, when the level of the incremental signal IB is "H", the output signals DB1, DB2, DB3, DB5 input to the input terminals B1 to B4 of the second group in each selection circuit are output terminals Y.
Absolute position data DO1, DO from 1, Y2, Y3, Y4
2, DO3, and DO4 are output.

Here, the output signals DA2, DB2, DB3
With respect to the relationship between the incremental signal IB and the incremental signal IB, the changing points (edges) of the output signals DA2, DB2, and DB3 coincide (synchronize) with the changing points (edge) of the incremental signal IB as described above. On the other hand, output signals DA1, DA4, D
The relationship between A6, DB1, DB5 and the incremental signal IB is that output signals DA1, DA4, DA6, DB1, D
Each change point of B5 is out of phase by λ / 4 with respect to the change point of the incremental signal IB, and in the case of the present embodiment, each change point of the output signals DA1, DA4, DA6 is
The time in FIG. 6 indicates that the incremental signal IB exists only in the region of “H” level, and the change points of the output signals DB1 and DB5 exist only in the region of the incremental signal IB of “L” level. You can see from the chart.

In this embodiment, when the incremental signal IB is at "L" level, the output signals DA1, DA4,
Since DA6 is in the stable region and the output signals DB1 and DB5 are in the stable region when the incremental signal IB is at the "H" level, the output signals DA1, DA2, DA4 and DA6 are the incremental signals when the incremental signal IB is at the "L" level. Output signal DB when IB is at "H" level
1, DB2, DB3, DB5 are selected by the selector 7 and output as absolute position data DO1 to DO4.
Here, the incremental signal IB is the absolute position data D
Used as O5, absolute position data DO1 to DO5 divided into 2N = 16 pieces are obtained.

It should be noted that which level of the incremental signal IB the signal of the input terminal of the first group or the input terminal of the second group to select is determined by the binary cyclic serial code used. The selection logic in the selector 7 may be appropriately changed according to the serial code.

Further, the following logical operation in the EX-OR gate G6, DG3 * DG4, gives an incremental signal IA divided into 2N = 16 pieces.

Since the incremental signal IA is out of phase by λ / 4 with respect to the incremental signal IB, E
4 by the operation IA * IB in the X-OR gate G7
An incremental signal DO6 divided into N = 32 is obtained. With this incremental signal DO6, the resolution of the previously obtained 2N = 16 pieces of absolute position data is set to 2
By multiplying, 4N = 32 pieces of absolute position data as shown in FIG. 7 are obtained.

Although the optical rotary encoder having a circular code plate has been described as an example in the above embodiment, a linear encoder having a linear code plate or a magnetic encoder for magnetically detecting a code is used. Of course, the present invention can be applied in the same manner.

[0050]

According to the present invention, as described above, an absolute value encoder for reading a code of a plurality of bits from a code plate provided with a binary serial code and outputting absolute position data indicating an absolute position, An absolute encoder that prevents all read absolute position data from overlapping can be easily configured, and a serial code with a resolution lower than the resolution of the obtained absolute position data can be transferred to the code plate. Since it suffices to form the encoder, the detection distance between the code plate and the detection element can be widened, and an absolute value encoder with less mechanical limitation can be realized.

Further, since the characteristics of the two sets of serial codes attached to the two tracks of the code plate are utilized to generate the incremental signal from the signals detected from these serial codes, the incremental code track is specially designed. It is also possible to realize the detection of the code attached to the track without reading errors without providing the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an absolute value encoder according to the present invention.

FIG. 2 is a diagram showing a positional relationship between a code plate and detection elements of the absolute value encoder shown in FIG.

FIG. 3 is an explanatory view showing the detection elements in a developed manner for explaining an array pattern of the detection elements on the code plate shown in FIG.

FIG. 4 is an explanatory view for explaining a basic arrangement of detection elements according to the present invention.

FIG. 5 is an explanatory diagram for explaining a general arrangement of detection elements according to the present invention.

FIG. 6 is a time chart showing the waveform of the signal of each part when the code plate of FIG. 1 is rotated once.

FIG. 7 is a diagram showing 32 pieces of absolute position data obtained in the configuration of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Absolute value encoder 2 Code board 6 Logical operation circuit 7 Selector IA, IB Incremental signal SA1-SA6, SB1-SB6 Detection element FA 1st binary cyclic series FB 2nd binary cyclic series T1 1st code track T2 second code track

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03M 1/24

Claims (1)

[Claims] 1. An absolute value encoder of 4N division, which reads a plurality of codes from a code plate provided with a binary serial code and outputs absolute position data, having a first code track and a second code track. , Under the condition that the reading results of consecutive K + 1 codes are all different in the first code track and the sum of the binary values of any two reading results is not 2 ^{K + 1} -1. The created N divisions (2 ^K-1 <N ≦ 2 ^K , K is an integer of 2 or more, N is an even number of 4 or more) are provided with the first binary serial code, and the second code track is provided with the first binary serial code. A code plate provided with an N-divided second binary serial code created by taking the exclusive OR of the binary serial code of 1 and the incremental code divided into N pieces; Absolute position data from the code track and / or the second code track. An absolute value encoder comprising: a detector means for reading the data, and a means for reading a required code from the first code track and the second code track to create an incremental signal.