JPH088491B2 - NRZ data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application
The present invention relates to an NRZ data demodulation device used in a system that transmits data using an NRZ code.

(B) Conventional technology As described on page 51 of "Mobile Communications" published by Nikkan Kogyo Shimbun on May 30, 1988.
Receiving devices that receive NRZ encoded data are known. FIG. 3 shows such an NRZ data demodulation device, which includes a high frequency amplification block (31), a frequency conversion block (32), an intermediate frequency amplification block (33), an FM detection block (34), and a low pass filter ( 35), a waveform shaping circuit (36) and a CPU (37). The CPU (37) discriminates the output pulse width of the waveform shaping circuit (36) and controls and calls the reception block based on the demodulation and demodulation signals. , Or display.

In the NRZ data receiver configured as above, the DC level of the detection output of the FM detection block (34) is affected by the fluctuation of the local oscillation frequency of the frequency conversion block (32), the characteristic fluctuation of the FM detection block (34), etc. Fluctuates. In FSK demodulation in which demodulation is performed by discriminating pulse widths, since there is a DC level, it is not possible to perform faithful demodulation by a waveform shaping circuit that simply compares the detected output with zero potential. Therefore, a waveform shaping circuit as shown in FIG. 4 is generally used.

Referring to FIG. 4, the terminal (41) receives the FM detection signal Vdet through the low pass filter (35) shown in FIG. The pin (41) and the comparator inverting the time constant circuit is between the input terminals of a resistor R ₄₁ and capacitor C ₄₁ (42) is connected. The time constant of this circuit is set relatively large because the frequency of the signal to be handled is several hundred Hz. A resistor _R42 having the same resistance value as the resistor _R41 is connected between the terminal (41) and the inverting input terminal of the comparator (42) to prevent offset. Further, the power supply terminal of the comparator (42) is grounded through a control transistor Q _41, based on battery saving signal which becomes intermittent high level of the control transistor Q ₄₁ (hereinafter, simply referred to as control signal)
To intermittent operation waveform shaping circuit by inputting a V _BS, and reduces power consumption. This control signal V
_{The BS} is also supplied to other blocks of the NRZ data receiving system.

The operation of the above-described waveform shaping circuit will be described with reference to FIG. Control signal V _BS is intermittent signal at the low level during a period III becomes a high level in the period I and II, the control signal V _BS
Becomes high level, the comparator (42) enters an operating state, the other blocks also start operating, and the FM detection signal Vdet is input to the terminal (41). Then, substantially τ (= C ₄₁ R ₄₁₎ time constant circuit when the period II to the FM detection signal Vdet average Vav the comparator from the rising of the control signal V _BS (42)
Input to the non-inverting input terminal of. Period II ends and control signal
During the period III to V _BS goes low, when charges of the capacitor C ₄₁ of the time constant circuit is resistor R _41, it is discharged through the low-pass filter (35). Therefore, in each cycle in which the control signal _VBS goes high, the comparator (42)
Performs accurate waveform shaping. Note that the FM detection signal Vdet
The waveform corresponds to that modulated at a single level. Also,
The amplitude of each waveform is arbitrarily scaled.

(C) Problem to be Solved by the Invention By the way, the charging voltage of the capacitor C ₄₁ in FIG. 4 is the average DC voltage of the input signal during normal operation, and by doing so, accurate discrimination is possible. There is. This is based on the premise that the input signal itself has almost no DC component. However, in practice, the input signal may have a DC component, in which case the circuit of FIG. 4 has a problem in that it cannot make an accurate determination. The input signal having a DC component means a case where codes of the same polarity are continuous, and indicates a case where 0s and 1s are continuous, such as "11000001111". When 0 or 1 is continuously applied to the waveform shaping circuit of FIG. 4 in this way, the charging voltage of the capacitor C ₄₁ is biased to a value corresponding to 0 or 1, which may cause misjudgment. Become. FIG. 2 shows the signal configuration of the pager. As is apparent from FIG. 2, there is no problem because 0 and 1 are repeated in the bit synchronizing signal period, but 0 and 1 may continue three times in the frame synchronizing signal period, which is a problem.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and an integrating circuit that detects an average DC voltage of detected NRZ data, an output of the NRZ data and the integrating circuit. A comparison circuit for comparing a voltage, a memory for generating stored data according to a calling signal, and a decoder for decoding an output signal of the comparison circuit and applying a calling signal to the memory according to the decoded output. In the NRZ data demodulating device including, the holding means for holding the charge of the capacitor of the integrating circuit is provided, and when the decoder detects that a synchronizing signal period for synchronizing the NRZ data has been reached, the detection output thereof It is characterized in that the holding means is operated according to the above.

(E) Operation According to the present invention, when the decoder detects that the incoming NRZ data has reached the synchronizing signal period for synchronizing, the charging voltage of the integrating circuit is changed according to the detected output. Since the data is held, it can be accurately discriminated even if data having a DC component is applied thereafter.

(F) Embodiment FIG. 1 shows an embodiment of the present invention. (1) is a V / I (voltage-current) conversion circuit for converting the output voltage of the low-pass filter (35) into a current, ( 2) is the V / I conversion circuit (1)
Capacitor for charging the output current of the device, (3) is a comparison circuit, (4) is a ROM (read only memory) that generates stored data in response to a calling signal, and (5) is the comparison circuit ( A decoder which decodes the output signal of 3) and applies a calling signal to the ROM (4) according to the decoded output, and (6) and (7) are opened / closed according to the detection output of the decoding (5). The first and second switches.

In FIG. 1, the same circuit elements as those in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, the pager signal as shown in FIG.
The V / I conversion circuit (1) is detected after being detected by the FM detection block (34) and the unwanted components removed by the low-pass filter (35).
And it is applied to the comparison circuit (3). First, during the bit synchronization signal period, the levels of 0 and 1 are repeated in sequence,
A current according to the repetition flows from the V / I conversion circuit (1) to the capacitor (2). In the initial state, the first and second switches (6) and (7) are closed. With the closing of the first switch (6), the transistor (8) is on and the V / I conversion circuit (1) is operating. Therefore, since the average level (1/2) of 0 and 1 is charged in the capacitor (2), the output (waveform shaping output) accurately level-compared is output to the output terminal of the comparison circuit (3). can get. Here, when the output is applied to the decoder (5), the decoder (5) performs the decoding, detects that 0 and 1 continue for 9 bits, and determines that it is a bit synchronization signal period. Then, the decoder (5) opens the first and second switches (6) and (7). In response to the opening of the first switch (6), the transistor (8) is turned off and the V / I conversion circuit (1) stops operating. In addition, depending on the opening of the second switch (7), V / I can be
The impedance seen from the output side of the conversion circuit (1) becomes very large and discharge is prevented. Therefore, the above-mentioned charging voltage is held in the capacitor (2) as it is. When the bit sync signal period ends, the frame sync signal period and the group designation signal period then follow, and then the data of the content to be transmitted follows, but the capacitor (2) holds the aforementioned voltage during that period. Therefore, an accurate discrimination output appears at the output terminal of the comparison circuit (3). As a result, a message or the like to be displayed can be obtained at the output terminal (9). Then, when the content to be transmitted is completed, the completion is detected by the decoder (5), and the first and second switches (6) are detected according to the detection output.
And (7) are closed to restore the initial state. By doing so, it becomes a standby state for the next reception.

Incidentally, when the second switch (7) is open, the capacitor (2) is slightly discharged (generally the base current of the transistor) to the non-inverting input terminal (+) of the comparison circuit (3). However, it is extremely small and can be retained for several tens of seconds.

(G) Effect of the Invention As described above, according to the present invention, it is possible to provide an NRZ data demodulating device capable of performing accurate waveform shaping of an input signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a signal configuration diagram of a pager, FIG. 3 is a block diagram of an NRZ data receiving system, and FIG. 4 is a circuit diagram of a conventional waveform shaping circuit. ,
5 and FIG. 5 are waveform charts for use in the explanation of FIG.

Claims (2)

[Claims] 1. An integrating circuit for detecting an average DC voltage of detected NRZ data, a comparing circuit for comparing the NRZ data with an output voltage of the integrating circuit, and data stored in response to a calling signal. A NRZ data demodulating device comprising: a memory for generating; a decoder for decoding an output signal of the comparison circuit and applying a calling signal to the memory according to the decoded output; NRZ data demodulation characterized in that holding means is provided, and when the decoder detects that a synchronization signal period for synchronizing NRZ data has come, the holding means is operated according to the detection output. apparatus. 2. The NRZ data demodulating device, wherein the synchronizing signal period is a bit synchronizing signal period that does not include a DC component.