JPH088432A - Thin film transistor - Google Patents

Abstract

PURPOSE:To provide a thin film transistor which can improve display quality of a liquid crystal panel, by eliminating irregularity of parasitic capacitance of a thin film transistor. CONSTITUTION:The channel protecting film 13' of a thin film transistor is formed only on a gate electrode 8. A source electrode 9 and a drain electrode 10 intersect only the two facing sides of a region formed by the channel protecting film 13', and do not overlap with the other sides. The source electrodes 9 and the drain electrode 10 crosswise interset the gate electrode 8. By this constitution, the value of a parasitic capacitance generated in the part where the thin film transistor is formed can be made constant.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (Thi) used in an active matrix liquid crystal display.
n Film Transistor).

[0002]

2. Description of the Related Art Thin film transistor (hereinafter referred to as TFT)
A display using an active matrix type display substrate using the OLED has been actively researched because it can obtain higher image quality than a display device using a simple matrix type display substrate.

FIG. 4 is a perspective view schematically showing a liquid crystal panel portion of a conventional active matrix liquid crystal display. In FIG. 4, 1 is a scanning line, 2 is a data line, and 3 is T.
FT, 4 are pixel electrodes for driving liquid crystal, 5 is a glass substrate, 6
Is a counter electrode made of a transparent conductive film, 7 is a counter substrate, 8 is a gate electrode connected to the scanning line 1, and 9 is a source electrode (or a drain electrode) connected to the data line 2. Source electrode), 10 is the pixel electrode 4
A drain electrode (relative to the source electrode 9) electrically connected to.

In a normally transmissive liquid crystal display device, it is necessary to transmit light from the back light source,
The pixel electrode 4 and the counter electrode 6 must be transparent conductive films. The elements of the scanning line 1, the data line 2, the TFT 3, and the pixel electrode 4 are formed by repeating thin film formation, selective etching, and the like on the glass substrate 5 on the side where these are formed.

When color display is performed on the liquid crystal panel, color display can be performed by forming a color filter corresponding to each pixel on the glass substrate 5 on the counter substrate 7. In such a liquid crystal panel, when the TFT 3 is driven according to an image signal and the voltage applied to the liquid crystal layer is changed, the transmittance of the liquid crystal panel is changed accordingly, and an image can be displayed.

Next, a channel protection type TFT of a liquid crystal panel
The manufacturing process of the array will be described with reference to the drawings. 5 is a sectional view of the manufacturing process, and FIG. 6 is a plan view thereof. In FIG. 5, 4'is an ITO (Ind
aluminum tin oxide film layer, 8'is a scanning line 1, a Cr layer to be the gate electrode 8, 11 is an insulating layer of SiNx (Si nitride film), and 12 is a-
A semiconductor layer of Si (amorphous Si), 13 is a channel protection layer of SiNx,

[0007]

[Outer 1]

(FIG. 5 (a)) The glass substrate 5 was subjected to Cr by a sputtering method.
Deposit 1000 Å of layer 8 '.

(FIG. 5 (b)) The Cr layer 8'is etched so as to leave the pattern of the scanning line 1 and the gate electrode 8 (FIG. 6).
(a)).

(FIG. 5 (c)) An ITO film layer 4'is deposited on the glass substrate 5 by DC sputtering to a thickness of 1000 liters.

(FIG. 5 (d)) The ITO film layer 4'is etched so as to leave the pattern of the pixel electrode 4 (FIG. 6 (b)).

(FIG. 5 (e)) Next, the insulating layer 1 is formed by the plasma CVD method.
1 as SiNx 4000 Å and semiconductor layer 12 as a-Si 10
00Å, 1000 Å of SiNx is deposited as the channel protection layer 13.

(FIG. 5 (f)) The channel protective layer 13 is etched by a photolithography process to form a pattern to be the channel protective film 13 '(FIG. 6 (c)).

[0014]

[Outside 2]

(FIG. 5 (h)) A hole 15 is formed in the insulating layer 11 (see FIG. 6).
(d)).

(FIG. 5 (i)) The Al layer 16 is 7000 by DC sputtering.
Å Accumulate.

(FIG. 5 (j)) The Al layer 16 is selectively etched to form the source electrode 9 and the drain electrode 10.

[0018]

[Outside 3]

After the alignment film and the liquid crystal layer are formed and sealed on the glass substrate 5 on which the TFT array is formed by the above process, the counter substrate 7 on which the black matrix, the color filter and the like are formed is adhered to the liquid crystal panel. Is completed.

More recently, in order to make the TFT 3 smaller, the channel protection film 13 'is eliminated, and the semiconductor layer 12 is patterned in the shape of the gate electrode 8 by exposure from the rear surface of the glass substrate 5. Type TFTs are being actively developed. The manufacturing process in this case is as follows. FIG. 7 is a sectional view of the manufacturing process, FIG. 8 is a plan view thereof, and 13 ″ is a channel region.

The steps up to forming the gate electrode 8 and the pixel electrode 4 on the glass substrate 5 of FIGS. 7 (a) to 7 (d) are the same as those for forming the channel protective film 13 '.

[0022]

[Outside 4]

(FIG. 7 (f)) Etching is performed by a photolithography process so as to form a pattern of the channel region 13 ″ (FIG. 8 (c)).

(FIG. 7 (g)) A hole 15 is formed in the insulating layer 11 (FIG. 8).
(d)).

(FIG. 7 (h)) 7,000 Al layer 16 was formed by DC sputtering.
Å Accumulate.

(FIG. 7 (i)) The Al layer 16 is selectively etched to form the source electrode 9 and the drain electrode 10.

[0027]

[Outside 5]

FIG. 9 is a plan view of an inverted stagger type transistor having a channel protective film 13 ', where S1 is a gate.
The GS region of the parasitic capacitance between the sources and S2 are the GD region of the parasitic capacitance between the gate and the drain. Channel protective film 1
In the structure having 3 ', the gate electrode 8, the source electrode 9 and the drain are formed by using the insulating layer 11 on the gate electrode 8 as a dielectric in the shaded portion GS region S1 and GD region S2 shown in FIG. A parasitic capacitance is formed between the electrodes 10.

The value of the parasitic capacitance is determined by the pattern of the gate electrode 8, the pattern of the channel protective film 13 'and the pattern of the source electrode 9 and the drain electrode 10. Here, the reason why this parasitic capacitance changes depending on the pattern of the channel protective film 13 'is that the channel protective film 13' acts as a conductor when the TFT 3 is in an active state.
This is because the region S1 and the GD region S2 are separated by the center of the pattern of the channel protective film 13 '.

Further, FIG. 10 shows a plan view of a thin film transistor in which a channel region 13 ″ is formed on the gate electrode 8 in a self-aligned manner by exposing from the back surface of the glass.
As shown in FIG. 10A, the value of the parasitic capacitance in the FT is the pattern of the gate electrode 8 and the source electrode 9 and the drain electrode 10.
It is determined by the pattern.

Generally, in the process of manufacturing an active matrix substrate, a patterning shift occurs between layers. For example, as shown in FIG. 9 (b), when a shift occurs in the arrow direction, the GS region S1 decreases and the GD region S2 decreases.
Will increase. On the contrary, when the shift occurs, the GS region S1 increases and the GD region S2 decreases. That is, the parasitic capacitance of the TFT 3 changes due to the deviation of each pattern. Similarly, also in the self-aligned TFT, the GS region S1 increases and the GD region S2 decreases when a shift occurs in the arrow direction as shown in FIG. 10B.

The main causes of these patterning deviations are alignment misalignment during exposure and distortion of the photomask itself. To solve this problem
As disclosed in Japanese Laid-Open Patent Publication No. 267617, there is proposed a structure in which the TFT 3 has a U-shape so as to suppress variations in parasitic capacitance within a substrate or between substrates.

[0033]

However, in the TFT having such a structure, when the above-mentioned variation of the parasitic capacitance occurs in the same substrate, for example, when the display pixel is divided and exposed by the stepper, FIG. As shown in, the exposure boundary is recognized and the display quality is degraded. Further, when the parasitic capacitance varies between the substrates, the circuit constant cannot be made constant, and the display quality varies, which causes a deterioration in image quality.

The main causes of these pattern shifts are alignment shifts during exposure and distortion of the photomask itself. To solve this problem, a structure in which the shape of the TFT is U-shaped has been proposed. However, when such a structure is adopted, the area occupied by the TFT in one pixel becomes large and the aperture ratio is lowered. There was a problem of inviting.

The present invention solves the above-mentioned problems of the prior art by eliminating variations in the parasitic capacitance of TFTs, improving display quality, and achieving a large aperture ratio of a liquid crystal panel.
The purpose is to provide FT.

[0036]

To achieve this object, the present invention provides a gate electrode patterned to form a scan electrode under a channel region of a thin film transistor, and a transparent conductive film for driving a liquid crystal. In a thin film transistor having a source electrode (or a drain electrode) for transmitting an image signal to the pixel electrode and a drain electrode (or a source electrode) connected to the pixel electrode, the channel protection film of the thin film transistor is on the gate electrode. The source electrode and the drain electrode cross over only two opposing sides of the region where the channel protective film is formed and do not overlap on the other side, and the source electrode and the drain electrode Both the electrodes have a cross-shaped structure with the gate electrode in a cross shape. Characterize.

In addition, a gate electrode patterned to form a scanning electrode below the channel region of the thin film transistor, and the source electrode (or drain) for transmitting an image signal to a pixel electrode formed of a transparent conductive film for driving liquid crystal. Electrode) and a drain electrode (or source electrode) connected to the pixel electrode, and the semiconductor layer forming the channel region is self-aligned on the gate electrode by exposure from the back surface of the insulating substrate. In the thin film transistor to be formed, both the source electrode and the drain electrode have a cross-shaped crossover structure on the channel region.

[0038]

According to the above structure, by adopting the crossover structure in which the portion of the gate electrode of the TFT and the source electrode and the drain electrode are all cross-shaped, variations in parasitic capacitance due to mask misalignment occur. Disappears.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a channel protection type T according to the first embodiment.
The plane structure figure of FT is shown. Moreover, the same reference numerals are given to those having the same action and effect described in each drawing of the conventional example, and the detailed description thereof will be omitted.

The first embodiment is an example of a channel protection type TFT 3 in which a protection film is left on the channel of the TFT 3. In FIG. 1, C1 and C2 are the source electrode 9 and FIG.
Shown in (k) are contact portions of the semiconductor layer 12, C3 and C4 are contact portions between the drain electrode 10 and the semiconductor layer 12, and C5 is contact portions between the channel protective film 13 ', the source electrode 9 and the drain electrode 10. Figure 2 shows the TFT including the parasitic capacitance
3 shows an equivalent circuit of 3.

The manufacturing process of the liquid crystal panel is the same as the conventional process. The channel protective film 13 'of the TFT 3 is formed only on the gate electrode 8, and the source electrode 9 and the drain electrode 10 form the channel protective film 13'. Crossing over only the two opposite sides of the existing region, not overlapping on the other side, and the source electrode 9 and the drain electrode.
Together with 10, the gate electrode 8 and the gate electrode 8 are crossed in a cross shape.

With the above structure, the value of the parasitic capacitance generated in the TFT 3 portion can be made constant regardless of the mask alignment accuracy. Explaining the reason for this, in FIG. 1A, the gate-source parasitic capacitance Cgs shown in FIG. 2 is the region indicated by the shaded GS region S1. Similarly, the parasitic capacitance Cgd between the gate and the drain is the region shown by the shaded GD region S2.

By adopting this structure, the regions C1 to C5 do not change even when the mask misalignment occurs in the direction of the arrow as shown in FIGS. 1B and 1D when the active matrix substrate is manufactured. , Gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgs
gd is always the GS area S1 and GD area S2 in the shaded area,
It is always a constant value regardless of the direction and amount of deviation.

From the above, when the active matrix substrate is manufactured, the line of the connecting portion at the boundary of the exposure shot area, which is caused by the accuracy of the photomask or the stepper, disappears, and a liquid crystal panel with high display quality is realized. be able to.

Next, a second embodiment will be described with reference to the drawings. Example 2 is a case of a self-aligned TFT 3 in which the pattern of the semiconductor layer 12 is formed in the same shape as the shape of the gate electrode 8 by exposure from the back surface of the insulating substrate in the manufacturing process of the liquid crystal panel. FIG. 3 is a plan view of the self-aligned TFT 3 of the second embodiment.

Here, the difference from the conventional example is that, as a pattern of the substrate design of the TFT array, as shown in FIG. 3A, the gate electrode 8, the source electrode 9, the gate electrode 8 and the drain on the channel region 13 ″ are formed. The electrode 10 is designed so as to have a cross-shaped crossover structure.In this case, the parasitic capacitance Cgs between the gate and the source is the GS region S1 shown by the hatched portion. The parasitic capacitance Cgd becomes the GD region S2 shown by the hatched portion.

Therefore, even if the mask misalignment occurs in the direction of the arrow as shown in FIG. 3B, the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd are always GS in the shaded area. The regions S1 and GD are regions S2, which are always constant values regardless of the direction and amount. As a result, similarly to the first embodiment, the line of the joining portion at the boundary of the exposure shot area disappears, and a liquid crystal panel with high display quality can be realized.

[0049]

As described above, according to the present invention,
In the case of the channel protection type TFT in which the channel protection film is formed on the gate electrode, the source electrode and the drain electrode cross over only two opposing sides of the region formed by the channel protection film and overlap on the other side. In addition, both the source electrode and the drain electrode cross over with the gate electrode in a cross shape. With the above configuration, the value of the parasitic capacitance generated in the TFT section can be made constant regardless of the mask alignment accuracy.

Also in the case of a self-aligned TFT, if the gate electrode and the source electrode and the gate electrode and the drain electrode both have a cross-shaped crossover structure on the channel region, the value of the parasitic capacitance shifts from the mask alignment. Even if the error occurs, the value is always constant regardless of the direction and amount of the deviation.

From the above, it is possible to obtain a liquid crystal panel using the TFT of the present invention, which eliminates the dispersion of the parasitic capacitance, improves the display quality, and has a large aperture ratio.

[Brief description of drawings]

FIG. 1 is a plan view of a channel protection type thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a thin film transistor including a parasitic capacitance.

FIG. 3 is a plan view of a self-aligned thin film transistor according to a second embodiment of the present invention.

FIG. 4 is a perspective view schematically showing a liquid crystal panel section of a conventional active matrix type liquid crystal display device.

FIG. 5 is a cross-sectional view showing a manufacturing process of a channel protection type thin film transistor array of a conventional liquid crystal panel.

FIG. 6 is a plan view showing a manufacturing process of a channel protection type thin film transistor array of a conventional liquid crystal panel.

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional self-aligned thin film transistor array.

FIG. 8 is a plan view showing a manufacturing process of a conventional self-aligned thin film transistor array.

FIG. 9 is a plan view of a conventional channel protection type thin film transistor.

FIG. 10 is a plan view of a conventional self-aligned thin film transistor.

FIG. 11 is a diagram showing a boundary line at an exposure boundary that occurs when the parasitic capacitance varies in the substrate.

[Explanation of symbols]

1 ... Scan line, 2 ... Data line, 3 ... TFT (thin film transistor), 4 ... Pixel electrode, 4 '... ITO film layer,
5 ... Glass substrate, 6 ... Counter electrode, 7 ... Counter substrate,
8 ... Gate electrode, 8 '... Cr layer, 9 ... Source electrode,
10 ... Drain electrode, 11 ... Insulating layer, 12 ... Semiconductor layer,
13 ... Channel protective layer, 13 '... Channel protective film,
13 ″ ... channel region, 14 ... ohmic layer, 15 ...
Hole, 16 ... Al layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mutsumi Kimura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

[Claims] 1. A gate electrode patterned to form a scan electrode below a channel region of a thin film transistor, and a source electrode (or drain electrode) for transmitting an image signal to a pixel electrode formed of a transparent conductive film for driving liquid crystals. ) And a drain electrode (or source electrode) connected to the pixel electrode, a channel protective film of the thin film transistor is formed only on the gate electrode, and the source electrode and the drain electrode are the channel protective film. A structure in which only the two opposite sides of the region where is formed do not overlap with the other sides and do not overlap with the other side, and both the source electrode and the drain electrode are cross-shaped in a cross shape with the gate electrode. A thin film transistor having. 2. A source electrode (or drain electrode) for transmitting an image signal to a gate electrode patterned to form a scanning electrode below a channel region of a thin film transistor, and a pixel electrode formed of a transparent conductive film for driving liquid crystal. ) And a drain electrode (or source electrode) connected to the pixel electrode and forming the channel region in a self-aligned manner on the gate electrode by exposure from the back surface of the insulating substrate. In the thin film transistor described above, the source electrode and the drain electrode both have a cross-shaped crossover structure on the channel region.