JPH0884153A - Communication bus system and master station used therefor - Google Patents

Abstract

PURPOSE: To provide a communication bus system, with which problems caused by a chain lock of slave stations are reduced, and a master station to be used for the same. CONSTITUTION: A master station transmits a message composed of frame units by winning a selection, and this message is formatted so as to contain a chain lock signal and a release signal for respectively performing the chain lock and release of slave stations addressed in the duration time of plural frames consisting of the message. Thus, access from other master stations to a chain locked slave station in this duration time is blocked. Further, other master station executes a 1st sequence for detecting blocking and performing comparatively frequent retry within a time sufficiently shorter than the standard longest value of duration time as a whole. Next, a 2nd sequence is continued as needed for performing comparatively non-frequent retry within a time longer than the standard longest duration time as a whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention comprises a master station and slave stations, all master stations comprising frame-based selection means, selection result detection means, and frame format means. Formatting means sends a message composed in units of frames by winning the selection, said message each locking and releasing a slave station addressed for the duration of a plurality of frames constituting the message. It relates to a multi-station communication bus system in which the access to the locked slave station by another master station is at least individually blocked during the duration by including the locking and releasing cues to be made. is there.

[0002]

2. Description of the Related Art Generally, in such a communication system, the maximum allowable frame length is limited, so that individual master stations cannot occupy the entire system for more than a proper period. As a result, if a master station wishes to send a long message to a slave station, it must be done in each successive frame that makes up this message as a whole. In such a case, the master station should prevent addressed slave stations from being addressed by other master stations during successive frames of this message. To this end, Applicant's US Pat.
937816, 5128936 and 5249.
A locking mechanism as described in No. 182 has been proposed. In one embodiment of this known locking mechanism, the maximum locking period is 300 milliseconds. There is a problem that another master station will not succeed even if it tries to transmit a frame to the slave station within this period. To solve this, this second master station can repeatedly try to transmit.

[0003]

Nevertheless, access should be made as quickly as possible, whether or not the slave station is locked. In this respect,
Even if the slave is not locked, access by other master stations may be temporarily blocked, for example, because the slave station's receive buffer remains filled with previously received messages. Of course. Although less frequent, such blockages can result from electrical disturbances and transient errors.

It is an object of the present invention to allow a master station to access a slave station as quickly as possible, whether or not the slave station is temporarily locked to another master station. It is to provide a bus system.

[0005]

SUMMARY OF THE INVENTION The present invention provides that the other master station retries relatively frequently within an overall time that is well below the standard maximum of the duration. The first sequence followed by a second sequence that retries relatively infrequently within an overall time longer than a typical maximum of the duration is blocked. It is characterized by having a sequence means for detecting and executing. Attempts are made relatively often throughout the first sequence, and if there is a brief error condition, regardless of whether the slave station is locked or not,
The actual access to the slave station is only slightly delayed. Attempts are made relatively discretely through the second sequence to allow access after the locked state ends. If a temporary error condition occurs, the same error will not appear in successive attempts of the second sequence, as there is a relatively long period between successive attempts of the second sequence. In essence, the present invention is a compromise between more frequent attempts to improve functionality and less frequent attempts that are simple in procedure and reduce the load on the communication bus and the stations that belong to it.

Preferably, when the other master station detects that the address sent to the slave station has not been acknowledged, it performs a third sequence of attempting to address the slave station almost instantaneously. However, it has a second sequence means for accessing the slave station only when the approval of the address is detected. In some situations, a slave may not approve its address because it exists for a very short time.
Another possible cause is that the station is actually absent. In both cases, even if the reasons are different,
Retries almost instantaneously at the slave address level further speeds up the overall operation.
In the first case, the cause will soon be over and access will be successful. In the second case, the master station can perform other operations.

The invention also relates to a master station used in a communication bus system of the kind mentioned above.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a schematic of a single channel communication bus system. The line 20 represents a channel and is, for example, a stranded conductor. Three stations 22, 24 and 26 are provided, each of which has an interface circuit 28, 3 respectively.
0 and 32 respectively. There are many different station configurations. This device can be simple or complex,
For example, television receiver, washing machine, microwave oven, centralized timer, temperature / solar radiation sensor, lighting (secondary)
It can be a system. One device acts as the master station for the bus and another device acts as the slave station. Some devices act as transmitters of data and some act as receivers. The operations described below are performed on the communication bus system and executed by the interface circuit.

FIG. 2 shows the communication operation at the frame level. In this figure, the time axis is shown as a curve 40 along which the bit cells are arranged adjacently. Reference numeral 42 indicates a start bit. Reference numeral 44 relates to a mode indicator showing the bit rate at which the data is transmitted. It consists of a maximum of 3 bits. The number of standard transmission frequencies is predetermined. Reference numeral 46 indicates the address of the master station. This address consists of 12 bits followed by a parity bit P. The selection operation is performed on the mode display and the master station address. As for mode selection, the lowest (slowest) mode wins. In terms of address, the station with the highest priority wins. The mode display and master station address together constitute a priority signal. Only 1 after sending master address
One master station remains. This station then sends the slave station address 48. This address consists of 12 address bits, one parity bit P, and a blank for the address acknowledge bit A. If the slave station sees an address to itself, it sends an address acknowledge bit in block A. If this address acknowledge bit is not received, the intended slave station is either absent or not working, or the address has an incorrect parity bit. In such a case, the frame shown in FIG.
Stop immediately. If the approval by the slave station is correct,
The master station transmits the control signal 50. This signal is 4
Control bits, one parity bit P, and a blank for the control acknowledge bit A. The processing of the P and A bits is performed in the same manner as the slave station address. If the control acknowledge bit does not appear, the frame will stop immediately. If the approval by the slave station is correct, a data byte is sent (52). A description will be given based on the master transmitting station. The data byte consists of 8 bits, a "final" data byte signal (EOD), a parity bit P, and a blank for the data acknowledge bit A. The EOD cue indicates whether the sending station considers the byte as the last byte or non-final byte of the message. The maximum frame length is 2 bytes in mode 0 and mode 1
Is 32 bytes from (master station) or 16 bytes from (slave station), 128 bytes from (master station) or 64 bytes from (slave station) in mode 2, but shorter than these Message is also possible, of course. The parity bit P is also
It is also determined based on the EOD bit. If no data acknowledge bit is received, parity error, control signal 50
There are various possible causes, such as a slave station that has stopped due to the acceptance of, or that the slave station cannot receive the data bytes and store them in a buffer, for example, because the data processing took too long. In all of these cases, the master station is set to the repeat state. In this state, the data bytes containing EOD, P, A are repeated until the last data acknowledge bit is received. At that time, if the data byte is not the last byte, the repeat state is aborted and the next data byte (eg 54) is sent. On the other hand, if this data byte is the last data byte, then the frame and message are finished. After that, a new message / frame can be started. Each time you send a data byte,
Increase the counter position. If the counter reaches the maximum frame length or the message is complete, the "last" data byte is indicated (the first of the two possible limits is determined). The frame ends after the "last" byte. If the data acknowledge bit is not received correctly after the "final" byte, the "final" byte is repeated until the defined frame length is met. If the message is not yet complete when the maximum frame length is reached, a new frame is started. The first data byte is selected as the first data byte of the message that has not yet been sent, or as the data byte for which the correct data acknowledgment byte has not yet been received. It therefore does not include the double transmission of data bytes that have already been successfully transmitted. That is, if a "locking" mechanism is used at this point, the slave can be reserved for the current transmission. This will be described in detail below. This locking mechanism allows another master station with a higher priority to occupy the entire bus at the same time, but cannot access a slave station that is already locked. With this configuration, the procedure at the slave station is simplified.

The master station can set or release the lock flag in the slave by a predetermined control signal instructing the slave to follow only the master station. The slave station is released by the master station sending a 1-byte data frame containing the release instruction. The lock flag should be set / unset by the slave after at least one byte of the associated frame has been successfully transmitted / communicated.

The slave address acknowledge bit is a mode (speed) of the frame when the slave is absent.
Cannot be processed, if there is a parity error in the master address and / or the slave address, or if the timing is incorrect and a bus error occurs, resulting in a synchronization or parity error. Not given to. Master is
Repeat the frame as much as possible in the lower mode,
Respond to the disapproval bit of the address by requesting (as repeatedly as possible) the status for the slave in mode O. The highest mode in which the slave can operate is obtained from the status. As a result, the message is repeated in the highest feasible mode. If the transmission repeatedly stops at the slave address disapproval bit, then the slave must be determined to be absent. In this case, further iterations are meaningless.

The control acknowledge bit is not provided in the case of a parity error, a timing error, or if the slave cannot perform the required function. The master station can react in the first case by repeating the message. If no further control acknowledge bit is received, the slave station requests the master station to determine why this acknowledge bit was not received.

The data disapproval bit occurs in the case of a parity error, a timing error, or when the receive buffer is completely full. If it is due to a parity error, or the buffer is completely full, this byte is repeated as much as possible until the byte is acknowledged or the frame length is exhausted. If the transmission of bytes within this frame does not end, a new frame is started for this byte.

The following control signals are defined. HEX0 (0000): Read the status of the interface circuit of the slave station. If the acknowledge signal does not follow after this operation, it is determined that the interface circuit of the slave station is incomplete. However, repeated operations can be performed. If an acknowledge signal is received, the slave station consequently outputs a data byte whose status is indicated. HEX2 (0010): Read status and supply lock signal to slave station. If the slave station is locked by another master station, this situation is signaled in a data byte and this requesting master station must try again. HEX3 (0011): Reads data and supplies a lock signal to the slave station. If no answer is received, the status is queried as shown below. Bit 0 = 0: The slave station's transmit buffer is empty.
This is signaled to the control system. Bit 2 = 1: Slave station is locked by another master station. The control system receives a retry command. Bit 4 = 0: Slave station cannot send data. This is signaled to the control system. Bit 0,
In all cases other than 2 and 4, start a new frame with the same control code. HEX4 (0100): Read the lower 2 bits of the 4-bit address where the slave station is locked. If the slave station is not locked, this is signaled to the master's control system by a disapproval bit. HEX5 (0101): The most significant bit of the 4-bit address is controlled in the same manner as HEX4 (0100). HEX6 (0110): Read slave status,
release. If the slave station is locked by another master station, this is signaled by the disapproval bit and the master aborts its attempt. HEX7 (0111): Read the data and release it. Corresponds to code 0011, except for release. HEX8 (1000): Write a hold request. If the disapproval bit occurs, a question is asked about the slave station's attributes / status. The latter is interpreted as follows. Bit 1 = 1: The slave receive buffer is not empty. This is signaled to the master control system. Bit 2 = 1: Same as above Bit 3 = 0: Since the slave has no memory,
Unable to respond to attribute / status requirements. If none of the three bits have an answer, make a new attempt. HEX A (1010): Write command and lock.
As a result, the status is read and, in the case of the disapproval bit, it is interpreted as follows. Same for bits 1 and 2. If none of these bits have an answer, make a new attempt. HEX B (1011): Write data and lock. As a result, the status is read, and in the case of the disapproval bit, it is interpreted in the same manner as HEX A. HEX E (1110): Write instruction and release.
Others are the same as A. HEX F (1111): Write data and release. Others are the same as A.

At the end of each frame, the transmitting station (slave station or master station) checks to see if all required bytes have been transmitted. If not, the master station starts a new frame and the transmitting station stores the remaining bytes in the local transmit buffer.

FIG. 3 shows an embodiment of the interface circuit. The circuit (60) includes connection terminals for the following devices. Seen clockwise from the oscillator (6 MHz), power supply VCC, ground GND, test control Test, 8-bit data for local control system, and sync (strobe) pin

[Outer 1] And read / write control

[Outside 2] And the choice between address and data

[Outside 3] , An interrupt signal Int, three preset address bits (A0, A1, A2), two lines for TTL level data, and a two-stranded wire (D ² B: Domestic) for single-channel communication as described above. Digital Bus)
And with. The element 62 includes a clock and a control portion (POR = P
power-On Reset). "Chip ready" signal, POR signal and clock signals 0P, 1P
Occurs here. The "chip ready" signal indicates that the circuit is operational again after power up or reset.

Block 64 is the circuit that filters the signal on the D ² B and TTL lines and detects and controls this signal. The data contents of the signals on the D ² B and TTL lines are the same except for the electrical differences as follows. While TTL is unidirectional, D ² B is bidirectional and the voltage levels are different. On line 65, the line bit is transmitted at the TTL level. Block 66
At, the conversion between line bits and logic bits is performed. Block 67 constitutes two unidirectional latch circuits between blocks 66 and 68. Line 69
Sends a signal that activates the next bit. Block 68 constitutes the heart of the interface circuit. Here the parity bits are formed, the acceptance bits are detected, and the various control and status bits, if any, are parsed or stored for the query. In addition, information is exchanged with the control system and interaction with the RAM buffer 70 is configured. The buffer 70 has 8-bit data.
The number of bytes is determined by the application. The address appears on line 71. Block 72 is a data gate having a data width of 8 bits and connected to a local control system (not shown). Signal mode 0P and 1P
Is a second clock signal having the same frequency as 0P and 1P or a frequency of 1/4 depending on the operating mode on the external bus D ² B. Line 76 controls the switching of the clock to bit levels for various bit lengths, which is the start bit, mode / address /
The control bits and the data bits do not have to be the same. Line 75 has a similar function at the frame level. Line 77 is the grant line (EN) and lines 78 and 79 provide synchronous coupling.

In a simple embodiment, the circuit is in mode 0.
And 1 and is also suitable for master operation in addition to slave operation. The circuit is initialized when a reset signal (power-on-reset, POR) is generated. The microprocessor uses the circuit address given to the interface circuit as
It can be created by loading some freely accessible registers. In addition, some flag bits are set that indicate the function of the application (if local memory is present and the slave station can also act as a transmitter). The signal POR also acts as an interrupt signal to the local control system. The bus status of the slave part of the circuit is stored in the slave status register. If the circuit is locked by another station,
The address of the locked station is stored in the lock address register. In order for the circuit to operate as a master station, the control circuit needs to provide the following information.
In the case of a slave station address, control code, and write operation, a data byte to send to load into the master station buffer, a mode signal indicating the line mode to be used, and in the master station instruction register. Master station request signal loaded.

As a result, the station initiates a message and performs the associated selection procedure if necessary. When the frame ends after being selected, an interrupt signal (INT) to the local control system is given. As a result, the local control system can read the cause of the interrupt signal (master interrupt, slave transmitter interrupt or receiver interrupt) in the interrupt register. The master status register contains a predetermined number of acknowledge bits to indicate whether the message was successful. Therefore, this master status register operates as a counter. Further, in the case of a read operation, after the interrupt signal, the master buffer will contain the received data. The interrupt register is reset after being read. this is,
This is done by a complete write operation in the register.

Substantially similar operations are performed for the slave receiver function. In this case, a predetermined number of acknowledge bits is stored in the slave receiver register. When the slave receive buffer is read, the slave receiver instruction register is filled with the information 00 (HEX).

FIG. 4 is a flow chart of a retry procedure for frame transmission by the master station. In this example,
The maximum locking period is 300 milliseconds. Block 10
0 indicates the start of the transmission means, and it is assumed that the station knows which data is transmitted to which slave station. This procedure may be wholly or partly associated with the slave transmitter station situation. At block 102, the retry parameter is reset to zero. At block 104, the master attempts to transmit the frame. This block may include a selection procedure. If the start and selection for that frame is successful for the master station, proceed to block 106. At block 106, it is determined if the slave station is transmitting an acknowledgment for its own address and a control code CC indicating that the master station requires the slave to have some mode of operation. There are various possibilities. For one, the control code may simply request the slave to report its operating status, which does not prevent the operation implying the locked status itself. Other control codes require extensive data conversion that is not allowed by locked slaves. Generally, if approved, the system will block 10.
Proceed to 8, where the operation is performed and finally complete. If not approved at block 106, then the retry parameters are tested at block 110. If this value is less than or equal to 2, then block 116 is performed with low latency and the parameter is incremented at block 120. 104,
The loop of 106, 110, 116, 120 is repeated up to 3 times. If the parameter value reaches 3, the system proceeds to blocks 112, 118 which require a long latency.
This latter loop also repeats up to 3 times. Finally, if the parameter value reaches 6, the system admits failure and proceeds to block 114. The total time required to perform this procedure is on the order of 324 milliseconds.

In summary, there are three categories of errors. ● Cause: Temporary transmission error, eg electrical disturbance. Timing Rule: This error is absent as it will last a very short time. ● Cause: The slave receive buffer is full. Timing Rule: A slave must process its receive buffer chip within 25 ms. Master procedure: Add 3 × 8 msec. Since the transmission time of the frame exceeds 25 msec, retransmission is performed 3 times at intervals of at least 8 msec. ● Cause: The slave is locked by another master. Timing Rule: The master cannot keep the slave lock for more than 300 ms. That is, if this error occurs, the slave will be released 300 milliseconds later.

In addition, there is a procedure for the slave to release itself in situations where the master does not release the slave due to internal errors. This is shown in Figures 5 and 6. The flow chart of FIG. 5 shows block 1 for receiving a frame
Starts from 30. Thereafter, at block 132, the frame present in the receive buffer is duplicated to the local processing unit at this station. At block 134, it is detected whether the acquired frame contains a release code. If this frame contains a release signal (Y),
At block 136, the release timer is stopped. If no release signal is found (N), the release timer is restarted at block 138. In each of these individual configurations, each frame is either released (= last frame) or locked (=
Either non-final frame). In either case, block 140 processes the frame or message. At block 142, the procedure ends. In FIG. 6 the self-release procedure by the locked station is shown. At block 144, the expiration of the release timer is detected after 300 milliseconds. Block 146
At, the slave is actually released. Block 14
At 8, the procedure ends. Of course, a master station that does not know this can relock the slave station in the next frame of the message that has not yet finished.

FIG. 7 shows a modification of the flowchart of the retry means of FIG. Corresponding blocks are generally denoted by the same reference numerals. The different points are as follows. In block 101, two retry parameters
Reset both Retry and Retry1 to 0. The former has already been described with reference to FIG. Block 1
At 03, check if the slave station has sent an acknowledgment for its own address. If not, the master station performs a test on the value of parameter Retry1 at block 109. If the number of transmissions is less than or equal to 2, the value of parameter Retry1 is incremented by 1 in block 113, and then the system returns to block 104. When the parameter Retry1 reaches the value 3, the system proceeds to block 111 and the master station takes another action. As mentioned above, this loop executes almost instantly. This means that, in any way, its iteration time is significantly shorter than the iteration time of the next slow loop and can be well determined within block 116. The delay can be on the order of microseconds, but may be a few milliseconds.

If the approval is confirmed in block 103, the parameter Retry1 is reset to 0 again in block 105. By doing so, it is possible to avoid the case where the slave address is accidentally failed once again after passing through the block 113 three times and becoming Y in the block 103, and immediately ending. it can. However, block 10
5 may be omitted. At block 107, a test is performed on the control code CC. In both possible outcomes, the system continues as in FIG.

[Brief description of drawings]

FIG. 1 is a diagram showing the general structure of a single channel communication bus system.

FIG. 2 is a diagram showing a configuration of a communication operation.

FIG. 3 is a diagram showing an embodiment of an interface circuit according to the present invention.

FIG. 4 is a flow chart of a retry procedure according to the present invention.

FIG. 5 is a flowchart of a release procedure according to the present invention.

FIG. 6 is a flowchart of a second release procedure according to the present invention.

FIG. 7 is a flow chart of an improved retry procedure according to the present invention.

[Explanation of symbols]

 20 channels 22, 24, 26 stations 28, 30, 32, 60 interface circuit 70 RAM buffer

Claims (6)

[Claims] 1. A master station and slave stations, all master stations comprising frame-based selection means, selection result detection means, and frame format means, said frame format means comprising said selection. Send a message composed of frames by winning
Another master station during said duration by said message including a locking and releasing signal respectively for locking and releasing the slave station addressed for the duration of the frames constituting the message. In a multi-station communication bus system, in which access to a locked slave station is at least individually blocked by the other master station, the total master time is more than the standard maximum value of the duration. A first sequence of relatively frequent retries within a very short period of time, followed by a relatively infrequent retry of the total time within a period longer than the standard maximum of the duration. 2. The multi-station communication bus system, comprising: a sequence means for executing the sequence 2 and detecting the blocked state. 2. The communication bus system according to claim 1, wherein when the another master station detects that the address transmitted to the slave station is not approved,
A second sequence of performing a third sequence of attempting to address the slave station almost instantly, and accessing the slave station only when an acknowledgment of the address is detected;
A multi-station communication bus system having the sequence means of. 3. The communication bus system according to claim 1, wherein at least one of the first and second sequences makes at least three consecutive attempts. 4. The communication bus system according to claim 1, 2 or 3, wherein the bus is a D2B bus. 5. A master station and a slave station, all master stations comprising frame-based selection means, selection result detection means, and frame format means, said frame format means comprising said selection. Send a message composed of frames by winning
Another master station during said duration by said message including a locking and releasing signal respectively for locking and releasing the slave station addressed for the duration of the frames constituting the message. In a multi-station communication bus system, in which access to a locked slave station is at least individually blocked by the other master station, the total master time is more than the standard maximum value of the duration. A first sequence of relatively frequent retries within a very short period of time, followed by a relatively infrequent retry of the total time within a period longer than the standard maximum of the duration. Master station used in a multi-station communication bus system, characterized in that the master station has sequence means for detecting and executing the sequence 2 6. The master station according to claim 5, wherein when detecting that the address transmitted to the slave station is not approved, a third sequence is performed in which an attempt to address the slave station is made almost instantaneously. Run and
A master station having second sequence means for accessing the slave station only when the approval of the address is detected.