JPH0883884A - Three-dimensional semiconductor integrated circuit and fabrication therefor - Google Patents
Three-dimensional semiconductor integrated circuit and fabrication thereforInfo
- Publication number
- JPH0883884A JPH0883884A JP21738494A JP21738494A JPH0883884A JP H0883884 A JPH0883884 A JP H0883884A JP 21738494 A JP21738494 A JP 21738494A JP 21738494 A JP21738494 A JP 21738494A JP H0883884 A JPH0883884 A JP H0883884A
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- Prior art keywords
- integrated circuit
- semiconductor integrated
- semiconductor
- circuit
- semiconductor module
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＬＳＩ（ｌａｒｇｅ
ｓｃａｌｅ ｉｎｔｅｇｒａｔｉｏｎ）等の三次元半導
体集積回路およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI (large size).
The present invention relates to a three-dimensional semiconductor integrated circuit such as a scale integration) and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】ＬＳＩ等の半導体集積回路は、シリコン
基板に多数の素子、およびそれら素子の所要のものどう
しを接続する配線部を積層することにより構成される。
このような半導体集積回路の一例を図１４に示す。2. Description of the Related Art A semiconductor integrated circuit such as an LSI is constructed by stacking a large number of elements on a silicon substrate and wiring portions for connecting required elements of these elements.
An example of such a semiconductor integrated circuit is shown in FIG.
【０００３】図１４は従来の半導体集積回路の断面図で
ある。この図で、１は半導体集積回路を示す。半導体集
積回路１は、Ｓｉ基板２、その上に積層された複数の素
子層３、所要の電気的接続を行なう配線部４、４ａ、４
ｂ、および絶縁層５で構成されている。なお、この図お
よび以下に示す全ての図において、配線部にはハッチン
グが施されている。このようにＳｉ基板２の上に積層さ
れた回路面は、回路が多層化すると表面に凹凸が生じる
ので、さらにその上に回路を積層しようとする場合、露
光光の焦点を合わせることが困難になり、リソグラフィ
ーの技術を使用できない。このため、そのような積層を
行なう場合には、図１５に示す手段が採用される。FIG. 14 is a sectional view of a conventional semiconductor integrated circuit. In this figure, 1 indicates a semiconductor integrated circuit. The semiconductor integrated circuit 1 includes a Si substrate 2, a plurality of element layers 3 stacked on the Si substrate 2, and wiring portions 4, 4a, 4 for performing required electrical connections.
b and the insulating layer 5. In addition, in this figure and all the figures shown below, the wiring portion is hatched. In this way, the circuit surface laminated on the Si substrate 2 has irregularities on the surface when the circuit is multi-layered. Therefore, when the circuit is further laminated on it, it is difficult to focus the exposure light. And the technology of lithography cannot be used. Therefore, when such stacking is performed, the means shown in FIG. 15 is adopted.
【０００４】図１５は従来の半導体集積回路の断面図で
ある。この図で、図１４に示す部分と同一部分には同一
符号が付してある。半導体集積回路１の上に絶縁層６が
施され、その表面を平坦にしたうえ、絶縁層６の表面上
に他の半導体集積回路７がリソグラフィー技術により積
層される。９はスルーホール（例えば直径１０μｍ）で
あり、このスルーホール８の内面に導体物質層を付着さ
せることにより、半導体積層回路１の配線部４ａと半導
体積層回路７の配線部４ｃとの所要の接続、および半導
体積層回路１の配線部４ｂと半導体積層回路７の配線部
４ｄとの所要の接続がなされる。FIG. 15 is a sectional view of a conventional semiconductor integrated circuit. In this figure, the same parts as those shown in FIG. 14 are designated by the same reference numerals. An insulating layer 6 is provided on the semiconductor integrated circuit 1, the surface is made flat, and another semiconductor integrated circuit 7 is laminated on the surface of the insulating layer 6 by a lithographic technique. Reference numeral 9 denotes a through hole (for example, a diameter of 10 μm), and a conductive material layer is attached to the inner surface of the through hole 8 to make a required connection between the wiring portion 4a of the semiconductor laminated circuit 1 and the wiring portion 4c of the semiconductor laminated circuit 7. , And the wiring portion 4b of the semiconductor laminated circuit 1 and the wiring portion 4d of the semiconductor laminated circuit 7 are connected as required.
【０００５】このように、半導体積層回路を凹凸の上に
さらに積層する代わりに、平坦化した後に所要の回路を
配線基板に配置する手段が用いられる。しかし、この手
段では、積層化に従い製造の歩留まりが等比級数的に著
しく低下するため、各ＩＣチップは別個のセラミック又
はガラスの配線モジュール上に配置する手段も用いられ
る。これを図１６により説明する。図１６は配線モジュ
ールを用いた半導体積層回路の断面図である。この図
で、１１、１２はＩＣチップ、１３は配線モジュールを
示す。配線モジュール１３は複数の層より成り、各層に
配線が施されており、かつ、他の層との間の接続のため
導体金属を充填したスルーホールが形成されている。Ｉ
Ｃチップ１１に形成されているスルーホールと配線モジ
ュール１３の最上層に形成されているスルーホールとが
接続され、又、ＩＣチップ１２の外部に付着された配線
部と配線モジュール１３の最上層に形成されているスル
ーホールとが接続され、これにより、各ＩＣチップ１
１、１２がそれぞれ所要の他のＩＣチップと接続され
る。As described above, instead of further laminating the semiconductor laminated circuit on the unevenness, a means for arranging the required circuit on the wiring substrate after flattening is used. However, in this method, the manufacturing yield is significantly reduced in a geometrical progression as the layers are laminated. Therefore, a method of disposing each IC chip on a separate ceramic or glass wiring module is also used. This will be described with reference to FIG. FIG. 16 is a sectional view of a semiconductor laminated circuit using a wiring module. In this figure, 11 and 12 are IC chips, and 13 is a wiring module. The wiring module 13 includes a plurality of layers, wiring is provided in each layer, and through holes filled with a conductive metal are formed for connection with other layers. I
The through hole formed in the C chip 11 and the through hole formed in the uppermost layer of the wiring module 13 are connected, and the wiring portion attached to the outside of the IC chip 12 and the uppermost layer of the wiring module 13 are connected. The formed through holes are connected to each other, so that each IC chip 1
1 and 12 are respectively connected to other required IC chips.
【０００６】[0006]
【発明が解決しようとする課題】上記の図１５および図
１６に示す手段は、半導体積層回路や配線モジュールを
多層化して回路を構成する手段である。このように多層
化する手段では、製造工程が多層化された層の数に比例
して増加し、歩留まりが悪化するという問題があった。
さらに、各層間を接続する配線が長くなり、信号伝送時
間が増大するという問題もあった。The means shown in FIGS. 15 and 16 are means for forming a circuit by stacking semiconductor laminated circuits or wiring modules in multiple layers. In such a method of forming multiple layers, there is a problem in that the number of manufacturing steps increases in proportion to the number of layers and the yield deteriorates.
Further, there is also a problem that the wiring connecting each layer becomes long and the signal transmission time increases.
【０００７】本発明の目的は、上記従来技術における課
題を解決し、歩留まりを悪化させたり配線長を増大させ
たりすることなく高密度化が可能な三次元半導体積層回
路およびその製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems in the prior art, and to provide a three-dimensional semiconductor laminated circuit which can be highly densified without deteriorating the yield or increasing the wiring length, and a manufacturing method thereof. Especially.
【０００８】[0008]
【課題を解決するための手段】上記の目的を達成するた
め、本発明は、１つのチップで構成される半導体集積回
路と、この半導体集積回路の所定の個所に形成した局部
的平坦面と、この局部的平坦面に固定される１つのチッ
プで構成される半導体モジュールと、前記半導体集積回
路の配線部と前記半導体モジュールの配線部とを電気的
に接続する配線部接続手段とで三次元半導体集積回路を
構成したことを特徴とする。In order to achieve the above object, the present invention provides a semiconductor integrated circuit composed of one chip, and a locally flat surface formed at a predetermined portion of the semiconductor integrated circuit. A three-dimensional semiconductor including a semiconductor module composed of one chip fixed to the locally flat surface and a wiring section connecting means for electrically connecting the wiring section of the semiconductor integrated circuit and the wiring section of the semiconductor module. It is characterized in that an integrated circuit is configured.
【０００９】又、本発明は、１つのチップで構成される
半導体集積回路の表面の所定個所を機械的に加工して局
部的平坦面を形成し、この局部的平坦面に半導体モジュ
ールを溶接又は接着剤或いは拡散接合により固定し、前
記半導体集積回路の配線部と前記半導体モジュールの配
線部との間を、集束したレーザ又は原子流或いはイオン
流により導体物質で接合して三次元半導体集積回路を製
造することを特徴とする。Further, according to the present invention, a predetermined part of the surface of a semiconductor integrated circuit composed of one chip is mechanically processed to form a locally flat surface, and a semiconductor module is welded or welded to the locally flat surface. The three-dimensional semiconductor integrated circuit is fixed by an adhesive or diffusion bonding, and the wiring portion of the semiconductor integrated circuit and the wiring portion of the semiconductor module are joined with a conductive material by a focused laser or atomic flow or ion flow. It is characterized by manufacturing.
【００１０】[0010]
【作用】半導体積層回路の表面の所定個所を機械的手段
で散逸させて凹部を形成し、この凹部に、既成の半導体
モジュールを溶接又は接着剤或いは拡散接合により固定
し、半導体集積回路の配線部と半導体モジュールの配線
部との間を、集束したレーザ又は原子流或いはイオン流
により導体物質で接合する。このように、個々に完成し
た半導体モジュールを直接に組み立てることにより、ひ
とつの半導体の多層化を避けることができ、ひいては歩
留まりの悪化や配線長の増大を生じることなく、高密度
の三次元半導体集積回路を構成することができる。A predetermined portion of the surface of the semiconductor laminated circuit is dissipated by mechanical means to form a concave portion, and an existing semiconductor module is fixed to the concave portion by welding, an adhesive, or diffusion bonding, and a wiring portion of the semiconductor integrated circuit. And the wiring part of the semiconductor module are joined with a conductive material by a focused laser or an atomic flow or an ion flow. As described above, by directly assembling the individually completed semiconductor modules, it is possible to avoid the multi-layering of one semiconductor, and further, it is possible to achieve high-density three-dimensional semiconductor integration without deteriorating the yield or increasing the wiring length. A circuit can be constructed.
【００１１】[0011]
【実施例】以下、本発明を図示の実施例に基づいて説明
する。図１は本発明の第１の実施例に係る三次元半導体
集積回路の断面図である。これらの図で、図１４に示す
部分と同一又は等価な部分には同一符号が付してある。
２０は半導体集積回路１の回路面の所要個所に形成され
た凹部を示す。３０は半導体積層回路１とは別の小形の
半導体モジュールであり、Ｓｉ基板３１、素子層３２、
配線部３３、絶縁層（ＳｉＯ2 やポリイミド）３４で構
成されている。３５は半導体モジュール３０の側部端面
３１ＴにスパッタされたＡｕ層である。３７は半導体積
層回路１の配線部４ａと半導体モジュール３０の配線部
３３との間の接続を行なうタングステン（Ｗ）層であ
る。The present invention will be described below with reference to the illustrated embodiments. 1 is a sectional view of a three-dimensional semiconductor integrated circuit according to a first embodiment of the present invention. In these figures, the same or equivalent parts as those shown in FIG. 14 are designated by the same reference numerals.
Reference numeral 20 denotes a recess formed in a required portion of the circuit surface of the semiconductor integrated circuit 1. Reference numeral 30 denotes a small-sized semiconductor module different from the semiconductor laminated circuit 1, which includes a Si substrate 31, an element layer 32,
It is composed of a wiring portion 33 and an insulating layer (SiO 2 or polyimide) 34. Reference numeral 35 denotes an Au layer sputtered on the side end surface 31T of the semiconductor module 30. Reference numeral 37 is a tungsten (W) layer for connecting the wiring portion 4a of the semiconductor laminated circuit 1 and the wiring portion 33 of the semiconductor module 30.
【００１２】次に、上記半導体集積回路の製造方法を、
図２、図３および図４を参照して説明する。図２は図１
４に示す半導体集積回路１と同一又は等価な半導体集積
回路を示し、図１４に示す部分と同一又は等価な部分に
は同一符号が付してある。まず、半導体集積回路１の表
面（回路面）の所定の個所に、先端半径１μｍのダイヤ
モンドの針に、押し付け力を0.5 ｍＮ一定に保持しなが
ら、12ＫＨｚ、0.5 μｍｐ−ｐの水平円振動を与えて当
該個所の切削を、切り屑を吸引しながら行ない、10×50
μｍの凹部２０を形成する。凹部２０の底面には、0.03
μｍの凹凸と平坦にＳｉが露出される。この状態が図３
に示されている。Next, a method for manufacturing the above semiconductor integrated circuit will be described.
This will be described with reference to FIGS. 2, 3 and 4. 2 is shown in FIG.
4 shows a semiconductor integrated circuit which is the same as or equivalent to the semiconductor integrated circuit 1 shown in FIG. 4, and parts which are the same as or equivalent to those shown in FIG. First, a diamond circular needle having a tip radius of 1 μm is applied to a predetermined position on the surface (circuit surface) of the semiconductor integrated circuit 1, while a pressing force is kept constant at 0.5 mN, and horizontal circular vibration of 12 KHz and 0.5 μmp-p is applied. Cutting the relevant part while sucking chips, 10 × 50
A recess 20 of μm is formed. 0.03 on the bottom of the recess 20
Si is exposed flat with unevenness of μm. This state is shown in Figure 3.
Is shown in.
【００１３】なお、除去した素子層３８および配線層４
８は、共通機能に適した汎用の半導体モジュール２のう
ち、本実施例の機能に不要な部分である。又、各種の機
能に対応してマスクを用意し、Ｓｉがエッチングストッ
プ層になるようにエッチングしても凹面２０は製造でき
るが、本実施例の機械加工は高価なマスクの準備や他の
部分にマスキングを強いるようなエッチングを行なわず
に、その所要な部分だけを他の部分に影響を及ぼさずに
除去できる。さらに、エッチングによる材料の組成、残
留応力などのムラによる表面の凹凸より平坦な表面を創
出できる。The removed element layer 38 and wiring layer 4
Reference numeral 8 denotes a portion of the general-purpose semiconductor module 2 suitable for the common function, which is unnecessary for the function of this embodiment. Further, the concave surface 20 can be manufactured by preparing a mask corresponding to various functions and etching so that Si serves as an etching stop layer. However, the machining of this embodiment requires expensive mask preparation and other parts. It is possible to remove only the required portion without affecting other portions without performing etching forcing masking on. Further, it is possible to create a flatter surface than unevenness of the surface due to unevenness of material composition, residual stress, etc. due to etching.
【００１４】図３に示す半導体集積回路１とは別に、既
成の半導体モジュール３０を用意し、その側部端面３１
ＴにＡｕを薄くスパッタする。この半導体モジュール３
０を、その回路面が半導体集積回路１の回路面に対して
ほぼ垂直になり、かつ、Ａｕ層３５が凹部２０の底部に
接触するような状態で凹部２０に立て、200 ℃で拡散接
合させる。この状態が図４に示されている。次にノズル
状に先をしぼったＦ−ＦＡＢ（ＦｏｃｕｓｅｄＦａｓｔ
Ａｔｏｍ Ｂｅａｍ）ガンによって半導体モジュール
３０の配線部３３と半導体積層回路１の配線部４ａとの
間において、外部に露出しているＳｉ基板２および絶縁
層５上にタングステンを付着させてタングステン層３７
を形成する。この状態が図１に示されている。上記の各
数値は一例を示す数値である。A ready-made semiconductor module 30 is prepared separately from the semiconductor integrated circuit 1 shown in FIG.
Au is thinly sputtered on T. This semiconductor module 3
0 is erected in the recess 20 such that its circuit surface is substantially perpendicular to the circuit surface of the semiconductor integrated circuit 1 and the Au layer 35 is in contact with the bottom of the recess 20, and diffusion bonding is performed at 200 ° C. . This state is shown in FIG. Next, an F-FAB (Focused Fast) with a nozzle-shaped tip squeezed
Between the wiring portion 33 of the semiconductor module 30 and the wiring portion 4a of the semiconductor laminated circuit 1 by an atom beam gun, tungsten is deposited on the Si substrate 2 and the insulating layer 5 exposed to the outside to form the tungsten layer 37.
To form. This state is shown in FIG. The above numerical values are numerical values showing an example.
【００１５】このように、本実施例では、共通機能を有
する汎用の半導体積層回路の表面を機械的に切削して凹
部を形成し、この凹部に特殊機能を有する半導体モジュ
ールを固定し、半導体積層回路の所要の配線部と、半導
体モジュールの所要の配線とをタングステンで最短距離
で接続したので、半導体積層回路上にさらに積層を行な
う必要はなく、したがって、歩留まりの悪化や配線長の
増大を生じることなく高密度の三次元半導体集積回路を
構成することができる。又、凹部は局部的に形成される
ので、不必要な機能をもつ回路部分の除去を、最小に止
めることができる。As described above, in the present embodiment, the surface of the general-purpose semiconductor laminated circuit having the common function is mechanically cut to form the concave portion, and the semiconductor module having the special function is fixed to the concave portion to form the semiconductor laminated layer. Since the required wiring portion of the circuit and the required wiring of the semiconductor module are connected by the shortest distance with tungsten, it is not necessary to perform further lamination on the semiconductor laminated circuit, so that the yield is deteriorated and the wiring length is increased. It is possible to configure a high-density three-dimensional semiconductor integrated circuit without using the device. Further, since the concave portion is locally formed, the removal of the circuit portion having an unnecessary function can be minimized.
【００１６】図５および図６は本発明の第２の実施例に
係る三次元半導体集積回路の断面図である。各図で、図
１４に示す部分と同一又は等価な部分には同一符号が付
してある。４ｅは接続対象となる配線部を示す。本実施
例においても、半導体集積回路１の回路面を切削し、こ
れにより形成された底部が平坦な凹部に小形の半導体モ
ジュール３０を、その回路面が半導体積層回路１の回路
面とほぼ垂直な状態で固定して所要の接続を行なう。本
実施例における凹部は、絶縁層５と配線部４の一部を切
削することにより形成される。このように切削された状
態が図５に破線で示され、それにより形成された凹部が
符号２１で示されている。このように、機械的除去加工
では、底面が工具の移動面で決定されるため、底面に絶
縁層と配線部が混在していても平坦に創出できる。これ
は、反応する液体又は気体による化学的除去加工ではな
し得ない特徴である。5 and 6 are sectional views of a three-dimensional semiconductor integrated circuit according to the second embodiment of the present invention. In each figure, the same or equivalent parts as those shown in FIG. 14 are designated by the same reference numerals. Reference numeral 4e indicates a wiring portion to be connected. Also in this embodiment, the circuit surface of the semiconductor integrated circuit 1 is cut, and the small semiconductor module 30 is formed in the recess having a flat bottom formed by this, and the circuit surface thereof is substantially perpendicular to the circuit surface of the semiconductor laminated circuit 1. Fix in the state and make the required connection. The recess in this embodiment is formed by cutting a part of the insulating layer 5 and the wiring portion 4. The state of being cut in this way is shown by a broken line in FIG. 5, and the concave portion formed thereby is shown by reference numeral 21. As described above, in the mechanical removal processing, the bottom surface is determined by the moving surface of the tool, so that even if the insulating layer and the wiring portion are mixed on the bottom surface, it can be created flat. This is a characteristic that cannot be achieved by chemical removal processing with a reacting liquid or gas.
【００１７】図６は別に用意された既成の半導体モジュ
ール３０を上記凹部２１に固定して半導体集積回路１に
接続した状態を示す図である。半導体モジュール３０の
Ｓｉ基板３１表面および側面所要部分に配線部３３に接
してＡｕをスパッタし、凹部２１に半導体モジュール３
０を、その側面のスパッタ部分が半導体集積回路１の切
削後の配線部４ｅと接触する状態で立て、拡散接合させ
る。本実施例の効果もさきの実施例の効果と同じであ
る。FIG. 6 is a view showing a state in which a ready-made semiconductor module 30 prepared separately is fixed in the recess 21 and connected to the semiconductor integrated circuit 1. Au is sputtered on the surface of the Si substrate 31 of the semiconductor module 30 and on a required portion of the side surface thereof in contact with the wiring portion 33, and the semiconductor module 3 is formed in the recess 21.
0 is set in a state where the sputtered portion on the side surface thereof is in contact with the cut wiring portion 4e of the semiconductor integrated circuit 1, and diffusion bonding is performed. The effect of this embodiment is the same as the effect of the previous embodiment.
【００１８】図７は本発明の第３の実施例に係る三次元
半導体集積回路の断面図である。この図で、図５に示す
部分と同一又は等価な部分には同一符号が付してある。
４ａは接続対象となる配線部（図１に示す配線部に相当
する配線部）を示す。本実施例においても、半導体集積
回路１の回路面を切削して形成された図５に示すものと
同じ凹部２１に小形の半導体モジュール３０を、その回
路面が半導体積層回路１の回路面とほぼ垂直な状態で固
定して所要の接続を行なうものであり、当該接続は半導
体モジュール３０の配線部３３と、半導体集積回路１の
配線部４ａ、４ｅとの間の接続である。FIG. 7 is a sectional view of a three-dimensional semiconductor integrated circuit according to the third embodiment of the present invention. In this figure, the same or equivalent parts as those shown in FIG. 5 are designated by the same reference numerals.
Reference numeral 4a indicates a wiring portion to be connected (a wiring portion corresponding to the wiring portion shown in FIG. 1). Also in this embodiment, a small semiconductor module 30 is formed in the same recess 21 as that shown in FIG. 5 formed by cutting the circuit surface of the semiconductor integrated circuit 1, and the circuit surface thereof is almost the same as the circuit surface of the semiconductor laminated circuit 1. The connection is made in a fixed state in a vertical state, and the connection is between the wiring portion 33 of the semiconductor module 30 and the wiring portions 4a and 4e of the semiconductor integrated circuit 1.
【００１９】本実施例では、半導体モジュール３０の凹
部２１への固定を、ろう付け接着により行なう点でさき
の各実施例と異なる。４０は当該ろう付け部を示す。ろ
う付け部４０により半導体モジュール３０を凹部２１に
固定した後、半導体モジュール３０の配線部３３と半導
体集積回路１の配線部４ａ、４ｅとの間にモリブデンが
付着される。本実施例の効果もさきの実施例の効果と同
じである。This embodiment differs from the previous embodiments in that the semiconductor module 30 is fixed to the recess 21 by brazing. 40 indicates the brazing part. After the semiconductor module 30 is fixed to the recess 21 by the brazing portion 40, molybdenum is attached between the wiring portion 33 of the semiconductor module 30 and the wiring portions 4a and 4e of the semiconductor integrated circuit 1. The effect of this embodiment is the same as the effect of the previous embodiment.
【００２０】図８および図９は本発明の第４の実施例に
係る三次元半導体集積回路の断面図である。各図で、図
２に示す部分と同一又は等価な部分には同一符号が付し
てある。４ａ、４ｆ、４ｇ、４ｈ、４ｉは接続対象とな
る半導体積層回路１側の配線部を示す。本実施例におい
ても、半導体集積回路１の回路面を切削し、これにより
形成された凹部に小形の半導体モジュールを、そのＳｉ
基板面が半導体積層回路１の回路面と対向する状態で固
定して所要の接続を行なう。本実施例における凹部は、
絶縁層５と配線部４の一部を切削することにより形成さ
れる。このように切削された状態が図８に破線で示さ
れ、それにより形成された凹部が符号２２で示されてい
る。8 and 9 are sectional views of a three-dimensional semiconductor integrated circuit according to the fourth embodiment of the present invention. In each figure, the same or equivalent parts as those shown in FIG. 2 are designated by the same reference numerals. Reference numerals 4a, 4f, 4g, 4h, and 4i denote wiring portions on the semiconductor laminated circuit 1 side to be connected. Also in this embodiment, the circuit surface of the semiconductor integrated circuit 1 is cut, and a small semiconductor module is formed in the concave portion formed by the cutting.
The substrate is fixed so that the surface of the substrate faces the circuit surface of the semiconductor laminated circuit 1, and the required connection is made. The recess in this embodiment is
It is formed by cutting a part of the insulating layer 5 and the wiring portion 4. The state of being cut in this way is shown by a broken line in FIG. 8, and the concave portion formed thereby is shown by reference numeral 22.
【００２１】図９は別に用意された既成の半導体モジュ
ールを上記凹部２２に固定して半導体集積回路１に接続
した状態を示す図である。この図で、５０は小形の半導
体モジュールを示す。この半導体モジュール５０は、Ｓ
ｉ基板５１、素子層５２、配線部５３、絶縁層５４を有
する。半導体積層回路１の配線部４ｆと半導体モジュー
ル５０の配線部５３との間の接続のため、半導体モジュ
ール５０のＳｉ基板５１にスルーホール５５Ｈ1 （内壁
に導電物質が塗布されている。以下同じ。）が形成さ
れ、同じく配線部４ａと素子層５２との間を接続するた
めスルーホール５５Ｈ2 が、又、配線部４ｉと素子層５
２および配線部５３との間を接続するためスルーホール
５５Ｈ3 がそれぞれ形成されている。本実施例の効果も
さきの各実施例の効果と同じである。FIG. 9 is a view showing a state in which a separately prepared ready-made semiconductor module is fixed in the recess 22 and connected to the semiconductor integrated circuit 1. In this figure, 50 indicates a small semiconductor module. This semiconductor module 50 is
The i-substrate 51, the element layer 52, the wiring portion 53, and the insulating layer 54 are included. In order to connect the wiring portion 4f of the semiconductor laminated circuit 1 and the wiring portion 53 of the semiconductor module 50, the through hole 55H 1 (conductive material is applied to the inner wall of the Si substrate 51 of the semiconductor module 50. The same applies hereinafter. ) Is formed, a through hole 55H 2 for connecting the wiring portion 4a and the element layer 52 is formed, and the wiring portion 4i and the element layer 5 are also formed.
Through holes 55H 3 are formed to connect between the wiring 2 and the wiring portion 53. The effect of this embodiment is the same as the effect of each of the preceding embodiments.
【００２２】図１０は本発明の第５の実施例に係る三次
元半導体積層回路の断面図である。この図で、図９に示
す部分と同一又は等価な部分には同一符号が付してあ
る。図９に示す実施例が半導体モジュール５０を、その
Ｓｉ基板５１を半導体積層回路１の回路面に対向させた
状態で凹部２２に固定したのに対して、本実施例では、
半導体モジュール５０を、その回路面を半導体積層回路
１の回路面に対向させた状態で凹部２２に固定した点で
図９に示す実施例と異なる。図１０で、５８Ｓは半導体
モジュール５０の絶縁部５４の外面に沿って付着された
導電層であり、半導体積層回路１の配線部４ｆに接続さ
れる。５８Ｈ1 、５８Ｈ2 はそれぞれ半導体モジュール
５０の絶縁層５４に設けられたスルーホールであり、半
導体積層回路１の配線部４ａ、４ｉに接続される。本実
施例の効果もさきの各実施例の効果と同じである。FIG. 10 is a sectional view of a three-dimensional semiconductor laminated circuit according to the fifth embodiment of the present invention. In this figure, the same or equivalent parts as those shown in FIG. 9 are designated by the same reference numerals. In the embodiment shown in FIG. 9, the semiconductor module 50 is fixed in the recess 22 with the Si substrate 51 facing the circuit surface of the semiconductor laminated circuit 1, whereas in the embodiment,
The semiconductor module 50 is different from the embodiment shown in FIG. 9 in that the semiconductor module 50 is fixed to the recess 22 with its circuit surface facing the circuit surface of the semiconductor laminated circuit 1. In FIG. 10, 58S is a conductive layer attached along the outer surface of the insulating portion 54 of the semiconductor module 50, and is connected to the wiring portion 4f of the semiconductor laminated circuit 1. Reference numerals 58H 1 and 58H 2 are through holes provided in the insulating layer 54 of the semiconductor module 50, and are connected to the wiring portions 4a and 4i of the semiconductor laminated circuit 1. The effect of this embodiment is the same as the effect of each of the preceding embodiments.
【００２３】図１１、図１２および図１３はそれぞれ本
発明の第６の実施例に係る三次元半導体積層回路の製造
工程断面図である。これら各図で、同一部分には同一符
号が付してある。図１１で、６０は半導体積層回路を示
し、Ｓｉ基板６１、Ａｌの配線層６２および絶縁層６３
で構成されている。図１２に示す符号７１、７２は半導
体集積回路６０の回路面の一部を排除してできた２つの
凹部を示す。図１３で、８０は既成の半導体モジュール
を示す。この半導体モジュール８０は、Ｓｉ基板８１、
素子層８２、配線部８３、絶縁層８４、およびＡｌより
成る２つの導電突出部８６で構成されている。11, FIG. 12 and FIG. 13 are cross-sectional views of manufacturing steps of a three-dimensional semiconductor laminated circuit according to the sixth embodiment of the present invention. In each of these figures, the same parts are designated by the same reference numerals. In FIG. 11, reference numeral 60 denotes a semiconductor laminated circuit, which includes a Si substrate 61, an Al wiring layer 62 and an insulating layer 63.
It is composed of Reference numerals 71 and 72 shown in FIG. 12 denote two recesses formed by removing a part of the circuit surface of the semiconductor integrated circuit 60. In FIG. 13, reference numeral 80 denotes an existing semiconductor module. The semiconductor module 80 includes a Si substrate 81,
The element layer 82, the wiring portion 83, the insulating layer 84, and the two conductive protruding portions 86 made of Al are included.
【００２４】次に本実施例の製造方法を説明する。図１
１に示す半導体集積回路６０の表面（回路面）の所定個
所（図では両側部）に対して、先端半径１μｍのダイヤ
モンドの針に、高さを一定に保持しながら、30ＫＨｚ、
1 μｍｐ−ｐの水平円振動を与えて当該個所の切削を行
ない、10×10μｍの凹部７１、７２を形成する。各凹部
７１、７２の底面には、絶縁層６３（ＳｉＯ2 ）とＡｌ
の配線部６２とが露出される。この状態が図１２に示さ
れている。Next, the manufacturing method of this embodiment will be described. FIG.
30 kHz at a predetermined position (both sides in the figure) on the surface (circuit surface) of the semiconductor integrated circuit 60 shown in FIG. 1 while holding the height constant with a diamond needle having a tip radius of 1 μm,
A horizontal circular vibration of 1 .mu.mp-p is applied to cut the relevant portion to form recesses 71, 72 of 10.times.10 .mu.m. The insulating layer 63 (SiO 2 ) and Al are formed on the bottom surface of each recess 71, 72.
And the wiring portion 62 of are exposed. This state is shown in FIG.
【００２５】次に、図１３に示す予め用意された既成の
半導体モジュール８０を半導体積層回路６０に接合す
る。この接合は、半導体モジュール８０の導電突出部８
６を、それぞれ凹部７１、７２に露出したＡｌの配線部
６２に接触させた状態（半導体集積回路６０の回路面と
半導体モジュール８０の回路面とが対向する状態）で押
し付け、樹脂材料９０をレーザによってろう付けするこ
とにより行なう。この状態が図１３に示されている。当
該樹脂材料９０のろう付け時の熱により、導電突出部８
６のＡｌが配線部６２のＡｌと拡散接合する。なお、上
記の各数値は一例を示す数値である。本実施例の効果も
さきの各実施例の効果と同じである。Next, the ready-made semiconductor module 80 shown in FIG. 13 is joined to the semiconductor laminated circuit 60. This joining is performed by the conductive protrusion 8 of the semiconductor module 80.
6 is pressed in a state of being in contact with the Al wiring portions 62 exposed in the recesses 71 and 72 (the circuit surface of the semiconductor integrated circuit 60 and the circuit surface of the semiconductor module 80 are opposed to each other), and the resin material 90 is irradiated with laser light. By brazing with. This state is shown in FIG. The conductive protrusion 8 is heated by the heat of the resin material 90 when brazing.
Al of 6 is diffusion bonded to Al of the wiring portion 62. It should be noted that each of the above numerical values is an example. The effect of this embodiment is the same as the effect of each of the preceding embodiments.
【００２６】なお、上記各実施例の説明では、半導体集
積回路に凹部を形成し、これに半導体モジュールを固定
する例について説明したが、凹部に限ることはなく、半
導体集積回路の突出部又は台形部を平坦にし、突出した
状態で半導体モジュールを固定してもよい。又、半導体
モジュールおよびそれを固定する平坦面は１つでなく、
２つ以上であってもよい。この場合、それらの数が多数
であると、高さの異なる半導体モジュールが半導体集積
回路の上に林立する状態となる。In the description of each of the above embodiments, an example in which a concave portion is formed in a semiconductor integrated circuit and a semiconductor module is fixed to the concave portion is described, but the concave portion is not limited to the projection portion or the trapezoid of the semiconductor integrated circuit. The semiconductor module may be fixed in a projecting state by flattening the portion. Also, the semiconductor module and the flat surface that fixes it are not one,
There may be two or more. In this case, when the number of them is large, the semiconductor modules having different heights stand on the semiconductor integrated circuit.
【００２７】[0027]
【発明の効果】以上述べたように、本発明では、半導体
集積回路の所定の個所に凹部を形成し、この凹部に半導
体モジュールを固定し、半導体集積回路の配線部と半導
体モジュールの配線部とを電気的に接続するようにした
ので、多層化を避けることができ、ひいては歩留まりの
悪化を生じることなく、高密度の三次元半導体集積回路
を構成することができる。又、凹部は局部的に形成され
るので、回路部分の破壊を最小に止めることができる。As described above, according to the present invention, a concave portion is formed at a predetermined position of a semiconductor integrated circuit, the semiconductor module is fixed in the concave portion, and a wiring portion of the semiconductor integrated circuit and a wiring portion of the semiconductor module are formed. Since they are electrically connected to each other, it is possible to avoid multi-layering, and it is possible to construct a high-density three-dimensional semiconductor integrated circuit without lowering the yield. Further, since the concave portion is locally formed, it is possible to minimize the destruction of the circuit portion.
【図１】本発明の第１の実施例に係る三次元半導体集積
回路の断面図である。FIG. 1 is a sectional view of a three-dimensional semiconductor integrated circuit according to a first embodiment of the present invention.
【図２】図１に示す三次元半導体集積回路の製造方法を
説明する図である。FIG. 2 is a diagram illustrating a method of manufacturing the three-dimensional semiconductor integrated circuit shown in FIG.
【図３】図１に示す三次元半導体集積回路の製造方法を
説明する図である。FIG. 3 is a diagram illustrating a method for manufacturing the three-dimensional semiconductor integrated circuit shown in FIG.
【図４】図１に示す三次元半導体集積回路の製造方法を
説明する図である。FIG. 4 is a diagram illustrating a method of manufacturing the three-dimensional semiconductor integrated circuit shown in FIG.
【図５】本発明の第２の実施例に係る三次元半導体集積
回路の製造過程を説明する図である。FIG. 5 is a diagram illustrating a manufacturing process of the three-dimensional semiconductor integrated circuit according to the second embodiment of the present invention.
【図６】本発明の第２の実施例に係る三次元半導体集積
回路の断面図である。FIG. 6 is a sectional view of a three-dimensional semiconductor integrated circuit according to a second embodiment of the present invention.
【図７】本発明の第３の実施例に係る三次元半導体集積
回路の断面図である。FIG. 7 is a sectional view of a three-dimensional semiconductor integrated circuit according to a third embodiment of the present invention.
【図８】本発明の第４の実施例に係る三次元半導体集積
回路の製造過程を説明する図である。FIG. 8 is a diagram illustrating a manufacturing process of the three-dimensional semiconductor integrated circuit according to the fourth embodiment of the present invention.
【図９】本発明の第４の実施例に係る三次元半導体集積
回路の断面図である。FIG. 9 is a sectional view of a three-dimensional semiconductor integrated circuit according to a fourth embodiment of the present invention.
【図１０】本発明の第５の実施例に係る三次元半導体集
積回路の断面図である。FIG. 10 is a sectional view of a three-dimensional semiconductor integrated circuit according to a fifth embodiment of the present invention.
【図１１】本発明の第６の実施例に係る三次元半導体集
積回路の製造過程を説明する図である。FIG. 11 is a diagram illustrating a manufacturing process of the three-dimensional semiconductor integrated circuit according to the sixth embodiment of the present invention.
【図１２】本発明の第６の実施例に係る三次元半導体集
積回路の製造過程を説明する図である。FIG. 12 is a diagram illustrating a manufacturing process of the three-dimensional semiconductor integrated circuit according to the sixth embodiment of the present invention.
【図１３】本発明の第６の実施例に係る三次元半導体集
積回路の断面図である。FIG. 13 is a sectional view of a three-dimensional semiconductor integrated circuit according to a sixth embodiment of the present invention.
【図１４】従来の半導体積層回路の断面図である。FIG. 14 is a cross-sectional view of a conventional semiconductor laminated circuit.
【図１５】従来の半導体積層回路の断面図である。FIG. 15 is a cross-sectional view of a conventional semiconductor laminated circuit.
【図１６】従来の半導体積層回路の断面図である。FIG. 16 is a cross-sectional view of a conventional semiconductor laminated circuit.
１ 半導体集積回路 ２ Ｓｉ基板 ３ 素子層 ４、４ａ、４ｂ 配線部 ５ 絶縁層 ２０ 凹部 ３０ 半導体モジュール ３１ Ｓｉ基板 ３２ 素子層 ３３ 配線部 ３４ 絶縁層 ３５ Ａｕ層 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Si substrate 3 Element layer 4, 4a, 4b Wiring part 5 Insulating layer 20 Recessed portion 30 Semiconductor module 31 Si substrate 32 Element layer 33 Wiring portion 34 Insulating layer 35 Au layer
Claims (8)
路と、この半導体集積回路の所定の個所に形成した局部
的平坦面と、この局部的平坦面に固定される１つのチッ
プで構成される半導体モジュールと、前記半導体集積回
路の配線部と前記半導体モジュールの配線部とを電気的
に接続する配線部接続手段とで構成したことを特徴とす
る三次元半導体集積回路。1. A semiconductor integrated circuit composed of one chip, a locally flat surface formed at a predetermined portion of the semiconductor integrated circuit, and one chip fixed to the locally flat surface. A three-dimensional semiconductor integrated circuit comprising a semiconductor module and a wiring section connecting means for electrically connecting the wiring section of the semiconductor integrated circuit and the wiring section of the semiconductor module.
よびこれに固定される１つのチップの組は、１つ又は複
数であることを特徴とする三次元半導体集積回路。2. The three-dimensional semiconductor integrated circuit according to claim 1, wherein the local flat surface and one chip set fixed to the local flat surface are one or more.
ルは、その回路面が前記半導体集積回路の回路面とほぼ
垂直になるように前記局部的平坦面に固定されているこ
とを特徴とする三次元半導体集積回路。3. The three-dimensional structure according to claim 1, wherein the semiconductor module is fixed to the locally flat surface so that a circuit surface of the semiconductor module is substantially perpendicular to a circuit surface of the semiconductor integrated circuit. Semiconductor integrated circuit.
ルは、その回路面が前記半導体集積回路の回路面とほぼ
平行になるように前記局部的平坦面に固定されているこ
とを特徴とする三次元半導体集積回路。4. The three-dimensional structure according to claim 1, wherein the semiconductor module is fixed to the locally flat surface such that a circuit surface of the semiconductor module is substantially parallel to a circuit surface of the semiconductor integrated circuit. Semiconductor integrated circuit.
ルは、その回路面が前記半導体集積回路の回路面と対向
していることを特徴とする三次元半導体集積回路。5. The three-dimensional semiconductor integrated circuit according to claim 3, wherein a circuit surface of the semiconductor module faces a circuit surface of the semiconductor integrated circuit.
ルは、その基板が前記半導体集積回路の回路面と対向し
ていることを特徴とする三次元半導体集積回路。6. The three-dimensional semiconductor integrated circuit according to claim 3, wherein the substrate of the semiconductor module faces a circuit surface of the semiconductor integrated circuit.
は、前記半導体モジュールの基板を貫通して形成される
スルーホールと、このスルーホール内に形成された導体
物質層とで構成されていることを特徴とする三次元半導
体集積回路。7. The wiring part connecting means according to claim 5, comprising a through hole formed through the substrate of the semiconductor module, and a conductor material layer formed in the through hole. A three-dimensional semiconductor integrated circuit characterized by the above.
路の表面の所定個所を機械的に加工して局部的平坦面を
形成し、この局部的平坦面に半導体モジュールを溶接又
は接着剤或いは拡散接合により固定し、前記半導体集積
回路の配線部と前記半導体モジュールの配線部との間
を、集束したレーザ又は原子流或いはイオン流により導
体物質で接合したことを特徴とする三次元半導体集積回
路の製造方法。8. A locally flat surface is formed by mechanically processing a predetermined portion of the surface of a semiconductor integrated circuit composed of one chip, and a semiconductor module is welded or glued or diffused on the locally flat surface. A three-dimensional semiconductor integrated circuit, which is fixed by bonding, and is bonded between a wiring part of the semiconductor integrated circuit and a wiring part of the semiconductor module with a conductive material by a focused laser or an atomic flow or an ion flow. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21738494A JPH0883884A (en) | 1994-09-12 | 1994-09-12 | Three-dimensional semiconductor integrated circuit and fabrication therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21738494A JPH0883884A (en) | 1994-09-12 | 1994-09-12 | Three-dimensional semiconductor integrated circuit and fabrication therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0883884A true JPH0883884A (en) | 1996-03-26 |
Family
ID=16703336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21738494A Pending JPH0883884A (en) | 1994-09-12 | 1994-09-12 | Three-dimensional semiconductor integrated circuit and fabrication therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0883884A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6807363B1 (en) | 1999-10-29 | 2004-10-19 | Fujitsu Limited | Digital moving picture data player system having a time-based access list |
| US8841778B2 (en) | 1997-04-04 | 2014-09-23 | Glenn J Leedy | Three dimensional memory structure |
-
1994
- 1994-09-12 JP JP21738494A patent/JPH0883884A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8841778B2 (en) | 1997-04-04 | 2014-09-23 | Glenn J Leedy | Three dimensional memory structure |
| US8907499B2 (en) | 1997-04-04 | 2014-12-09 | Glenn J Leedy | Three dimensional structure memory |
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