JPH0883496A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To shorten the access time to the address with which a defective address is replaced when the defective address is designated. CONSTITUTION: A main memory address cell array 1 where many ordinary cells S1 are arranged is connected with decoders 2, 3 which select ordinary cells S1 designated by an address signal A1. A spare memory cell array 4 with a small capacity is installed separately from the main memory cell array 1 and is connected with spare decoders 5, 6 for selecting the spare cell S2. The spare decoders 5, 6 are connected to a decision means 7. In the case where the address designated by the address signal A1 is defective, the means 7 outputs to the spare decoders 5, 6 a second address signal A2 that designates the address with which the defective address is replaced in the spare memory cell array 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy function. In recent years, semiconductor memory devices have become larger in scale, and higher processing speeds have been demanded. Along with this, in the manufacturing process, miniaturization and increase in the number of elements to be manufactured progress, the defect rate of cells in the semiconductor memory device increases, and the yield decreases. Therefore, redundant cells (spare cells) are additionally manufactured in addition to the normal cells that are normally used in the semiconductor memory device in advance, and the redundant cells are used when there are defective cells in the normal cells. Redundancy (defect relief) to relieve the defective cell by
The design is being done.

[0002]

2. Description of the Related Art Spare cells are arranged on the same memory cell array as normal cells along word lines or bit lines, and usually several spare lines are prepared. The repair of the defective cell is performed by replacing the line in the one row or the one column including the defective cell with the spare line. The spare line is selected by registering the defective address in the spare decoder, and the defective address is registered by using a method such as programming with a laser or blowing of a fuse.

For example, as shown in FIG. 5, a spare line 41a composed of a spare cell S2 is a memory cell array 41.
When formed in the column direction, the spare cell S2 shares a word line with the normal cell S1 and also has a spare line 4
The bit line 1a has the same resistance and capacitance as the bit line of the normal cell S1. Therefore, even when the defective address is designated, the same load as when the normal address is designated is applied to the word line and the bit line.
The processing speed of the memory is largely controlled by the wiring load (resistance) applied to the word line and the bit line.

In a redundant memory, it is necessary to judge whether the designated address is a defective address. Therefore, the address signal is sent to the decoder as well as to the matching circuit, and the matching circuit determines whether or not the designated address matches the defective address. When the designated address matches the defective address, the registered address on the spare line corresponding to the defective address is selected. At this time, the defective line replaced with the spare line is not electrically connected to the decoder, so that the defective line is not selected even when an address signal is input to the decoder.

[0005]

When the specified address is not a defective address, the normal cell corresponding to the specified address is selected as soon as the address signal is input to the decoder. However, when the designated address is a defective address, the process is delayed by the waiting time until the registration process for a new defective address is input to the decoder after waiting for the determination process in the coincidence circuit. Therefore, the access speed becomes slow when the defective cell is designated and the spare cell is selected.

Since the access speed of the entire memory is dominated by the slowest access speed, there is a problem that the delay of the access speed when the spare cell is selected causes the delay of the access speed of the memory as it is.

The present invention has been made in view of the above problems, and an object of the present invention is to output a signal for designating a replacement address when a defective address is designated as an output timing of a normal address signal. An object of the present invention is to provide a semiconductor memory device that can reduce the access speed of the semiconductor memory device by suppressing the processing delay caused by the delay.

[0008]

FIG. 1 is a diagram illustrating the principle of a semiconductor memory device according to the present invention. In the main memory cell array 1 in which a large number of normal cells S1 are arranged, each decoder 2, which selects the normal cell S1 designated based on the address signal A1,
3 is connected. The spare memory cell array 4 is provided separately from the main memory cell array 1, and the spare memory cell array 4 is connected with spare decoders 5 and 6 for selecting the spare cells S2 arranged therein. Each of the spare decoders 5 and 6 is connected to the judging means 7, and the judging means 7 specifies the replacement destination address in the spare memory cell array 4 when the designated address designated by the address signal A1 is a defective address. The second address signal A2 is output to the spare decoders 5 and 6.

The structure of the spare memory cell array 4 is as follows.
For example, a cell line 1a, which constitutes one bit line in the longitudinal direction of a defective region serving as a replacement unit for repairing a defective cell in the main memory cell array 1, is divided into 2 ⁿ equal parts where n is a natural number. It is possible to adopt a configuration in which the spare cell lines 4a each having a number of spare cells S2 equal to the number of divided cells as one bit line are arranged.

In addition to this configuration, for example, the spare decoders 5 and 6 select the first decoder 5 for selecting the spare cell line 4a from the spare memory cell array 4 and the address in the orthogonal direction of the spare cell line 4a. Second for
And the decoder 6 of. Then, the judging means 7 is caused to output the upper n bits of the N-bit address data designated by the address signal A1 to the first decoder 5 as the second address signal A2, and to the second decoder 6 as well. On the other hand, the lower (N−n) bits of the address data are output.

It is also possible to adopt a structure in which the defective area is a partial area including the defective cell in the cell line 1a and the defective area is replaced with the spare cell line 4a. In this case, the judgment means 7 is made to judge whether the address designated by the address signal A1 is a defective area or not, and when the designated address belongs to the defective area, the second address signal A2 is outputted. There is.

[0012]

The defective area including the defective cell in the main memory cell array 1 is stored in the spare cell line 4 in the spare memory cell array 4.
is replaced by a. The address of the defective area is registered in the judging means 7 in advance as a defective address. The address signal A1 is inputted to the decoders 2 and 3 and the judging means 7.
Based on the address signal A1, the normal cells arranged at the designated address are selected by the decoders 2 and 3 from the main memory cell array 1. Here, if the address designated by the address signal A1 is a defective address, the normal cell is not selected from the main memory cell array 1, and the second address signal A2 is sent from the judging means 7 to each spare decoder 5 , 6 are output. At this time, since the second address signal A2 is output after waiting for the judgment processing by the judging means 7, the input timing of the second address signal A2 to the spare decoders 5 and 6 is such that the decoder 2 at the normal time is input. It is slightly delayed from the input timing of the address signal A1 to A3. However, the number of spare cells arranged in the spare memory cell array 4 is sufficiently smaller than the number of normal cells arranged in the main memory cell array 1, and its word line and bit line are also sufficiently short, so that the second address The selection process of the spare cell S2 after the signal A2 is input to the spare decoders 5 and 6 can be completed in a short time. Therefore, the processing time from when the address signal A1 is input to the semiconductor memory device until the cell at the designated address destination is selected is compared with that when the designated address is a normal address, compared to when it is a normal address. Not too late.

Here, the spare memory cell array 4 is divided into the cell lines 1a in the main memory cell array 1 into 2 ⁿ equal parts where n is a natural number, and a number of spare cells S2 equal to the number of the divided cells are provided. If the spare cell line 4a is provided, the defective area can be replaced by each spare cell line 4a using the normal cell group S1 having the common upper n bits of the address as a replacement unit. At this time, the determination means 7 outputs, as the second address signal A2, the upper n bits of the N-bit address data designated by the address signal A1 to the first decoder 5, and outputs the second decoder 6 to the second decoder 6. The lower (N-n) bits of the address data are output. Therefore, the address data of the address signal A1 need only be sent as it is to the auxiliary decoders 5 and 6 by dividing it into upper bits and lower bits.

Further, if the spare cell line 4a is replaced with a partial area including the defective cell in the cell line 1a, the normal cell S1 other than the defective area in the cell line 1a is a normal cell. In addition, the area occupied by the spare memory cell array becomes small relative to the number of repair cells.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. The semiconductor memory device of this embodiment is composed of SRAM. FIG. 2 shows the overall configuration of the semiconductor memory device. As shown in the figure, the memory cell array 11 is constructed by arranging a large number of cell lines 11a in which normal cells S1 are arranged in the column direction. In the present embodiment, the repair of defective cells is performed in cell line 11a units. A row decoder 12 is connected to the memory cell array 11, and a column decoder 14 is connected via a gate circuit 13. The row decoder 12 is connected to the row address buffer 15, and the column decoder 14 is connected to the column address buffer 16.

The spare memory cell array 17 is provided separately from the memory cell array 11, and has a plurality of spare cell lines 17a (only one is shown in FIG. 2) in which the spare cells S2 are arranged in the column direction. It is installed and configured. The number of spare cells S2 arranged in one spare cell line 17a is 1/2 ^{n of the} number of normal cells S1 arranged in one cell line 11a. In this embodiment, n = 2 is adopted. The number of cells is 1/4. Therefore, the spare cell line 17a is 1/4 the length of the cell line 11a, and the bit line is also 1/4 the length. A spare row decoder 18 is connected to the spare memory cell array 17, and three spare column decoders 20 are connected via a gate circuit 19.

The four spare cell lines 17a form one unit, and one spare column decoder 20 is provided for each unit, that is, for every four spare cell lines 17a. The spare row decoder 18 and each spare column decoder 20 are both connected to the signal distribution circuit 21, and the signal distribution circuit 21 is connected to the row address buffer 15 and the coincidence circuit 22. Further, the matching circuit 22 has a redundant R
The OM 23 is connected.

The gate circuit 13 and the gate circuit 19 are connected via a common data line, and the common data line is connected to an input / output circuit 25 via a sense amplifier 24.
Reading and writing of data is performed via the common data line.

A row address signal RA for designating a row address input to the row address buffer 15 from the outside is
The row address buffer 15 outputs the data to the row decoder 12 and the signal distribution circuit 21. Also,
A column address signal CA designating a column address input to the column address buffer 17 from the outside is output from the column address buffer 17 to the column decoder 14 and the coincidence circuit 22.

The cell line 11a including the defective cell DS is not used as the defective cell line DL, and the spare cell line 17a in the spare memory cell array 17 is used as an alternative thereto. At this time, as shown in FIG. 3, four spare cell lines 17a are used as a substitute for one defective cell line DL. In this embodiment, up to three defective cell lines DL can be repaired.

Each cell line 11 is provided in the column decoder 14.
A large number of redundant fuses connected in series with each bit line are provided for each a. The redundant fuse corresponding to the defective cell line DL is cut in advance so that the defective cell line DL is not selected even if the column address signal CA designating the defective cell line DL is input to the column decoder 14.

The redundant ROM 23 stores defective column address data of the defective cell line DL and transfer designation data for designating a replacement destination of the defective cell line DL. The matching circuit 22 determines whether the column address designated by the column address signal CA matches the defective address based on the defective address data stored in the redundant ROM 23. When the column address coincides with the defective address, the designation signal SA designating the transfer destination is output to the signal distribution circuit 21 based on the transfer designation data.

Only when the designation signal SA is input, the signal distribution circuit 21 supplies the spare row decoder 18 with the lower (N) of the row address signal RA as the row address signal S _RA.
-2) In addition to outputting the bit, the upper 2 bits of the row address signal RA are output as the column address signal S _CA to the spare column decoder 20 designated by the designation signal SA.

Next, the operation of the semiconductor memory device configured as described above will be described. The row address signal RA externally input to the semiconductor memory device is output to the row decoder 12 and the signal distribution circuit 21 via the row address buffer 15, and the column address signal CA externally input.
Is output to the column decoder 14 and the coincidence circuit 22 via the column address buffer 16.

In the row decoder 12, the word line driver located at the specified row address is driven based on the input row address signal RA, and each normal cell S1 on that word line is activated. When the designated address is a normal address, the designated column address is selected in the column decoder 14 based on the input column address signal CA, and the designated column address is selected via the gate circuit 13, the sense amplifier SA, and the input / output circuit 25. Data is read or written between the bit line and the common data line.

Meanwhile, the coincidence circuit 22 determines whether or not the column address designated by the input column address signal CA coincides with the defective address based on the defective address data stored in the redundant ROM 23, and the designated column address is defective. If the address does not match, match circuit 2
No signal is output from 2. Therefore, when the designated address is a normal address, only the row address signal RA is input to the signal distribution circuit 21, and no signal is output from the signal distribution circuit 21.

Next, when the designated address is a defective address, the designated column address is selected by the column decoder 14 based on the column address signal CA.
The defective cell line DL is not selected because the fuse is blown. Therefore, each normal cell S on the word line located at the specified row address based on the row address signal RA.
Only 1 is activated, and data is not read or written in the memory cell array 11.

At this time, the coincidence circuit 22 determines that the designated column address based on the column address signal CA coincides with the defective address, and the coincidence circuit 22 outputs the designation signal SA to the signal distribution circuit 21. At that time, the signal distribution circuit 21 is in a waiting state for receiving the row address signal RA. When the designation signal SA is input, the lower (N-2) bits of the row address signal _RA are supplied from the signal distribution circuit 22 to the spare row decoder 1 as the row address signal S _RA.
8 is output to the spare column decoder 20 designated by the designation signal SA as the column address signal S _CA.

For example, if row address data "1100 ... 01" is designated by the row address signal RA, the lower (N-2) -bit data "00 ... 0" is specified.
1 "is output to the spare row decoder 18, and the upper 2 bits of data" 11 "are output to the spare column decoder 20 designated by the designation signal SA. Therefore, the replacement destination of the defective cell line DL is specified by which spare column decoder 20 of the three spare column decoders 20 the column address signal S _CA is output, and the four replacement target spare memory cell arrays 17 in the spare memory cell array 17 are identified. Spare cell line 17
A spare cell S2 to be replaced is selected from a by the row address signal S _RA input to the spare row decoder 18 and the column address signal S _CA input to the spare column decoder 20.

[0030] That is, output to the spare column decoder 20
The row in the defective cell line DL is
One spare cell to replace the cell corresponding to the address
The line 17a is selected by the spare column decoder 20.
It Then, “00” output to the spare row decoder 18 is output.
"01" is selected by the spare column decoder 20.
The defective cell line 17a
The replacement destination of the cell corresponding to that row address in DL
Spare cell S2 is selected. And the designated address
Data between the spare cell S2 and the replacement cell
The data is written or written.

Here, each spare decoupling circuit from the signal distribution circuit 21.
Address signal S to the feeders 18 and 20 _RA, S_CAThe output of
Matching circuit 22 matches specified address with defective address
Since it is done after waiting for the decision result to
To the column decoder 14 for the judgment processing time on the path 22
Be behind the output timing of the column address signal CA
Becomes However, the data in the spare memory cell array 17
The word line and the bit line are word lines in the memory cell array 11.
And sufficiently shorter than the bit line, and the spare memory cell array
B The spare cell S2 selection treatment time in 17 can be shortened.
Therefore, the normal address is specified even if the defective address is specified.
There is no delay in the processing time compared to when
Yes. Therefore, the access when the defective address is specified is
Compared with the conventional redundant semiconductor memory device,
Is shortened, which in turn shortens the access speed of semiconductor memory devices.
It is possible to shorten the time.

As described above in detail, according to the semiconductor memory device of this embodiment, the spare memory cell array 17 is provided separately from the memory cell array 11, and the spare decoders 18 and 20 dedicated to the spare memory cell array 17 are provided to specify the defective address. In this case, the spare cell S2 is selected from the spare memory cell array 17 having a small cell capacity. As a result, even if the input of the address signal designating the replacement destination of the defective address is somewhat delayed from the input timing at the time of the normal normal address due to the judgment processing in the coincidence circuit 22, the selection of the replacement destination cell S2 is performed. Is carried out in the spare memory cell array 17 having a small capacity, the total processing time is not much delayed as compared with the case where a normal address is designated. Therefore, the access speed of the semiconductor memory device can be shortened.

The present invention is not limited to the above embodiments, but can be modified as follows without departing from the spirit of the invention. (1) As shown in FIG. 4, the spare cell line 17a is not replaced for each cell line 11a, which is a 1-bit line including the defective cell DS, and only the partial area D including the defective cell DS in the cell line 11a is replaced. May be replaced with. Also in this configuration, the number of normal cells S1 in the cell line 11a is set to 2
^The spare cell S2 may be set to the number of cells divided into ⁿ equal parts. According to this configuration, the defective cell DS that can be relieved
It is possible to reduce the area occupied by the spare memory cell array 17 in proportion to the number. In the case of this configuration, a matching circuit for determining whether or not the designated row address of the row address signal RA belongs to the defective area and whether or not the column address signal CA as in the above embodiment is the defective column address are determined. A matching circuit for judging is provided side by side, and only when a matching signal is inputted from both matching circuits, the signal demultiplexing circuit 21 outputs the respective signals S _RA and S _CA to the preliminary decoders 18 and 20. Good.

(2) In the above embodiment, the spare cell line 17
Although the number of spare cells S2 in a is set to 1 / ⁿ of the number of normal cells S1 in the cell line 11a, it is not limited to 1 / ²ⁿ .

(3) In the above embodiment, the spare cell line 17
The number of the spare cells S2 in a is set to 1 / ⁿ of the number of the normal cells S1 in the cell line 11a, and n = 2 is adopted so that the length of the spare cell line 17a is equal to the length of the cell line 11a. However, the number is not limited to one quarter, and other numbers are
May be set. For example, the length of the spare cell line 17a is 1/2, 1/8, 1/1 of the length of the cell line 11a.
It may be 6 mag.

(4) In the above embodiment, the spare row decoder 1
8 is shared among the respective unit units that are units to which the defective cell line DL is replaced, but a plurality of spare memory cell arrays 17 are provided for each unit unit.
The spare row decoder 18 may be provided for each.

(5) In the above embodiment, the area in the column direction including the defective cell DS is the defective area to be replaced.
A region in the row direction including the may be set as a defect region.
In this case, one bit line in the row direction may be the replacement unit, or only a part of the one bit line in the row direction including the defective cell DS may be the defective region.

(6) The semiconductor memory device to which the present invention is applied is not limited to SRAM. For example, DRAM, EP-
The present invention may be applied to other semiconductor memory devices such as ROM.

(7) The configuration may be such that replacement is possible in both the row direction and the column direction. For example, a matching circuit may be provided for each of the column and the row, and both the row address signal and the column address signal may be determined to determine whether or not they are defective addresses.

(8) One spare column decoder may be used instead of providing the spare column decoder 20 individually for each unit unit to be replaced. The coincidence circuit 22 outputs a 2-bit designation signal SA for designating a unit unit to be replaced to the signal distribution circuit 21, and the designation signal SA is output.
The row address signal S _RA having the 2-bit data of 2) as the high-order bit and the high-order 2 bits of the row address signal RA as the low-order bit may be output to the spare column decoder 20.

The invention grasped from the above embodiment and not described in the scope of the claims will be described below together with the effects thereof. (1) In claim 2, in the spare memory cell array, 2 ⁿ cell lines each having a length 1/2 ⁿ times as long as the defective cell line in the main memory cell array are arranged in a row to form one replacement unit. According to this configuration, one substitution unit is 1
The replacement for each bit line can be efficiently performed.

(2) In claim 2, the spare memory cell array includes a plurality of the replacement units, and the second decoder is shared by the replacement units. With this configuration, the area occupied by the second decoder can be reduced.

(3) The cell lines arranged in the column-arranging direction of one bit line to be replaced, including the defective cell in the main memory cell array in which a large number of normal cells are arranged, are equal to 2 ^n.
A spare memory cell array in which a plurality of spare cell lines having the number of divided cells as spare cells are arranged in multiples of 2 ⁿ and a spare cell line is provided for every 2 ⁿ of the spare cell lines and a spare cell line in the spare memory cell array is selected First to do
, A second decoder for selecting each spare cell on the spare cell line in the spare memory cell array, and a designated address designated by an address signal designating a cell line in the main memory cell array is defective. Determining means for determining whether the address is an address and outputting a coincidence signal when the designated address is a defective address; an address signal for designating each normal cell on the cell line; and a coincidence signal from the determining means And a match signal is input, the upper n bits of the N-bit address data designated by the address signal are output to the first decoder, and the lower (N-n) bits of the address data are output. And a signal distribution means for outputting to the second decoder. According to this structure, the same effects as those of the respective inventions can be obtained.

[0044]

As described above in detail, according to the invention described in claim 1, even if a defective address is designated, the processing time at that time is compared with the processing time when the normal address is designated. Since there is not much delay, the excellent effect that the access speed of the semiconductor memory device can be shortened is achieved.

According to the second aspect of the present invention, since the defective area is replaced with the spare cell line for each normal cell group in which the upper n bits of the address have a common value, the upper n bits of the defective address signal data are replaced by the first n bits. It is possible to select a spare cell for replacement by simply sending the remaining lower bits to the second decoder.

According to the third aspect of the invention, the judging means outputs the upper n bits of the N-bit address signal data for the first decoder and the second address signal,
In the second decoder, the lower (N-
n) bits are output. Therefore, there is an excellent effect that the address data of the address signal can be sent as it is to the upper bit and the lower bit and sent to each spare decoder.

According to the fourth aspect of the present invention, since the defective area uses a cell line which is a 1-bit line as a replacement unit and the defective area is replaced with 2 ⁿ spare cell lines in the spare memory cell array, This has an excellent effect that the defective region of the 1-bit line can be efficiently replaced.

According to the fifth aspect of the invention, since only a part of the cell line including the defective cell is replaced with the spare cell line as the defective region, the normal area other than the defective region in the cell line is replaced. The cell can be used as a normal cell, and the area occupied by the spare memory cell array can be reduced for the number of repair cells.

According to the sixth aspect of the present invention, even in the structure in which the defective region as a replacement unit is set in the column direction,
This has an excellent effect that a defective address can be selected in a relatively short time through the column selection decoder and the row selection decoder.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram of a semiconductor memory device according to an embodiment.

FIG. 3 is an explanatory diagram showing a replacement relationship between defective cell lines and spare cell lines.

FIG. 4 is an explanatory diagram showing a replacement relationship between a defect line and a spare cell line according to another example.

FIG. 5 is a plan view of a conventional semiconductor memory device.

[Explanation of symbols]

 1 Main Memory Cell Array 1a Cell Line 2 Decoder 3 Decoder 4 Spare Memory Cell Array 4a Spare Cell Line 5 Spare Decoder 6 Spare Decoder 7 Judgment Means A1 Address Signal A2 Second Address Signal S1 Normal Cell S2 Spare Cell

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Teruaki Maeda 1844-2, Kozoji-cho, Kasugai-shi, Aichi FUJITSU VIEL SII Corporation

Claims (6)

[Claims] 1. A spare memory cell array for arranging spare cells is provided independently of a main memory cell array for arranging a large number of normal cells, and a dedicated spare decoder for selecting the spare cells is provided in the spare memory cell array. A connection means is provided, and when the designated address designated by the address signal is a defective address, a determining means is provided for outputting to the spare decoder a second address signal designating a replacement destination address in the spare memory cell array. A semiconductor memory device characterized by the above. 2. In the spare memory cell array, when a normal cell in the main memory cell array has a defective cell, a cell line which is a 1-bit line in a longitudinal direction of a defective region which is a replacement unit is represented by a natural number n. 2. The semiconductor memory device according to claim 1, wherein the number of the spare cells is equal to the number of cells divided into 2 ⁿ equal parts, and the spare cell line is a 1-bit line of the spare memory cell array. . 3. The spare decoder includes a first decoder for selecting a spare cell line which is a replacement destination of a defective area including a defective cell in the main memory cell array, and an address in a direction orthogonal to the spare cell line. And a second decoder for selecting
Of the N-bit address data of the address signal to the first decoder, and the lower (N-n) bits of the address data to the second decoder. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is set to 4. The defective area uses the cell line, which is a 1-bit line, as a replacement unit, and the defective area is replaced by 2 ⁿ spare cell lines in the spare memory cell array. The semiconductor memory device according to claim 2 or 3. 5. The defective area is a partial area including a defective cell in the cell line, and the defective area is replaced with a spare cell line in the spare memory cell array, and the address is sent to the judging means. To determine whether or not the address specified by the signal belongs to the defective area,
4. The semiconductor memory device according to claim 2, wherein the second address signal is output when the designated address belongs to a defective area. 6. The cell line and the spare cell line are arranged in a column direction, the first decoder is a column selection decoder, and the second decoder is a row selection decoder. The semiconductor memory device according to claim 3.