JPH087938B2 - Data sample circuit - Google Patents

Description

The present invention relates to a data sampling circuit, and more particularly to a data sampling circuit for reproducing data recorded on a recording medium such as an optical disk.

[Conventional technology]

A conventional data sampling circuit in an optical disc apparatus uses an optical disc as a light source and modulates the laser beam with a pulsed signal that is a binary signal of data to record the optical disc, or an optical disc memory having already recorded information. When reproducing data, in spot recording having information at pit intervals, the reproduced signal from the optical head is once differentiated, and the zero cross of the differentiated signal is detected to pulse the signal.

Also, in the case of width recording having information at the edge of the pit, a comparison circuit compares the reproduction signal from the optical head with the center value signal indicating the value of the center of the reproduction signal. It is pulsing.

Furthermore, as for the sample format which is one method for reproducing the data on the optical disc, a differential detection method is adopted in which the level of the reproduction signal is detected and pulsed.

[Problems to be Solved by the Invention]

However, none of the conventional data sampling circuits described above uses “1” or “0” at the instantaneous signal level at which pulsing is performed without using the total energy indicating the recorded content of the reproduction signal at the time of pulse detection. Is making a decision.

For this reason, since noise is generally superimposed on the reproduced signal, such a conventional data sampling circuit has a drawback that it is highly possible to detect a data value erroneously due to instantaneous noise that is pulsed. Have

Moreover, in such a conventional data sampling circuit, it is expected that the S / N ratio of the signal will deteriorate more and more as the bit density becomes higher in the future, and the bit error rate becomes worse. have.

An object of the present invention is to provide a data sampling circuit capable of performing accurate pulsing even in a reproduced signal on which noise is superimposed by using the total energy indicating the recorded content of the reproduced signal as much as possible at the time of pulse detection. To do.

[Means for solving the problem]

The data sampling circuit of the present invention (A) indicates the difference between the read signal and the center value signal by inputting the read reproduction signal and the center value signal indicating the value of substantially the center level of the reproduction signal. A differential amplifier that generates a difference signal, and (B) outputs an integrated signal obtained by integrating the difference signal from the differential amplifier, and resets the integrated signal by a data sample clock having a phase matched with the reproduction signal. An integrator circuit, (C) a comparison / determination circuit that outputs a determination signal for determining whether the integrated signal is positive or negative by comparing the integrated signal with a zero level, and (D) the data sample clock By performing sampling of the determination signal using the binary signal corresponding to whether the integration signal immediately before resetting is positive or negative, A data holding circuit for holding as reproduction data indicating the content of the reproduction signal.

[Action]

The center value signal is subtracted from the read reproduction signal, the reproduction signal is integrated with a positive value exceeding the center value signal and a negative value less than the center value signal, and whether the integration signal of the integration result is a positive value. Whether the value is negative is judged at the timing of the data sample clock having a phase matched to the reproduced signal, and the integrated signal is reset after determining whether the reproduced data is "1" or "0". .

By doing so, it is possible to determine whether the reproduction data is “1” or “0” by using the total energy indicating the recorded content of the reproduction signal between the data sample clocks,
Moreover, since the influence of noise can be reduced by integrating it, accurate pulsing can be performed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data sampling circuit of the present invention.

FIG. 2 is a signal waveform diagram showing an example of signal operation in the data sampling circuit of this embodiment.

FIG. 2 shows an example of the reproduction signal S1 when the width recording is performed as the recording method.

The data sampling circuit of this embodiment is shown in FIGS.
As shown in the figure, a reproduction signal S1 read from the optical head of the optical disk device, a center value signal S2 indicating a value of a substantially center level of the reproduction signal S1, and a data sample clock having a phase matched with the reproduction signal S1. I am using S3 and.

First, the differential amplifier 1 inputs the reproduction signal S1 and the center value signal S2 to generate a difference signal S4 indicating a difference value obtained by subtracting the center value signal S2 from the reproduction signal S1.

Therefore, the integrator circuit 2 uses the difference signal S4 from the differential amplifier 1.
The integrated signal S5 obtained by integrating is output, and the integrated signal S5 is reset by the data sample clock S3.

Then, the comparison and determination circuit 3 determines whether the integrated signal S5 is positive or negative by comparing the integrated signal S5 with the zero level of the ground signal, and indicates "1" or "0". The judgment signal S6 is output.

In addition, the data holding circuit 4 uses a flip-flop to sample the determination signal S6 by the data sample clock S3, so that the integration signal S5 immediately before resetting is positive or negative. The reproduced binary signal "1" or "0" is the reproduction data indicating the content of the reproduction signal S1.
As S7, the data sample clock S3 is held for one period and the reproduced data S7 is output.

As a result, the data sampling circuit of the present embodiment improves the S / N ratio by using the total energy indicating the recorded content of the reproduced signal as much as possible at the time of pulse detection even in the reproduced signal on which noise is superimposed. Therefore, accurate pulsing is performed with the influence of noise minimized.

〔The invention's effect〕

As described above, the data sampling circuit of the present invention performs accurate pulsing even for a reproduced signal on which noise is superimposed by using the total energy indicating the recorded content of the reproduced signal as much as possible at the time of pulse detection. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the data sampling circuit of the present invention, and FIG. 2 is a signal waveform diagram showing an example of signal operation in the data sampling circuit of the present embodiment. 1 ... Differential amplifier, 2 ... Integrator circuit, 3 ... Comparison judgment circuit, 4 ... Data holding circuit, S1 ... Reproduction signal, S2 ... Center value signal, S3 ... Data sample clock, S4 ... Difference signal, S5 ... Integral signal, S6 ... Judgment signal, S7 ... Playback data.

Claims (1)

[Claims] (A) A difference signal indicating a difference between the read signal and the center value signal is input by inputting the read reproduction signal and a center value signal indicating a substantially center level value of the reproduction signal. A differential amplifier for generating, (B) an integrating circuit which outputs an integrated signal obtained by integrating the difference signal from the differential amplifier, and resets the integrated signal by a data sample clock having a phase matched with the reproduction signal, (C) a comparison and determination circuit that outputs a determination signal for determining whether the integrated signal is positive or negative by comparing the integrated signal with a zero level, (D) using the data sample clock By sampling the determination signal, a binary signal corresponding to whether the integrated signal immediately before resetting is positive or negative is displayed to indicate the content of the reproduction signal. Data sampling circuit, characterized in that it comprises a data holding circuit, for holding the reproduced data.