JPH0879284A - Storing method for address of transmission terminal - Google Patents

Abstract

PURPOSE: To provide an economical address storage means which can be constituted of less number of parts by charging a reference capacitor and deciding the address of a transmission terminal from the ratio of first time and second time until reaching a prescribed voltage. CONSTITUTION: This is the method for storing the address of the transmission terminal 5N of a multi-drop transmission system. The reference capacitor C is charged from one electrode P00 of the two electrodes P00 and P01 for outputting an equal constant DC voltage serially through a first registor RS. Then, the first time until the voltage between both terminals of the capacitor C reaches the prescribed voltage from the state of 0 volt is measured. Also, the reference capacitor C is charged from the other electrodes P01 serially through a second resistor VR and the second time until the voltage between both terminals of the capacitor C reaches the prescribed voltage is measured. Then, the address of the transmission terminal 5N is decided from the ratio of the first time and the second time. Thus, the address storage means with less number of terminals and less number of the parts is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal of a so-called multi-drop transmission system, which is composed of one transmission source and one or more transmission terminals which simultaneously receive the addresses of serial signals transmitted from the transmission source to the transmission terminal. In the method of storing the address of the transmission terminal in the transmission system, or in the method of storing the address of the transmission terminal of the similar multi-drop transmission method that uses any one transmission terminal as the source, the address of the transmission terminal that does not lose its memory even in the event of a power failure Memory method.

[0002]

2. Description of the Related Art FIG. 4A shows an example of a connection relationship between a transmission source and a transmission terminal connected by a multi-drop transmission system.
In the figure, 4 is a transmission source, 51, 52 and 5N are transmission terminals. The transmission source 4 and the transmission terminals 51, 52 and 5N exchange signals via a serial signal line and are transmitted from the transmission source 4. Address signals are simultaneously received by the respective transmission terminals 51-5N. It should be noted that the transmission source is not always limited to a specific one, and each transmission terminal also has a function as a transmission source, and in some cases, there is a system that functions as a transmission source and in other cases as a transmission terminal. In this system as well, at one point in time, the relationship between the transmission source and the transmission terminal is the same as in the system represented by (a) in FIG.

FIG. 4B is a block diagram showing the main part of one transmission terminal, and mainly shows the method of setting the address of this transmission terminal. In the figure, 51 is a transmission terminal,
It is composed of a control calculation means 1, a transmission / reception circuit 2, and an address setting device A1. The control calculation means 1 receives a signal externally input to the terminal RX through the transmission / reception circuit 2 to the terminal RxD, and if the received signal is a signal for controlling an operating device such as a motor (not shown), the operation is performed. Signal converted to a signal suitable for the control of the device and output from an output circuit (not shown) and processed by the transmission terminal 51, for example, a signal such as an operation switch or sensor (not shown) connected to the transmission terminal 51 For example, the signal is transmitted from the terminal TxD via the transmission / reception circuit 2 via the terminal Tx.

The address setter A1 has a resistance Ri (i is a number 0 to 2)
And switch Si (i is the number 0 to 2)
One terminal of Si is connected to the reference potential GND of the power supply (potential corresponding to 0 of the binary signal), the other terminal is connected to one terminal of the resistor Ri, and the input of the control calculation means 1 from this connection point. It is connected to the terminal PIi (i is number 0 to 2). The terminal of the resistor Ri that is not connected to the switch Si is the positive electrode of the power supply.
It is connected to Vcc (1 of binary signal). When the switch Si is closed, the connection point between this switch and the resistor Ri is short-circuited to the reference potential GND, so that the signal value 0 is input to the input terminal PIi of the control calculation means 1. When the switch Si is open, the connection point between this switch and the resistor Ri is connected to the positive terminal VCC of the power supply via the resistor Ri, and the binary signal 1 is input to the input terminal PIi of the control calculation means 1. It As described above, the signal representing the address can be input to the input terminal PIi of the control calculation means 1 by opening and closing the switch Si.

FIG. 4 (c) shows another example of address setting. In the figure, 1 is a control operation means, 2 is a transmission / reception circuit,
It is the same as the one with the same reference numeral shown in FIG. A2 is an address setting circuit, which consists of a serial EEPROM that is a non-volatile memory element that electrically erases the contents to be stored, performs data input / output serially in bit units, and Store the address of the transmission terminal in
When necessary, send a pulse signal from pin PI3, and read the data representing the address stored in synchronization with this pulse signal from pin PI5 for use.

[0006] In addition, there is also a method of storing the address of the transmission terminal in a RAM that prevents loss of memory at the time of power failure by a battery.

[0007]

As described above, in the method of setting the address by the switch of FIG. 4 (b), which is one of the conventional methods, the required number of addresses is, for example, 10 In this case, four sets of switch circuits are required, the installation space is increased, and a large number of input signal terminals of the control calculation means of the transmission terminal are exclusively used for address input. As for switches, there are some small ones, and if a small one is used, the installation space can be saved, but on the other hand, there is a drawback that handling is difficult at the time of address setting because it is small. As a second example, the method of using the EEPROM and the method of using the battery, which are mentioned above, are difficult to be expensive.

Because of the above-mentioned circumstances, the present invention provides a method for realizing the storage of an address by a circuit in which the data representing the stored address can be input from a small number of terminals and the address can be stored easily at a low cost. To provide.

[0009]

In order to achieve the above-mentioned object, according to the present invention, one sender and one or more receivers for simultaneously receiving the serial signal address transmitted from the sender to the transmission terminal are provided. In the address storage method of the transmission terminal of the signal transmission system of the multi-drop transmission method consisting of the transmission terminal, from one electrode of the two electrodes that output a constant voltage of an equal value measured with reference to the DC reference potential. First time for charging a reference capacitor, one of electrodes of which is connected to a reference potential via a first resistor in series, until the voltage between both terminals of the capacitor reaches a predetermined voltage from 0 volt. To measure. A second capacitor is charged from the other electrode through a second resistor to a reference capacitor until the voltage between both terminals of the capacitor reaches a predetermined voltage from 0 volt.
To measure the time. And the measured first time and second
It is characterized in that the address of the transmission terminal is determined from the ratio of the times.

Further, the emitter of the transistor is connected to the terminal connected to the reference potential of the power source of the reference capacitor, and the resistor connected in series to the collector of the transistor is connected to the terminal not connected to the reference potential of the reference capacitor. It is characterized in that the charge / discharge of the reference capacitor is controlled by controlling the base current to the base of the transistor.

Further, the predetermined voltage is detected by the output voltage of the Schmitt circuit in which the potential of the terminal connected to the reference potential of the reference capacitor is used as the reference potential and the voltage of the terminal not connected to the reference potential of the reference capacitor is used as the input voltage. It is characterized by doing. Furthermore, the second resistor has a resistance value changing means capable of easily changing the resistance value,
Further, the second resistance is characterized by having means for fixing the resistance value after the change.

[0012] Further, a communication means which is detachable from the transmission terminal and communicates with the transmission terminal when attached to the transmission terminal,
Display means for displaying the address represented by the address signal based on the resistance value of the second resistance transmitted through the communication means, and the resistance value changing means detachable from the resistance value changing means for the resistance value of the second resistance. The address setter having the resistance driver for changing the resistance value of the second resistance via the address setting device and the operation input means causes the address based on the resistance value of the second resistance displayed on the display means to be the planned address. In addition, the resistance driver is controlled via the operation input means to adjust the resistance value of the second resistor.

[0013]

The first time is the time required to charge the reference capacitor through the first resistor in series from a constant DC voltage until the voltage between both terminals of this capacitor reaches a predetermined voltage from 0 volt. . Therefore, from the theory of electric circuits, the first time can be calculated by the following formula.

First time = −C1 × R1 × log (1−V / E) where C1 is the capacitance of the reference capacitor (unit F), R
1 is the resistance value of the first resistor (unit: Ω), V is a predetermined voltage, E
Is a constant voltage of direct current for a second time, through a second resistor in series with a reference capacitor,
This is the time required for charging from a constant DC voltage to a predetermined voltage from the voltage between both terminals of this capacitor to 0 V. Therefore, from the theory of electric circuits, the second time can be calculated by the following formula.

Second time = −C1 × R2 × log (1−V / E) where R2 is the resistance value of the second resistance (unit: Ω), and other symbols are the symbols used for the calculation of the first period. Therefore, (first time) / (second time) = (R1) / (R2) That is, the ratio of the first time and the second time is the resistance value of the first resistance and the resistance value of the second resistance. Equal to the ratio of. Since the first resistance and the second resistance are unique to the transmission terminal having this resistance, the ratio of the resistance values of both is determined in correspondence with the address of this transmission terminal, and the ratio of the resistance values is The address of the transmission terminal can be determined from the ratio of 1 hour to the second time.

Further, by controlling the current to the base of the transistor connected between the terminals of the reference capacitor by the control calculation means, and injecting a sufficient current into the base, the carrier is saturated between the emitter and collector of the transistor. In this state, the electric charge of the reference capacitor is rapidly discharged through the transistor, and the terminal voltage across the reference capacitor becomes 0 V in a short time.

Further, the predetermined voltage is detected by the output voltage of the Schmitt circuit in which the potential of the terminal connected to the reference potential of the reference capacitor is used as the reference potential and the voltage of the terminal not connected to the reference potential of the reference capacitor is used as the input voltage. Therefore, when the charging voltage of the capacitor exceeds the threshold voltage of the Schmitt circuit, the output voltage of the Schmitt circuit suddenly changes from the voltage representing one of the binary signals to the voltage representing the other value, and the predetermined voltage can be detected by this change. Therefore, the predetermined voltage is applied as a voltage equal to the threshold voltage of the Schmitt circuit.

Furthermore, it is preferable that the second resistor has a variable resistance value and can be fixed to the changed resistance value. Further, when the resistance driver of the address setting device is attached to the resistance value changing means of the second resistance of the transmission terminal, the address signal determined by the first resistance and the second resistance of the transmission terminal is transmitted to the address setting device, and the address is changed. It is displayed on the display means of the address setting device. If the address does not match the expected address of the transmission terminal, a signal for increasing or decreasing the address is input to the address setting device from the operating means of the address setting device. The address setting device controls the resistance driver according to the operation input, changes the value of the second resistance, and the address based on the changed result is displayed on the display means of the address setting device.

[0019]

【Example】

(Embodiment 1) FIG. 1 shows an embodiment of an address storage method of a transmission terminal according to the present invention. In the figure, 5N is a transmission terminal, which is composed of the elements of the control calculation means 1, the transmission / reception circuit 2, and the address storage circuit A11. Figure 4 among the elements that make up the transmission terminal 5N
The same parts as those shown in are attached with the same notations and an explanation thereof will be omitted. In the following description, 2 corresponding to 0 or 1
The value signal is simply referred to as a signal.

The address storage circuit A11 has a resistance RS as a first resistance (hereinafter referred to as a first resistance RS) and a variable resistance VR as a second resistance (hereinafter referred to as a second resistance VR). , Diode D0, D1, Schmitt circuit 3 and resistor R
i, RB, a transistor Tr, and a capacitor C (referred to as capacitor C in the following description) serving as a reference capacitor.

One terminal of the capacitor C is connected to the reference potential terminal GND of the power source (the terminal of the potential representing 0 of the binary signal). One terminal of the first resistor RS is connected to the output terminal PO0 of the control calculation means 1, the other terminal is connected to the anode of the diode D0, and the cathode of the diode D0 is not connected to the reference potential terminal GND of the capacitor C. The second resistor RS and the diode D0 are connected to the terminal by the voltage between the output signal terminal PO0 of the control calculation means 1 and the reference potential terminal GND.
A charging circuit for the capacitor C via the series circuit of is constructed.

One terminal of the second resistor VR has a control calculation means 1
Is connected to the output terminal PO1 of the
Connected to the anode of, the cathode of the diode D1 is connected to the terminal of the capacitor C that is not connected to the reference potential terminal GND, and the voltage between the output signal terminal PO1 of the control calculation means 1 and the reference potential terminal GND causes A charging circuit for the capacitor C is configured via a series circuit of two resistors VR and the diode D1. The diodes D0 and D1 are provided to block the current flowing from the capacitor C side to the output signal terminal PO0 or PO1 of the control calculation means 1, and the control calculation means 1 has the ability to block the reverse flow of current. If sufficient, this diode can be omitted.

The Schmitt circuit 3 has its input terminal connected to the terminal of the capacitor C not connected to the reference voltage terminal GND, and its output terminal connected to the input terminal PI0 of the control calculation means 1 so as to charge the capacitor C (reference voltage). When the voltage between the terminal connected to the voltage terminal GND and the other terminal) exceeds the threshold voltage value of this Schmitt circuit, 1 of the binary signal is output to the control calculation means 1 and the charging voltage of the capacitor C The predetermined voltage to be detected is given as a voltage value equal to the threshold voltage of the Schmitt circuit.

The emitter of the transistor Tr is a reference potential terminal
It is connected to GND and the collector is connected through resistor Ri to the terminal on the side not connected to the reference potential terminal of Condenco C,
The output signal terminal of the control calculation means 1 whose base is through the resistor RB
Connected to PO2. When the output signal from the terminal PO2 of the control calculation means 1 is 0, the current flowing into the base becomes 0,
The resistance value between the collector and the emitter of the transistor Tr becomes extremely high, and practically, the same effect as that of the circuit of the transistor Tr in parallel with the capacitor C being opened is brought about. When the value of the output signal of the output signal terminal PO2 of the control calculation means 1 becomes 1, a positive DC voltage corresponding to 1 of the signal is output from this terminal, which is sufficient to saturate the transistor Tr from this terminal. The base current is supplied, the resistance value between the emitter and collector of the transistor Tr is reduced, and the electric charge accumulated in the capacitor C is rapidly discharged by the circuit passing through the transistor Tr.

FIG. 2 shows the voltage of the terminal on the side not connected to the reference potential terminal GND of the capacitor C whose reference is the potential of the reference potential terminal GND of the power supply, where the horizontal axis is the time coordinate and the vertical axis is the voltage value coordinate. It is a diagram showing the characteristics of (the voltage is called the charging voltage of the capacitor C in the following description because this voltage is equal to the voltage across the terminals of the capacitor). In the figure, the curve
V1 is a curve showing the change in the charging voltage of the capacitor C with time when the capacitor C is charged via the first resistor RS, and the curve V2 is the case where the capacitor C is charged via the second resistor VR. Is a curve showing the change of the charging voltage of the capacitor C with respect to time, Vt is the threshold voltage of the Schmitt circuit 3, and is equal to the predetermined voltage of the charging voltage of the capacitor C to be detected as described above.

A method of determining an address will be described with reference to FIGS. 2 and 1. First, the signal value 1 is output from the output signal terminal P02 of the control calculation means 1 to discharge the electric charge accumulated in the capacitor C. In this state, the charging voltage of the capacitor C becomes 0 volt. Next, at time 0, the signal value of the output signal terminal PO2 is set to 0, and the output signal from the output signal terminal PO0 of the control calculation means 1 is set to 1. The capacitor C is charged with the voltage of the output signal terminal PO0 via the series circuit of the first resistor RS and the diode D1, and the charging voltage increases along the curve V1 with the passage of time. The curve V1 can be expressed by the following equation according to the electric circuit theory.

V1 = E1 × (1−exp− (t / (C1
× R1))) where E1 is the voltage obtained by subtracting the voltage drop caused by the current flowing in the quasi-direction of the diode D0 from the voltage of the terminal PO0 with reference to the reference voltage terminal GND when the signal value 1 is output from the terminal PO0. , C1 is the electrostatic capacity of the capacitor C (unit F), R1 is the resistance value of the first resistor RS (unit Ω), t is the elapsed time from time 0 (unit second) From the formula expressing V1 shown above, The time T1 as the first time until the charging voltage of the capacitor C reaches the threshold value voltage Vt of the Schmitt circuit 3 is obtained by the following equation.

[0028]

[Equation 1] T1 = -C1 * R1 * log (1-Vt / E1) Next, when the capacitor C is charged from the second resistor VR in the same manner as the operation of charging the capacitor C from the first resistor, the capacitor C is charged. The voltage rises along the curve V2 in FIG. The equation representing the curve V2 is similar to the equation representing the curve V1 and is represented by the following equation.

V2 = E2 × (1−exp− (t / (C1
× R2))) where E2 is the voltage obtained by subtracting the voltage drop caused by the current flowing in the quasi-direction of diode D1 from the voltage of terminal PO1 with reference to the reference voltage terminal GND when signal value 1 is output from terminal PO1. , R2 is the resistance value of the second resistor VR (unit: Ω), and the time T2 as the second time until the charging voltage of the capacitor C reaches the threshold value voltage Vt of the Schmitt circuit 3 from the equation expressing V2 shown above. Is calculated by the following equation.

[0030]

## EQU00002 ## T2 = -C1 * R2 log (1-Vt / E2) The terminal voltage when the signal value 1 is output from the terminal PO0 and the terminal PO1 is the same as that of the terminal PO0 and the terminal PO1. 1 circuit, and electric power is supplied from the same power source. Therefore, the voltages output from both output terminals are practically equal. Further, by using the diodes D0 and D1 having the same specifications, both diodes are used in the same environment, so that the voltage drop due to the quasi-directional current can be made almost equal. Therefore, the voltage E1 and the voltage E2 can be practically equal. Therefore, assuming that E1 and E2 are equal, the first time T1 and the second time T1
When the ratio to the time T2 is calculated from the equations 1 and 2, T2 / T1 = R2 / R1 and the ratio between the first time and the second time is equal to the ratio between the first resistance and the second resistance. Therefore, in the control calculation means 1, the signal value 1 is output to the output signal terminal PO0 and then the input signal terminal PI0
Input signal terminal PI0 after outputting signal value 1 to output signal terminal PO1 for the first time T1 until signal value 1 is input to
When the time T2 until the signal value 1 is input is measured as the second time and the ratio of the first time and the second time is obtained, the resistance value of the first resistor RS and the resistance value of the second resistor VR are calculated. Since a ratio equal to the ratio to the transmission terminal 5N is obtained, by defining the ratio of the resistance values of the first resistor RS and the second resistor VR in correspondence with the address of the transmission terminal 5N, the transmission terminal 5N can be constantly used even during a power failure. The address of can be stored.

Table 1 shows an example in which the ratio of the resistance values of the first resistor RS and the second resistor VR is defined in correspondence with the address of the transmission terminal 5N.
In the table, the address is entered in the left column of the table, and the magnification of the resistance value of the second resistor VR when the first resistor RS corresponding to the address in the left column is used as a reference is shown in the right column. For example, when the resistance value of the second resistor VR is set in the range of 1.8 to 2.2 times that of the first resistor RS, the address corresponds to this ratio.

[0032]

[Table 1]

(Embodiment 2) FIG. 3 shows an embodiment of a method for setting the second resistance according to the method of the present invention. In the figure, 5N1 is a transmission terminal, and
1 is the same as the transmission terminal 5N shown in FIG. 1 except that the second resistance RV is provided with resistance value changing means 31 for changing the resistance value of this resistance, and constitutes the transmission terminal 5N. The same parts as those forming the transmission terminal 5N shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted. The address storage circuit A12 is the same as the address storage circuit A11 shown in FIG. 1 except that the resistance value changing means 31 is provided. The resistance value changing means 31 is a mechanism that changes the resistance value of the second resistance RV when the rotary shaft 32 engaged with the external rotary shaft is rotated.

B1 is an address setting device, and the control calculation means 31,
Transmission / reception circuit 21, display means 41 controlled by control calculation means 31, operation input means 42 for inputting an operation signal to control calculation means 31, resistance drive machine controlled by control calculation means 31
It consists of 43 and. Further, the resistance drive machine 43 is driven by the stepping motor 431 and the stepping motor 431 and is transmitted to the transmission terminal.
The rotary shaft 43 engaging with the rotary shaft 32 of the resistance value changing means 31 of 5N1
And a motor controller 434 for driving the stepping motor 431 to control the rotation direction and the rotation speed based on the signal from the control calculation means 31.

The transmission terminal 5N1 and the address setting machine B1 can be mechanically attached and detached by a mechanism (not shown).
If you block the communication between 1 and devices other than the address setting machine B1 and install the address setting machine B1 on the transmission terminal 5N1,
Transmission terminal TX of transmission terminal 5N1 is reception terminal RX of address setter B1
Connected to S, the receiving terminal RX of the transmission terminal 5N1 is the address setter.
An address signal that is connected to the transmission terminal TXS of B1 and represents the address based on the address storage circuit A12 from the transmission terminal 5N1 is the address setter B1.
When this signal is input, the address setter B1 displays the address based on the input address signal on the display means 41. Further, the rotation shaft 433 of the speed reduction mechanism 432 engages with the rotation shaft 32 of the resistance value changing means 31 of the transmission terminal 5N1. If the address displayed on the display unit 41 is smaller than the address planned for the transmission terminal 5N1, when the push button switch 421 of the operation input unit 42 is pressed, the signal from this switch is input and the control calculation unit 31 controls the motor. Motor through machine 434
Rotate 431 and change the resistance value of the second resistor RV in the direction of increasing the address. If the displayed address is larger than the planned address, the push button switch 42 of the operation input means 42
When 2 is pressed, the signal from this switch is input, and the control calculation means 31 rotates the stepping motor 431 via the motor controller 434, and the second resistance in the direction of decreasing the address.
Change the resistance value of RV. As described above, the address of the transmission terminal 5N1 can be set to the planned address while reading the display of the address setting device B1.

[0036]

As described above, according to the method of the present invention, one transmission source and one or more transmission terminals which simultaneously receive the serial signal address transmitted from the transmission source to the transmission terminal are provided. In the address storage method of the transmission terminal of the multi-drop transmission system, by charging a reference capacitor through a first resistor from one electrode of two electrodes that output a constant voltage of the same direct current, this capacitor By measuring the first time until the voltage between the two terminals of the capacitor reaches a predetermined voltage from the state of 0 volt, and charging the reference capacitor from the other electrode through the second resistor, both ends of this capacitor A second time from when the voltage between the terminals is 0 volt to a predetermined voltage is measured, and the address of the transmission terminal is determined from the ratio of the first time and the second time. Therefore, the number of terminals required to determine the address is the terminal for supplying a constant voltage to the circuit of the first resistor, the terminal for supplying a voltage to the second resistor, and the reference capacitor except the terminal connected to the reference potential of the power supply. Since only three terminals for detecting the voltage between the terminals are required, the circuit required for address storage can be configured with a small number of parts, which is a fixed number of parts regardless of the number of addresses set, so that the installation space An economical means of address storage is provided both in terms of price and price.

According to the method of the present invention as set forth in claim 2, the emitter of the transistor is connected to the terminal connected to the reference potential of the power source of the reference capacitor, and the resistor connected in series to the collector of the transistor is connected. By connecting to the terminal that is not connected to the reference potential of the reference capacitor and controlling the base current to the base of the transistor, the charge and discharge of the reference capacitor is controlled, so by discharging the reference capacitor through the transistor, after reading the address. The address can be read subsequently with only a short time interval.

Further, according to the method of the present invention as set forth in claim 3, the potential of the terminal connected to the reference potential of the reference capacitor is used as the reference potential, and the voltage of the terminal not connected to the reference potential of the reference capacitor is input. Since the predetermined voltage is detected by the output voltage of the Schmitt circuit, which is a voltage, the predetermined voltage necessary for determining the address can be obtained as a reliable binary signal, and the address can be surely detected.

Furthermore, according to the method of the present invention as set forth in claim 4, the second resistor has a resistance value changing means capable of easily changing the resistance value, and the second resistor is changed. Since it has a means for fixing the resistance value of
In the transmission terminals manufactured in the same manner, it is possible to set different addresses only by changing the resistance value of the second resistance by the resistance value changing means, and it is possible to save the time and effort to manufacture the transmission terminals with different specifications.

According to the fifth aspect of the invention, it is detachable from the transmission terminal, and when it is attached to the transmission terminal, the communication means communicates with the transmission terminal, and the information is transmitted via the communication means. The resistance value of the second resistor is displayed via the display means for displaying the address represented by the address signal based on the resistance value of the second resistor and the resistance value changing means detachable from the resistance value changing means for the resistance value of the second resistor. By the address setting device having the resistance drive machine to be changed and the operation input means, the resistance drive is performed via the operation input means so that the address based on the resistance value of the second resistance displayed on the display means becomes the planned address. Since the controller controls the resistance value of the second resistor, the present location of the address set in the transmission terminal can be clearly read by the display means,
Moreover, the address can be easily set. Further, since the address setting device can be shared by a large number of transmission terminals, the cost required for the address setting is small for each transmission terminal, and the address setting can be performed reliably and easily, which brings about a sufficient economic effect.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a transmission terminal to which an address storage method of the present invention is applied.

FIG. 2 is a diagram explaining an address storage method in the transmission terminal shown in FIG.

FIG. 3 is a diagram showing an embodiment of an address determination method stored in a transmission terminal to which the method of the present invention is applied, in the address storage method of the transmission terminal according to the method of the present invention.

4A and 4B are diagrams for explaining an address storage method of a conventional transmission terminal, where FIG. 4A is a diagram for explaining the need for address storage in a transmission terminal of a multi-drop transmission system, and FIG. Figure showing address storage method, (c) shows address storage method of transmission terminal using electrically erasable nonvolatile memory

[Explanation of symbols]

 5N Transmission terminal 1 Control calculation means 2 Transmission / reception circuit A11 Address storage circuit C Reference capacitor RS1 1st resistance RS2 2nd resistance 3 Schmitt circuit

Claims (5)

[Claims] 1. The address of a transmission terminal of a signal transmission system of a multi-drop transmission system, which comprises one source and one or more transmission terminals which simultaneously receive the addresses of serial signals transmitted from the source to the transmission terminal. In the storage method, one of the two electrodes that outputs a constant voltage having an equal value, which is measured with reference to a direct current reference potential, is connected to the reference potential via one of the first resistors in series. The first time it takes for the voltage between both terminals of this capacitor to reach a predetermined voltage from the state of 0 volt is charged, and the reference voltage is measured from the other electrode through the second resistor. The second time when the capacitor is charged and the voltage between both terminals of this capacitor reaches the specified voltage from the state of 0 volt.
The address storage method of the transmission terminal, wherein the address of the transmission terminal is determined from the ratio of the measured first time and the measured second time. 2. The address storage method for a transmission terminal according to claim 1, wherein the emitter of the transistor is connected to a terminal connected to the reference potential of the power source of the reference capacitor, and the resistor connected in series to the collector of the transistor is connected. An address storage method for a transmission terminal, characterized in that charging and discharging of a reference capacitor is controlled by connecting to a terminal not connected to a reference potential of a reference capacitor and controlling a base current to the base of the transistor. 3. The address storage method for a transmission terminal according to claim 1, wherein a potential of a terminal connected to a reference potential of a reference capacitor is used as a reference potential, and a voltage of a terminal not connected to the reference potential of the reference capacitor is input. A method for storing an address of a transmission terminal, characterized in that a predetermined voltage is detected by the output voltage of the Schmitt circuit which is a voltage. 4. The address storage method for a transmission terminal according to claim 1, wherein the second resistor has a resistance value changing means capable of easily changing the resistance value, and the second resistor has a resistance after changing. An address storage method for a transmission terminal, characterized in that it has means for fixing the resistance value. 5. The transmission terminal address storage method according to claim 4, wherein the transmission terminal is detachable, and when the transmission terminal is attached to the transmission terminal, communication means communicates with the transmission terminal, and transmission is performed via the communication means. The display means for displaying the address represented by the address signal based on the resistance value of the second resistance, and the resistance value changing means attachable to and detachable from the resistance value changing means for the resistance value of the second resistor An address setting device having a resistance driving machine for changing the resistance value and an operation input means is operated via the operation input means so that the address based on the resistance value of the second resistance displayed on the display means becomes the planned address. Controlling the resistance driver to adjust the resistance value of the second resistance.