JPH0878797A - Base board for mounting high-frequency device - Google Patents
Base board for mounting high-frequency deviceInfo
- Publication number
- JPH0878797A JPH0878797A JP23943494A JP23943494A JPH0878797A JP H0878797 A JPH0878797 A JP H0878797A JP 23943494 A JP23943494 A JP 23943494A JP 23943494 A JP23943494 A JP 23943494A JP H0878797 A JPH0878797 A JP H0878797A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductor line
- characteristic impedance
- layer
- lower insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高速で作動させる高周
波デバイスを収容するパッケージの本体等を構成する高
周波デバイス実装用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency device mounting substrate which constitutes a main body of a package which houses a high-frequency device which operates at high speed.
【０００２】[0002]
【従来の技術】高集積化された高周波用の半導体チップ
等のデバイスを収容する多ピン構造のパッケージとし
て、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケ
ージが開発され、使用されている。2. Description of the Related Art A BGA (Ball Grid Array) package has been developed and used as a package having a multi-pin structure for accommodating devices such as highly integrated high frequency semiconductor chips.
【０００３】ＢＧＡパッケージは、図４に示したよう
に、その本体を構成する基板１０下面に基板１０に備え
た信号線路３０、電源線路（図示せず）又はグランド線
路５４に電気的に接続された外部接続端子２０を複数個
格子状に並べて備えている。外部接続端子２０表面に
は、はんだバンプ２２を半球状に形成している。そし
て、基板１０下面の複数の外部接続端子２０をパッケー
ジ実装用のボード表面の接続端子（図示せず）にそれぞ
れ重ね合わせて、それらの外部接続端子２０をボードの
接続端子にはんだバンプ２２を用いてそれぞれはんだ付
け接続することにより、パッケージをボードに表面実装
できるようにしている。As shown in FIG. 4, the BGA package is electrically connected to the signal line 30, the power line (not shown) or the ground line 54 provided on the substrate 10 on the lower surface of the substrate 10 which constitutes the main body. A plurality of external connection terminals 20 are arranged in a grid pattern. A solder bump 22 is formed in a hemispherical shape on the surface of the external connection terminal 20. Then, the plurality of external connection terminals 20 on the lower surface of the substrate 10 are respectively overlapped with the connection terminals (not shown) on the surface of the board for mounting the package, and the solder bumps 22 are used as the connection terminals of the board. The package can be surface-mounted on the board by soldering each.
【０００４】このＢＧＡパッケージにおいては、その本
体を構成する基板１０を、セラミック等からなる絶縁層
１２を複数積層して形成している。基板の絶縁層１２間
には、メタライズ等からなるグランド層５０を薄層状に
連続して広く備えている。基板１０の上面には、メタラ
イズ等からなる細帯状の信号線路３０を備えている。そ
して、信号線路３０をその下方のグランド層５０により
マイクロストリップ線路構造に形成して、信号線路３０
の特性インピーダンスを所定値の５０Ω等にマッチング
させている。In this BGA package, the substrate 10 constituting the main body of the BGA package is formed by laminating a plurality of insulating layers 12 made of ceramic or the like. Between the insulating layers 12 of the substrate, a ground layer 50 made of metallization or the like is continuously and widely provided in the form of a thin layer. A strip-shaped signal line 30 made of metallization or the like is provided on the upper surface of the substrate 10. Then, the signal line 30 is formed into a microstrip line structure by the ground layer 50 thereunder, and the signal line 30
The characteristic impedance of is matched with a predetermined value of 50Ω or the like.
【０００５】この基板上面の信号線路３０の特性インピ
ーダンスＺ0 の値は、次の式から得られることが知られ
ている。It is known that the value of the characteristic impedance Z 0 of the signal line 30 on the upper surface of the substrate is obtained from the following equation.
【０００６】[0006]
【数１】 [Equation 1]
【０００７】数１の式において、信号線路３０の幅ｗと
その厚さｔ、信号線路３０とグランド層５０との間の距
離ｈ、即ち絶縁層１２の層厚ｈは、図６に示した部位を
それぞれ示している。In the equation (1), the width w and the thickness t of the signal line 30 and the distance h between the signal line 30 and the ground layer 50, that is, the layer thickness h of the insulating layer 12 are shown in FIG. Each part is shown.
【０００８】基板１０には、タングステンメタライズ等
のメタライズを充填したビア等からなる円柱状の導体線
路６０を、基板１０を構成する複数の絶縁層１２を上下
に連続して貫通させて備えている。導体線路６０の上下
端は、基板上面の信号線路３０と基板下面の所定の外部
接続端子２０とにそれぞれ一連に接続している。導体線
路６０と交叉するグランド層５０部分には、図５に示し
たように、円形状の透孔５２を、導体線路６０を中心に
開口している。そして、導体線路６０をグランド層５０
により擬似同軸線路構造に形成している。The substrate 10 is provided with a cylindrical conductor line 60 composed of vias or the like filled with metallization such as tungsten metallization, in which a plurality of insulating layers 12 constituting the substrate 10 are continuously penetrated vertically. . The upper and lower ends of the conductor line 60 are connected in series to the signal line 30 on the upper surface of the board and the predetermined external connection terminals 20 on the lower surface of the board. In the portion of the ground layer 50 that intersects with the conductor line 60, as shown in FIG. 5, a circular through hole 52 is opened centering on the conductor line 60. Then, the conductor line 60 is connected to the ground layer 50.
To form a pseudo coaxial line structure.
【０００９】このグランド層の透孔５２に遊挿した導体
線路部分６０ａの特性インピーダンスＺ0 の値は、次の
式から得られることが知られている。It is known that the value of the characteristic impedance Z 0 of the conductor line portion 60a loosely inserted in the through hole 52 of the ground layer can be obtained from the following equation.
【００１０】[0010]
【数２】 [Equation 2]
【００１１】数２の式において、グランド層の透孔５２
の内径Ｄ、円柱状をした導体線路６０の外径ｄは、図５
に示した部位をそれぞれ示している。In the equation (2), the through hole 52 in the ground layer
The inner diameter D of the column and the outer diameter d of the cylindrical conductor line 60 are as shown in FIG.
The parts shown in are respectively shown.
【００１２】グランド層５０は、基板の最上層の絶縁層
１２より下方の複数の絶縁層１２に上下に連続して貫通
させて備えたグランド線路５４を介して、基板下面の所
定の外部接続端子２０に一連に接続していて、グランド
層５０を接地できるようにしている。The ground layer 50 is provided with a predetermined external connection terminal on the lower surface of the substrate through a ground line 54 which is vertically penetrated through a plurality of insulating layers 12 below the uppermost insulating layer 12 of the substrate. It is connected to 20 in series so that the ground layer 50 can be grounded.
【００１３】グランド層５０に開口した透孔５２は、そ
の内径を数２の式のＤから得られる大きさに形成してい
る。この数２の式によれば、基板の絶縁層１２が比誘電
率εr が９．５のアルミナセラミックで形成されてい
て、導体線路６０の外径が０．１ｍｍのときに、導体線
路６０の特性インピーダンスＺ0 を５０Ωにマッチング
させようとする場合には、グランド層５０に開口する透
孔５２の内径Ｄを約１．３０８ｍｍとすれば良いことが
判る。この数２の式を用いてグランド層の透孔５２の内
径Ｄを設定した場合には、グランド層の透孔５２に遊挿
した導体線路部分６０ａの特性インピーダンスを数２の
式から得られる所定値のＺ0 に正確にマッチングさせる
ことができる。The through hole 52 opened in the ground layer 50 has an inner diameter of a size obtained from D of the equation (2). According to the equation (2), when the insulating layer 12 of the substrate is made of alumina ceramic having a relative permittivity ε r of 9.5 and the outer diameter of the conductor line 60 is 0.1 mm, the conductor line 60 In order to match the characteristic impedance Z 0 of 50 to 50Ω, it is understood that the inner diameter D of the through hole 52 opening in the ground layer 50 should be about 1.308 mm. When the inner diameter D of the through hole 52 in the ground layer is set by using the expression of the mathematical expression 2, the characteristic impedance of the conductor line portion 60a loosely inserted in the through hole 52 of the ground layer is determined by the expression of the mathematical expression 2. It can be matched exactly to the value Z 0 .
【００１４】そのため、上記ＢＧＡパッケージにおいて
は、図７に示したように、基板の最上層の絶縁層１２よ
り下方の基板１０部分を多数の薄い絶縁層１２を積層し
て形成している。そして、それらの多数の絶縁層１２間
にグランド層５０をそれぞれ備えて、それらのグランド
層５０に開口した透孔５２に導体線路６０を連続して遊
挿している。そして、それらの多数のグランド層５０を
用いて高周波信号を伝える導体線路６０を同軸線路に近
い擬似同軸線路構造に形成している。そして、導体線路
６０の特性インピーダンスを導体線路６０のほぼ全長に
亙って数２の式から得られる特性インピーダンスのＺ0
に近づけている。そして、その導体線路６０を高周波信
号を伝送損失少なく伝えることができるようにしてい
る。Therefore, in the above BGA package, as shown in FIG. 7, the substrate 10 portion below the uppermost insulating layer 12 of the substrate is formed by laminating a large number of thin insulating layers 12. Then, the ground layer 50 is provided between each of the multiple insulating layers 12, and the conductor line 60 is continuously loosely inserted into the through hole 52 opened in the ground layer 50. Then, the conductor line 60 for transmitting a high-frequency signal is formed in a pseudo coaxial line structure close to a coaxial line by using the large number of ground layers 50. Then, the characteristic impedance of the conductor line 60 is Z 0 of the characteristic impedance obtained from the equation (2) over almost the entire length of the conductor line 60.
Is approaching. Then, the conductor line 60 can transmit a high frequency signal with a small transmission loss.
【００１５】最上層の絶縁層１２は、基板上面のマイク
ロストリップ線路構造をした信号線路３０の特性インピ
ーダンスを所定値の５０Ω等にマッチングさせるため
に、数１の式のＺ0 を５０Ω等とした場合に、数１の式
から得られる層厚ｈにその厚さを形成している。In order to match the characteristic impedance of the signal line 30 having the microstrip line structure on the upper surface of the substrate with the predetermined value of 50Ω or the like, the uppermost insulating layer 12 has Z 0 of the formula 1 set to 50Ω or the like. In this case, the thickness is formed to the layer thickness h obtained from the equation (1).
【００１６】[0016]
【発明が解決しようとする課題】しかしながら、上記の
ようにして、ＢＧＡパッケージの基板１０を形成した場
合には、導体線路６０の特性インピーダンスを５０Ω等
にマッチングさせようとすると、グランド層５０に開口
する透孔５２の内径Ｄが、前述のように約１．３０８ｍ
ｍ等と大きくなってしまった。そして、基板１０の下面
に外部接続端子２０を一般に汎用されている１．２７ｍ
ｍ等の小ピッチＨで複数個格子状に並べて備えるため
に、基板１０に導体線路６０を１．２７ｍｍ等の小ピッ
チＨで並べて備えようとした場合に、図８に示したよう
に、導体線路６０を遊挿するためのグランド層５０に開
口した透孔５２がそれに隣合う同じグランド層５０に開
口した透孔５２の一部に重なり合ってしまった。そし
て、グランド層の透孔５２に遊挿した導体線路部分６０
ａの特性インピーダンスを数２の式から得られる特性イ
ンピーダンスの５０Ω等にマッチングさせることが不可
能となってしまった。However, when the substrate 10 of the BGA package is formed as described above, if the characteristic impedance of the conductor line 60 is to be matched with 50Ω or the like, the ground layer 50 is opened. The inner diameter D of the through hole 52 is about 1.308 m as described above.
It has grown as m. The external connection terminal 20 is provided on the lower surface of the substrate 10.
In order to arrange a plurality of conductor lines 60 on the substrate 10 at a small pitch H such as 1.27 mm in order to arrange a plurality of them in a grid pattern at a small pitch H such as m, as shown in FIG. The through hole 52 opened in the ground layer 50 for loosely inserting the line 60 overlaps a part of the through hole 52 opened in the same ground layer 50 adjacent to the ground layer 50. The conductor line portion 60 loosely inserted in the through hole 52 of the ground layer
It became impossible to match the characteristic impedance of a with the characteristic impedance of 50Ω obtained from the equation (2).
【００１７】そこで、本発明者らは、鋭意研究の末、グ
ランド層５０に開口する透孔５２の内径を数２の式から
得られる透孔の内径Ｄより狭めて、その透孔５２に遊挿
した導体線路部分６０ａの特性インピーダンスを低く抑
えても、基板１０を構成する絶縁層１２の層厚を厚く形
成すれば、基板１０に上下に貫通させて備えた導体線路
６０の特性インピーダンスを、グランド層の透孔５２に
遊挿した導体線路部分６０ａの特性インピーダンスに比
べて、高められることを発見した。Therefore, the inventors of the present invention, after earnest research, make the inner diameter of the through hole 52 opening in the ground layer 50 narrower than the inner diameter D of the through hole obtained from the equation (2), and play in the through hole 52. Even if the characteristic impedance of the inserted conductor line portion 60a is suppressed to be low, if the insulating layer 12 forming the substrate 10 is formed to have a large thickness, the characteristic impedance of the conductor line 60 that is vertically penetrated through the substrate 10 is It has been discovered that the impedance is higher than the characteristic impedance of the conductor line portion 60a loosely inserted in the through hole 52 of the ground layer.
【００１８】それと共に、基板１０を構成する絶縁層１
２の数を減少させて、絶縁層１２の層厚を厚く形成すれ
ば、基板１０に上下に貫通させて備えた導体線路６０の
共振周波数点を高周波領域側にシフトさせることができ
ることを発見した。At the same time, the insulating layer 1 constituting the substrate 10
It was discovered that if the number of 2 is reduced and the insulating layer 12 is formed thicker, the resonance frequency point of the conductor line 60 that is vertically penetrated through the substrate 10 can be shifted to the high frequency region side. .
【００１９】そして、これらの発見に基づき、導体線路
６０の特性インピーダンスを所定値の５０Ω等にマッチ
ングさせると共に、導体線路６０下端に一連に接続され
た外部接続端子２０を基板１０の下面に１．２７ｍｍ等
の小ピッチで並べて備えた高周波デバイス実装用基板で
あって、導体線路６０の共振周波数点を高周波領域側に
シフトさせた高周波デバイス実装用基板を開発した。Based on these discoveries, the characteristic impedance of the conductor line 60 is matched with a predetermined value of 50Ω, and the external connection terminals 20 connected in series to the lower end of the conductor line 60 are provided on the lower surface of the substrate 10. We have developed a high-frequency device mounting substrate that is arranged side by side with a small pitch such as 27 mm, in which the resonance frequency point of the conductor line 60 is shifted to the high-frequency region side.
【００２０】即ち、本発明は、基板に備えた擬似同軸線
路構造をした導体線路の特性インピーダンスを所定値に
マッチングさせることができると共に、基板に備えた導
体線路下端に一連に接続された外部接続端子を基板の下
面に小ピッチで並べて備えることが可能な高周波デバイ
ス実装用基板であって、基板に備えた導体線路の共振周
波数点を高周波領域側にシフトさせることのできる高周
波デバイス実装用基板を提供することを目的としてい
る。That is, according to the present invention, the characteristic impedance of the conductor line having the pseudo coaxial line structure provided on the substrate can be matched to a predetermined value, and the lower end of the conductor line provided on the substrate is connected in series to the external connection. A high-frequency device mounting substrate capable of arranging terminals on the lower surface of the substrate side by side with a small pitch, and capable of shifting a resonance frequency point of a conductor line provided on the substrate to a high-frequency region side. It is intended to be provided.
【００２１】[0021]
【課題を解決するための手段】上記目的を達成するため
に、本発明の高周波デバイス実装用基板は、下部絶縁層
上に上部絶縁層をグランド層を介して積層して形成した
基板の上部絶縁層の上面に信号線路を備えて、該信号線
路をその下方の前記グランド層によりマイクロストリッ
プ線路構造に形成すると共に、前記基板に導体線路を前
記上部絶縁層と下部絶縁層とを連続して貫通させて備え
て、その導体線路の上下端を前記信号線路と前記下部絶
縁層の下面に備えた外部接続端子にそれぞれ一連に接続
し、さらに、前記導体線路と交叉する前記グランド層部
分に円形状の透孔を導体線路を中心に開口して、前記導
体線路を前記グランド層により擬似同軸線路構造に形成
してなる高周波デバイス実装用基板であって、前記グラ
ンド層の透孔の内径を、その透孔に遊挿した前記導体線
路部分の特性インピーダンスが所定値より低くなるよう
に小径に形成して、前記透孔に遊挿した導体線路部分の
特性インピーダンスを所定値より低下させると共に、前
記下部絶縁層の層厚を、その下部絶縁層に貫通させて備
えた前記導体線路部分の線路長が延長されてその導体線
路部分の特性インピーダンスが所定値より高くなるよう
に厚く形成して、該下部絶縁層に貫通させて備えた導体
線路部分の特性インピーダンスを所定値より上昇させ、
前記透孔に遊挿した導体線路部分の特性インピーダンス
の低下を前記下部絶縁層に貫通させて備えた導体線路部
分の特性インピーダンスの上昇分により相殺して、前記
導体線路の特性インピーダンスを所定値にマッチングさ
せたことを特徴としている。In order to achieve the above object, a substrate for mounting a high frequency device of the present invention has an upper insulating layer formed by laminating an upper insulating layer on a lower insulating layer via a ground layer. A signal line is provided on the upper surface of the layer, the signal line is formed in a microstrip line structure by the ground layer thereunder, and a conductor line is continuously penetrated through the substrate through the upper insulating layer and the lower insulating layer. In addition, the upper and lower ends of the conductor line are connected in series to the signal line and the external connection terminals provided on the lower surface of the lower insulating layer, and further, a circular shape is formed on the ground layer portion intersecting with the conductor line. Of the through hole of the ground layer, and the conductor line is formed in a pseudo coaxial line structure by the ground layer. Is formed to have a small diameter so that the characteristic impedance of the conductor line portion loosely inserted into the through hole is lower than a predetermined value, and the characteristic impedance of the conductor line portion loosely inserted into the through hole is lowered below a predetermined value. A layer thickness of the lower insulating layer is formed thick so that the line length of the conductor line portion provided by penetrating the lower insulating layer is extended and the characteristic impedance of the conductor line portion is higher than a predetermined value. , Increasing the characteristic impedance of the conductor line portion provided through the lower insulating layer above a predetermined value,
The decrease in the characteristic impedance of the conductor line portion loosely inserted in the through hole is offset by the increase in the characteristic impedance of the conductor line portion provided by penetrating the lower insulating layer, and the characteristic impedance of the conductor line is set to a predetermined value. It is characterized by matching.
【００２２】本発明の高周波デバイス実装用基板におい
ては、外部接続端子表面にはんだバンプを形成すること
を好適としている。In the high frequency device mounting substrate of the present invention, it is preferable to form a solder bump on the surface of the external connection terminal.
【００２３】また、本発明の高周波デバイス実装用基板
においては、下部絶縁層の層厚を０．１２ｍｍ以上に厚
く形成することを好適としている。Further, in the high frequency device mounting substrate of the present invention, it is preferable that the lower insulating layer is formed to have a thickness of 0.12 mm or more.
【００２４】また、本発明の高周波デバイス実装用基板
においては、上部絶縁層と下部絶縁層とがセラミックか
らなり、グランド層がメタライズからなり、導体線路が
メタライズが充填されたビアからなることを好適として
いる。In the high frequency device mounting substrate of the present invention, it is preferable that the upper insulating layer and the lower insulating layer are made of ceramic, the ground layer is made of metallized, and the conductor line is made of a via filled with metallized. I am trying.
【００２５】[0025]
【作用】本発明の高周波デバイス実装用基板において
は、グランド層の透孔の内径を、設定しようとする導体
線路の特性インピーダンスＺ0 を求める数２の式から得
られる透孔の内径Ｄより小径に形成している。そして、
そのグランド層の透孔に遊挿した導体線路部分の特性イ
ンピーダンスＺ1 を、設定しようとする導体線路の特性
インピーダンスの所定値のＺ0 に比べて、低下させてい
る。In the substrate for mounting a high frequency device of the present invention, the inner diameter of the through hole of the ground layer is smaller than the inner diameter D of the through hole obtained from the equation (2) for obtaining the characteristic impedance Z 0 of the conductor line to be set. Is formed. And
The characteristic impedance Z 1 of the conductor line portion loosely inserted in the through hole of the ground layer is made lower than the predetermined value Z 0 of the characteristic impedance of the conductor line to be set.
【００２６】それと共に、下部絶縁層の層厚を厚く形成
して、その下部絶縁層に貫通させて備えた導体線路部分
の線路長を延長している。そして、下部絶縁層に貫通さ
せて備えた導体線路部分の特性インピーダンスＺ2 を、
設定しようとする導体線路の特性インピーダンスの所定
値のＺ0 に比べて、上昇させている。At the same time, the lower insulating layer is formed to have a large thickness, and the line length of the conductor line portion provided through the lower insulating layer is extended. Then, the characteristic impedance Z 2 of the conductor line portion provided by penetrating the lower insulating layer is
The characteristic impedance of the conductor line to be set is increased as compared with Z 0 which is a predetermined value.
【００２７】そのため、グランド層の透孔に遊挿した導
体線路部分の特性インピーダンスＺ1 の低下を下部絶縁
層に貫通させて備えた導体線路部分の特性インピーダン
スＺ2 の上昇分により相殺して、基板の上部絶縁層と下
部絶縁層とに連続して貫通させて備えた導体線路の特性
インピーダンスを設定しようとする導体線路の特性イン
ピーダンスの所定値のＺ0 にマッチングさせることがで
きる。Therefore, the decrease in the characteristic impedance Z 1 of the conductor line portion loosely inserted in the through hole of the ground layer is offset by the increase in the characteristic impedance Z 2 of the conductor line portion provided by penetrating the lower insulating layer, The characteristic impedance of the conductor line provided by continuously penetrating the upper insulating layer and the lower insulating layer of the substrate can be matched with Z 0 of the predetermined value of the characteristic impedance of the conductor line to be set.
【００２８】それと共に、グランド層の透孔の内径を小
径に形成したため、基板の上部絶縁層と下部絶縁層とに
連続して貫通させて備えた導体線路のピッチを狭めて
も、グランド層に開口した透孔がそれに隣合う同じグラ
ンド層に開口した透孔の一部に重なり合うのを防ぐこと
ができる。At the same time, since the inner diameter of the through hole of the ground layer is formed to be small, even if the pitch of the conductor lines continuously penetrating the upper insulating layer and the lower insulating layer of the substrate is narrowed, It is possible to prevent the opened through hole from overlapping a part of the opened through hole in the same ground layer adjacent thereto.
【００２９】その結果、基板の上部絶縁層と下部絶縁層
とに連続して貫通させて備えた複数本の導体線路のピッ
チを狭めて、それらの導体線路下端にそれぞれ一連に接
続された外部接続端子を基板の下面に小ピッチで並べて
備えることができる。As a result, the pitch of a plurality of conductor lines provided continuously penetrating the upper insulating layer and the lower insulating layer of the substrate is narrowed, and external connection is connected to the lower ends of the conductor lines in series. The terminals can be provided on the lower surface of the substrate side by side with a small pitch.
【００３０】さらに、上部絶縁層の層厚を調整して、上
部絶縁層上面の信号線路とその下方のグランド層との間
の距離を調整したり、信号線路の幅やその厚さを調整し
たりして、上部絶縁層上面のマイクロストリップ線路構
造をした信号線路の特性インピーダンスを設定しようと
する信号線路の特性インピーダンスの所定値のＺ0 にマ
ッチングさせることができる。Further, the layer thickness of the upper insulating layer is adjusted to adjust the distance between the signal line on the upper surface of the upper insulating layer and the ground layer below it, and the width and thickness of the signal line are adjusted. Alternatively, the characteristic impedance of the signal line having the microstrip line structure on the upper surface of the upper insulating layer can be matched with the predetermined value Z 0 of the characteristic impedance of the signal line to be set.
【００３１】また、本発明の高周波デバイス実装用基板
においては、基板を下部絶縁層と上部絶縁層との少数層
で形成して、下部絶縁層の層厚を厚く形成したため、基
板の上部絶縁層と下部絶縁層とに連続して貫通させて備
えた導体線路の共振周波数点を、高周波領域側にシフト
させることができる。In the high frequency device mounting substrate of the present invention, since the substrate is formed of a small number of lower insulating layers and upper insulating layers and the lower insulating layer is formed thicker, the upper insulating layer of the substrate is formed. It is possible to shift the resonance frequency point of the conductor line, which is provided by continuously penetrating the lower insulating layer to the high frequency region side.
【００３２】また、外部接続端子表面にはんだバンプを
形成した本発明の高周波デバイス実装用基板にあって
は、その外部接続端子をボード表面の接続端子に重ね合
わせて、外部接続端子をボードの接続端子に外部接続端
子に形成されたはんだバンプを用いて距離短くはんだ付
け接続できる。そして、外部接続端子とボード表面の接
続端子との間を高周波信号を伝送損失少なく伝えること
ができる。In the high frequency device mounting board of the present invention in which the solder bumps are formed on the surfaces of the external connection terminals, the external connection terminals are superposed on the connection terminals on the board surface to connect the external connection terminals to the board. The solder bumps formed on the external connection terminals can be used to connect the terminals by soldering for a short distance. Then, a high frequency signal can be transmitted between the external connection terminal and the connection terminal on the surface of the board with less transmission loss.
【００３３】[0033]
【実施例】次に、本発明の実施例を図面に従い説明す
る。図１と図２は本発明の高周波デバイス実装用基板の
好適な実施例を示し、図１はその一部拡大正面断面図、
図２は図１のＡ―Ａ断面図である。以下に、この基板を
説明する。Embodiments of the present invention will now be described with reference to the drawings. 1 and 2 show a preferred embodiment of a high-frequency device mounting substrate of the present invention, and FIG. 1 is a partially enlarged front sectional view thereof,
FIG. 2 is a sectional view taken along line AA of FIG. The substrate will be described below.
【００３４】図の高周波デバイス実装用基板では、基板
１０を下部絶縁層１２ａ上に上部絶縁層１２ｂを積層し
て形成している。下部絶縁層１２ａと上部絶縁層１２ｂ
とは、セラミックで形成している。In the illustrated high frequency device mounting substrate, the substrate 10 is formed by laminating the upper insulating layer 12b on the lower insulating layer 12a. Lower insulating layer 12a and upper insulating layer 12b
And are made of ceramics.
【００３５】基板１０には、円柱状の導体線路６０を上
部絶縁層１２ｂと下部絶縁層１２ａとを上下に連続して
貫通させて備えている。導体線路６０は、タングステン
メタライズ等のメタライズが充填されたビアで形成して
いる。The substrate 10 is provided with a cylindrical conductor line 60 which is formed by vertically penetrating an upper insulating layer 12b and a lower insulating layer 12a. The conductor line 60 is formed by a via filled with metallization such as tungsten metallization.
【００３６】導体線路６０の上下端は、上部絶縁層１２
ｂの上面に備えた信号線路３０と下部絶縁層１２ａの下
面に備えたパッド状の外部接続端子２０とにそれぞれ一
連に接続している。信号線路３０と外部接続端子２０と
は、タングステンメタライズ等のメタライズでそれぞれ
形成している。The upper and lower ends of the conductor line 60 are formed on the upper insulating layer 12.
The signal line 30 provided on the upper surface of b and the pad-shaped external connection terminal 20 provided on the lower surface of the lower insulating layer 12a are connected in series. The signal line 30 and the external connection terminal 20 are each formed by metallization such as tungsten metallization.
【００３７】外部接続端子２０表面には、はんだバンプ
２２を半球状に形成している。そして、そのはんだバン
プ２２を用いて外部接続端子２０をボード表面の接続端
子（図示せず）にはんだ付け接続できるようにしてい
る。Solder bumps 22 are formed in a hemispherical shape on the surfaces of the external connection terminals 20. The solder bumps 22 are used to connect the external connection terminals 20 to the connection terminals (not shown) on the surface of the board by soldering.
【００３８】上部絶縁層１２ｂと下部絶縁層１２ａとの
間には、タングステンメタライズ等のメタライズからな
るグランド層５０を薄層状に連続して広く備えている。Between the upper insulating layer 12b and the lower insulating layer 12a, a ground layer 50 made of metallized metal such as tungsten metallized is continuously and widely provided in the form of a thin layer.
【００３９】導体線路６０と交叉するグランド層５０部
分には、図２に示したように、円形状の透孔５２を導体
線路６０を中心に開口している。そして、そのグランド
層の透孔５２に導体線路６０を遊挿して、導体線路６０
をグランド層５０により擬似同軸線路構造に形成してい
る。In the portion of the ground layer 50 that intersects with the conductor line 60, as shown in FIG. 2, a circular through hole 52 is opened centering on the conductor line 60. Then, the conductor line 60 is loosely inserted into the through hole 52 of the ground layer to form the conductor line 60.
Are formed into a pseudo coaxial line structure by the ground layer 50.
【００４０】信号線路３０は、その下方の上記グランド
層５０により、マイクロストリップ線路構造に形成して
いる。そして、信号線路３０の幅ｗとその厚さｔ、信号
線路３０とグランド層５０との間の距離ｈ、即ち上部絶
縁層１２ｂの厚さｈ１をそれぞれ大小に調整して、数１
の式から得られる信号線路３０の特性インピーダンスＺ
0 を設定しようとする信号線路３０の特性インピーダン
スの所定値の５０Ω等にマッチングさせている。The signal line 30 is formed in a microstrip line structure by the ground layer 50 below it. Then, the width w and the thickness t of the signal line 30 and the distance h between the signal line 30 and the ground layer 50, that is, the thickness h1 of the upper insulating layer 12b are adjusted to be large or small, respectively,
Characteristic impedance Z of the signal line 30 obtained from the equation
The characteristic impedance of the signal line 30 to be set to 0 is matched with a predetermined value of 50Ω or the like.
【００４１】導体線路６０を遊挿したグランド層の透孔
５２の内径は、数２の式のＺ0 を所定値の５０Ω等とし
た場合に数２の式から得られるグランド層の透孔の内径
Ｄに比べて、小径に形成している。そして、グランド層
の透孔５２に遊挿した導体線路部分６０ａの特性インピ
ーダンスＺ1 を設定しようとする導体線路６０の特性イ
ンピーダンスの所定値の５０Ω等より低下させている。The inner diameter of the through hole 52 in the ground layer, into which the conductor line 60 is loosely inserted, is the same as that of the through hole in the ground layer obtained from the equation 2 when Z 0 in the equation 2 is 50Ω which is a predetermined value. The diameter is smaller than the inner diameter D. Then, the characteristic impedance Z 1 of the conductor line portion 60a loosely inserted in the through hole 52 of the ground layer is made lower than a predetermined value of 50Ω or the like of the characteristic impedance of the conductor line 60 to be set.
【００４２】下部絶縁層１２ａは、その層厚を厚く形成
して、その下部絶縁層１２ａに上下に貫通させて備えた
導体線路部分６０ｂの線路長を延長している。そして、
その導体線路部分６０ｂの特性インピーダンスＺ2 を設
定しようとする導体線路６０の特性インピーダンスの所
定値の５０Ω等より上昇させている。The lower insulating layer 12a is formed to have a large thickness, and the line length of the conductor line portion 60b provided by vertically penetrating the lower insulating layer 12a is extended. And
The characteristic impedance Z 2 of the conductor line portion 60b is set higher than a predetermined value of 50Ω or the like of the characteristic impedance of the conductor line 60 to be set.
【００４３】そして、グランド層の透孔５２に遊挿した
導体線路部分６０ａの特性インピーダンスＺ1 の低下を
下部絶縁層１２ａに上下に貫通させて備えた導体線路部
分６０ｂの特性インピーダンスＺ2 の上昇分により相殺
して、基板の上部絶縁層１２ｂと下部絶縁層１２ａとに
上下に連続して貫通させて備えた導体線路６０の特性イ
ンピーダンスＺ0 を設定しようとする導体線路６０の特
性インピーダンスの所定値の５０Ω等にマッチングさせ
ている。そして、信号線路３０とそれに連なる導体線路
６０とに高周波信号を伝送損失少なく伝えることができ
るようにしている。Then, the characteristic impedance Z 1 of the conductor line portion 60a loosely inserted in the through hole 52 of the ground layer is increased, and the characteristic impedance Z 2 of the conductor line portion 60b provided by vertically penetrating the lower insulating layer 12a is increased. Of the characteristic impedance Z 0 of the conductor line 60, which is offset by the distance and is set to continuously penetrate through the upper insulating layer 12b and the lower insulating layer 12a of the substrate in the vertical direction. Matched with a value of 50Ω. The high-frequency signal can be transmitted to the signal line 30 and the conductor line 60 connected to the signal line 30 with less transmission loss.
【００４４】それと共に、基板１０を下部絶縁層１２ａ
と上部絶縁層１２ｂとの少数層で形成して、下部絶縁層
１２ａの層厚を厚く形成することにより、上部絶縁層１
２ｂと下部絶縁層１２ａとに上下に連続して貫通させて
備えた導体線路６０の共振周波数点を高周波領域側にシ
フトさせている。そして、導体線路６０に高周波信号を
伝えた場合に、導体線路６０が共振を起こして、導体線
路６０に高周波信号を伝えることが不可能となるのを防
ぐことができるようにしている。At the same time, the substrate 10 is attached to the lower insulating layer 12a.
And the upper insulating layer 12b are formed by a small number of layers, and the lower insulating layer 12a is formed to have a large layer thickness.
The resonance frequency point of the conductor line 60 provided by vertically penetrating the 2b and the lower insulating layer 12a is shifted to the high frequency region side. Then, when a high frequency signal is transmitted to the conductor line 60, it is possible to prevent the conductor line 60 from resonating and becoming impossible to transmit the high frequency signal to the conductor line 60.
【００４５】図１と図２に示した高周波デバイス実装用
基板は、以上のように構成している。The high frequency device mounting substrate shown in FIGS. 1 and 2 is configured as described above.
【００４６】次に、上述高周波デバイス実装用基板の具
体的な実験例を示す。この実験例では、上部絶縁層１２
ｂと下部絶縁層１２ａとを比誘電率εr が９．５のアル
ミナセラミックでそれぞれ形成して、上部絶縁層上面の
信号線路３０の幅ｗを０．３ｍｍとし、その信号線路３
０の厚さｔを０．０２０〜０．０２５ｍｍとした。そし
て、数１の式から得られる信号線路３０の特性インピー
ダンスＺ0 の値が５０Ωとなるように、数１の式を用い
て信号線路３０とその下方のグランド層５０との間の距
離ｈ、即ち上部絶縁層１２ｂの厚さｈ１を０．３２ｍｍ
とした。Next, a concrete experimental example of the above-mentioned substrate for mounting a high frequency device will be shown. In this experimental example, the upper insulating layer 12
b and the lower insulating layer 12a are each formed of alumina ceramic having a relative dielectric constant ε r of 9.5, and the width w of the signal line 30 on the upper surface of the upper insulating layer is set to 0.3 mm.
The thickness t of 0 was 0.020 to 0.025 mm. Then, the distance h between the signal line 30 and the ground layer 50 below the signal line 30 is calculated by using the formula 1 so that the value of the characteristic impedance Z 0 of the signal line 30 obtained from the formula 1 is 50Ω. That is, the thickness h1 of the upper insulating layer 12b is 0.32 mm.
And
【００４７】それと共に、メタライズが充填されたビア
からなる導体線路６０の外径ｄを０．１ｍｍとして、メ
タライズからなるグランド層の透孔５２の内径Ｄを０．
４７ｍｍとすると共に、下部絶縁層１２ａの厚さｈ２を
０．３２ｍｍとしたり、グランド層の透孔５２の内径Ｄ
を０．５２ｍｍとすると共に、下部絶縁層１２ａの厚さ
ｈ２を０．１９ｍｍとしたり、グランド層の透孔５２の
内径Ｄを０．６７ｍｍとすると共に、下部絶縁層１２ａ
の厚さｈ２を０．１２ｍｍとしたりした。At the same time, the outer diameter d of the conductor line 60 formed of a via filled with metallization is set to 0.1 mm, and the inner diameter D of the through hole 52 of the ground layer formed of metallization is set to 0.1 mm.
47 mm, the thickness h2 of the lower insulating layer 12a is 0.32 mm, and the inner diameter D of the through hole 52 of the ground layer is
Is 0.52 mm, the thickness h2 of the lower insulating layer 12a is 0.19 mm, the inner diameter D of the through hole 52 of the ground layer is 0.67 mm, and the lower insulating layer 12a is
The thickness h2 of each was set to 0.12 mm.
【００４８】そして、ＴＤＲ法を用いて導体線路６０の
特性インピーダンスＺ0 を測定したところ、いずれも５
０Ωとなることが確認された。Then, the characteristic impedance Z 0 of the conductor line 60 was measured using the TDR method.
It was confirmed to be 0Ω.
【００４９】また、ネットワークアナライザを用いて導
体線路６０のＳパラメータ値を測定したところ、上記の
ように、下部絶縁層１２ａの層厚を厚く形成した場合に
は、導体線路６０の共振周波数点が高周波領域側にシフ
トすることが確認された。具体的には、上部絶縁層１２
ｂの層厚ｈ１を０．３２ｍｍに形成すると共に、下部絶
縁層１２ａの層厚ｈ２を０．１２ｍｍに厚く形成した場
合には、導体線路６０の共振周波数点が１０ＧＨｚ付近
の高周波領域まで生じないことが確認された。また、上
部絶縁層１２ｂの層厚ｈ１を０．３２ｍｍに形成すると
共に、下部絶縁層１２ａの層厚ｈ２を０．３２ｍｍに厚
く形成した場合には、導体線路６０の共振周波数点が１
９ＧＨｚ付近の高周波領域まで生じないことが確認され
た。Further, when the S parameter value of the conductor line 60 was measured using a network analyzer, when the lower insulating layer 12a was formed thick as described above, the resonance frequency point of the conductor line 60 was It was confirmed to shift to the high frequency region side. Specifically, the upper insulating layer 12
When the layer thickness h1 of b is formed to be 0.32 mm and the layer thickness h2 of the lower insulating layer 12a is formed to be thick to 0.12 mm, the resonance frequency point of the conductor line 60 does not occur up to a high frequency region near 10 GHz. It was confirmed. Further, when the layer thickness h1 of the upper insulating layer 12b is formed to be 0.32 mm and the layer thickness h2 of the lower insulating layer 12a is formed to be thick to 0.32 mm, the resonance frequency point of the conductor line 60 is 1
It was confirmed that the high frequency region around 9 GHz did not occur.
【００５０】また、上記のようにして、グランド層の透
孔５２の内径Ｄを０．４７ｍｍに狭めて、下部絶縁層１
２ａの層厚ｈ２を０．３２ｍｍに厚く形成した場合に
は、基板１０に上下に貫通させて備えた複数本の導体線
路６０のピッチＨ、即ち導体線路６０下端に一連に接続
された下部絶縁層下面の外部接続端子２０のピッチＨ
を、一般に汎用されている１．２７ｍｍは勿論、０．６
５ｍｍまで狭めても、グランド層の透孔５２がそれに隣
合う同じグランド層の透孔５２の一部に重なり合うのを
防いで、導体線路６０の特性インピーダンスを５０Ωに
的確にマッチングさせることができることが確認され
た。Further, as described above, the inner diameter D of the through hole 52 of the ground layer is narrowed to 0.47 mm, and the lower insulating layer 1
When the layer thickness h2 of 2a is thickly formed to 0.32 mm, the pitch H of the plurality of conductor lines 60 provided vertically through the substrate 10, that is, the lower insulation connected in series to the lower end of the conductor line 60. The pitch H of the external connection terminals 20 on the lower surface of the layer
Is 0.6 mm as well as 1.27 mm which is generally used.
Even if it is narrowed to 5 mm, it is possible to prevent the through hole 52 of the ground layer from overlapping a part of the through hole 52 of the same ground layer adjacent to the ground layer 52 and accurately match the characteristic impedance of the conductor line 60 to 50Ω. confirmed.
【００５１】図３は本発明の高周波デバイス実装用基板
の他の好適な実施例を示し、詳しくはその一部拡大正面
断面図である。以下に、この基板を説明する。FIG. 3 shows another preferred embodiment of the substrate for mounting a high frequency device of the present invention, more specifically a partially enlarged front sectional view thereof. The substrate will be described below.
【００５２】図の高周波デバイス実装用基板では、上部
絶縁層１２ｂと下部絶縁層１２ａとを合成樹脂で形成し
ている。In the high frequency device mounting substrate shown in the figure, the upper insulating layer 12b and the lower insulating layer 12a are formed of synthetic resin.
【００５３】グランド層５０は、上部絶縁層１２ｂ下面
又は下部絶縁層１２ａ上面に銅等の金属箔を被着させて
備えている。導体線路６０と交叉するグランド層５０部
分には、円形状の透孔５２を導体線路５０を中心に開口
している。The ground layer 50 is provided by depositing a metal foil such as copper on the lower surface of the upper insulating layer 12b or the upper surface of the lower insulating layer 12a. In the portion of the ground layer 50 that intersects with the conductor line 60, a circular through hole 52 is opened centering on the conductor line 50.
【００５４】信号線路３０は、上部絶縁層１２ｂの上面
に被着された銅等の金属箔を細帯状にエッチング加工等
することにより上部絶縁層１２ｂの上面に備えている。The signal line 30 is provided on the upper surface of the upper insulating layer 12b by etching a metal foil such as copper deposited on the upper surface of the upper insulating layer 12b into a strip shape.
【００５５】外部接続端子２０は、下部絶縁層１２ａの
下面に被着された銅等の金属箔をエッチング加工等する
ことにより下部絶縁層１２ａの下面に備えている。外部
接続端子２０表面には、はんだバンプ２２を半球状に形
成している。The external connection terminal 20 is provided on the lower surface of the lower insulating layer 12a by etching a metal foil such as copper deposited on the lower surface of the lower insulating layer 12a. A solder bump 22 is formed in a hemispherical shape on the surface of the external connection terminal 20.
【００５６】導体線路６０は、円筒状をしていて、上部
絶縁層１２ｂと下部絶縁層１２ａとにスルーホール６２
を上下に連続して貫通させて開口して、そのスルーホー
ル６２内周面に導体めっき層６４を無電解めっき法等に
より信号線路３０と所定の外部接続端子２０とにそれぞ
れ連続させて備えることにより形成している。The conductor line 60 has a cylindrical shape and has through holes 62 in the upper insulating layer 12b and the lower insulating layer 12a.
Are continuously penetrated vertically and opened, and a conductor plating layer 64 is provided on the inner peripheral surface of the through hole 62 so as to be continuous with the signal line 30 and the predetermined external connection terminal 20 by electroless plating or the like. It is formed by.
【００５７】グランド線路５４は、円筒状をしていて、
下部絶縁層１２ａにスルーホール５６を上下に貫通させ
て開口して、そのスルーホール５６内周面に導体めっき
層５８を無電解めっき法等によりグランド層５０と所定
の外部接続端子２０とにそれぞれ連続させて備えること
により形成している。The ground line 54 has a cylindrical shape,
A through hole 56 is vertically penetrated through the lower insulating layer 12a to form an opening, and a conductor plating layer 58 is formed on the inner peripheral surface of the through hole 56 for the ground layer 50 and the predetermined external connection terminal 20 by electroless plating or the like. It is formed by continuously providing.
【００５８】その他は、前述図１と図２に示した高周波
デバイス実装用基板と同様に構成していて、その作用
も、前述図１と図２に示した高周波デバイス実装用基板
と同様である。Others are the same as those of the high-frequency device mounting substrate shown in FIGS. 1 and 2, and the operation is the same as that of the high-frequency device mounting substrate shown in FIGS. 1 and 2. .
【００５９】[0059]
【発明の効果】以上説明したように、本発明の高周波デ
バイス実装用基板によれば、基板の上部絶縁層と下部絶
縁層とに連続して貫通させて備えた擬似同軸線路構造を
した導体線路の特性インピーダンスを設定しようとする
導体線路の特性インピーダンスの所定値のＺ0 にマッチ
ングさせることができる。As described above, according to the high frequency device mounting substrate of the present invention, a conductor line having a pseudo-coaxial line structure which is provided by continuously penetrating the upper insulating layer and the lower insulating layer of the substrate. It is possible to match the characteristic impedance of Z 0 with a predetermined value Z 0 of the characteristic impedance of the conductor line to be set.
【００６０】それと共に、グランド層の透孔の内径を小
径に形成したため、基板の上部絶縁層と下部絶縁層とに
連続して貫通させて備えた複数本の導体線路のピッチを
狭めた場合に、グランド層の透孔がそれに隣合う同じグ
ランド層の透孔の一部に重なり合うのを防ぐことができ
る。そして、基板の上部絶縁層と下部絶縁層とに連続し
て貫通させて備えた複数本の導体線路のピッチを狭め
て、それらの導体線路下端にそれぞれ一連に接続された
外部接続端子を下部絶縁層の下面に小ピッチで並べて備
えることができる。At the same time, since the inner diameter of the through hole of the ground layer is formed to be small, when the pitch of the plurality of conductor lines provided continuously penetrating the upper insulating layer and the lower insulating layer of the substrate is narrowed, It is possible to prevent the through hole of the ground layer from overlapping a part of the through hole of the same ground layer adjacent thereto. Then, the pitch of the plurality of conductor lines provided by continuously penetrating the upper insulating layer and the lower insulating layer of the substrate is narrowed, and the external connection terminals connected in series at the lower ends of the conductor lines are respectively insulated from the lower insulating layer. It may be provided on the lower surface of the layer side by side with a small pitch.
【００６１】さらに、基板の上部絶縁層と下部絶縁層と
に連続して貫通させて備えた導体線路の共振周波数点を
高周波領域側にシフトさせることができる。そして、基
板の上部絶縁層と下部絶縁層とに連続して貫通させて備
えた導体線路に高周波信号を伝えた場合に、導体線路が
共振を起こして、導体線路に高周波信号を伝えることが
不可能となるのを防ぐことができる。Furthermore, it is possible to shift the resonance frequency point of the conductor line provided by penetrating the upper insulating layer and the lower insulating layer of the substrate continuously to the high frequency region side. When a high-frequency signal is transmitted to the conductor line that is continuously penetrated through the upper insulating layer and the lower insulating layer of the substrate, the conductor line resonates and it is impossible to transmit the high-frequency signal to the conductor line. It can be prevented from becoming possible.
【図１】本発明の高周波デバイス実装用基板の一部拡大
正面断面図である。FIG. 1 is a partially enlarged front sectional view of a high frequency device mounting substrate of the present invention.
【図２】図１のＡ―Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の高周波デバイス実装用基板の一部拡大
正面断面図である。FIG. 3 is a partially enlarged front sectional view of a high frequency device mounting substrate of the present invention.
【図４】ＢＧＡパッケージの本体を構成する高周波デバ
イス実装用基板の一部拡大正面断面図である。FIG. 4 is a partially enlarged front sectional view of a high-frequency device mounting substrate that constitutes the main body of the BGA package.
【図５】図４のＢ―Ｂ断面図である。5 is a sectional view taken along line BB of FIG.
【図６】数１の式の参考図である。FIG. 6 is a reference diagram of the equation of Formula 1.
【図７】ＢＧＡパッケージの本体を構成する高周波デバ
イス実装用基板の一部拡大正面断面図である。FIG. 7 is a partially enlarged front cross-sectional view of a high-frequency device mounting substrate that constitutes the main body of the BGA package.
【図８】高周波デバイス実装用基板の一部拡大断面図で
ある。FIG. 8 is a partially enlarged cross-sectional view of a high frequency device mounting substrate.
１０ 基板 １２ 絶縁層 １２ａ 下部絶縁層 １２ｂ 上部絶縁層 ２０ 外部接続端子 ２２ はんだバンプ ３０ 信号線路 ５０ グランド層 ５２ 透孔 ５４ グランド線路 ５６ スルーホール ５８ 導体めっき層 ６０ 導体線路 ６２ スルーホール ６４ 導体めっき層 10 board 12 insulating layer 12a lower insulating layer 12b upper insulating layer 20 external connection terminal 22 solder bump 30 signal line 50 ground layer 52 through hole 54 ground line 56 through hole 58 conductor plating layer 60 conductor line 62 through hole 64 conductor plating layer
Claims (4)
を介して積層して形成した基板の上部絶縁層の上面に信
号線路を備えて、該信号線路をその下方の前記グランド
層によりマイクロストリップ線路構造に形成すると共
に、前記基板に導体線路を前記上部絶縁層と下部絶縁層
とを連続して貫通させて備えて、その導体線路の上下端
を前記信号線路と前記下部絶縁層の下面に備えた外部接
続端子にそれぞれ一連に接続し、さらに、前記導体線路
と交叉する前記グランド層部分に円形状の透孔を導体線
路を中心に開口して、前記導体線路を前記グランド層に
より擬似同軸線路構造に形成してなる高周波デバイス実
装用基板であって、前記グランド層の透孔の内径を、そ
の透孔に遊挿した前記導体線路部分の特性インピーダン
スが所定値より低くなるように小径に形成して、前記透
孔に遊挿した導体線路部分の特性インピーダンスを所定
値より低下させると共に、前記下部絶縁層の層厚を、そ
の下部絶縁層に貫通させて備えた前記導体線路部分の線
路長が延長されてその導体線路部分の特性インピーダン
スが所定値より高くなるように厚く形成して、該下部絶
縁層に貫通させて備えた導体線路部分の特性インピーダ
ンスを所定値より上昇させ、前記透孔に遊挿した導体線
路部分の特性インピーダンスの低下を前記下部絶縁層に
貫通させて備えた導体線路部分の特性インピーダンスの
上昇分により相殺して、前記導体線路の特性インピーダ
ンスを所定値にマッチングさせたことを特徴とする高周
波デバイス実装用基板。1. A signal line is provided on an upper surface of an upper insulating layer of a substrate formed by laminating an upper insulating layer on a lower insulating layer via a ground layer, and the signal line is provided by the ground layer below the signal line. The conductor line is formed in a strip line structure, and the substrate is provided with a conductor line continuously penetrating the upper insulating layer and the lower insulating layer, and upper and lower ends of the conductor line are formed on the lower surfaces of the signal line and the lower insulating layer. Connected to each of the external connection terminals in series, and further, a circular through hole is opened in the ground layer portion intersecting with the conductor line centering on the conductor line, and the conductor line is simulated by the ground layer. A high-frequency device mounting substrate formed in a coaxial line structure, wherein the characteristic impedance of the conductor line portion loosely inserted into the through hole of the ground layer is lower than a predetermined value. And the characteristic impedance of the conductor line portion loosely inserted in the through hole is lowered below a predetermined value, and the layer thickness of the lower insulating layer is provided so as to penetrate the lower insulating layer. The characteristic impedance of the conductor line portion, which is formed by extending the line length of the conductor line portion so that the characteristic impedance of the conductor line portion becomes higher than a predetermined value and penetrating the lower insulating layer, The characteristic impedance of the conductor line is increased by offsetting the decrease in the characteristic impedance of the conductor line portion loosely inserted in the through hole by the increase in the characteristic impedance of the conductor line portion provided by penetrating the lower insulating layer. A high-frequency device mounting substrate, which is matched to a predetermined value.
した請求項１記載の高周波デバイス実装用基板。2. The high frequency device mounting substrate according to claim 1, wherein solder bumps are formed on the surfaces of the external connection terminals.
厚く形成した請求項１又は２記載の高周波デバイス実装
用基板。3. The high frequency device mounting substrate according to claim 1, wherein the lower insulating layer is formed to have a thickness of 0.12 mm or more.
からなり、グランド層がメタライズからなり、導体線路
がメタライズが充填されたビアからなる請求項１、２又
は３記載の高周波デバイス実装用基板。4. The substrate for mounting a high frequency device according to claim 1, 2 or 3, wherein the upper insulating layer and the lower insulating layer are made of ceramic, the ground layer is made of metallized, and the conductor line is made of a via filled with metallized. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23943494A JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23943494A JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0878797A true JPH0878797A (en) | 1996-03-22 |
| JP3313250B2 JP3313250B2 (en) | 2002-08-12 |
Family
ID=17044723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23943494A Expired - Fee Related JP3313250B2 (en) | 1994-09-06 | 1994-09-06 | Substrate for mounting high frequency devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3313250B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289736A (en) * | 2001-03-27 | 2002-10-04 | Kyocera Corp | Package for storing high-frequency semiconductor element and its mounting structure |
| JP2008251783A (en) * | 2007-03-30 | 2008-10-16 | Kyocera Corp | Wiring board and electronic device |
| JP2008251784A (en) * | 2007-03-30 | 2008-10-16 | Kyocera Corp | Wiring board and electronic device |
| US9754830B2 (en) | 2012-07-20 | 2017-09-05 | Fujitsu Limited | Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device |
| US10283464B2 (en) | 2017-07-11 | 2019-05-07 | Fujitsu Limited | Electronic device and manufacturing method of electronic device |
-
1994
- 1994-09-06 JP JP23943494A patent/JP3313250B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002289736A (en) * | 2001-03-27 | 2002-10-04 | Kyocera Corp | Package for storing high-frequency semiconductor element and its mounting structure |
| JP4623850B2 (en) * | 2001-03-27 | 2011-02-02 | 京セラ株式会社 | High frequency semiconductor element storage package and its mounting structure |
| JP2008251783A (en) * | 2007-03-30 | 2008-10-16 | Kyocera Corp | Wiring board and electronic device |
| JP2008251784A (en) * | 2007-03-30 | 2008-10-16 | Kyocera Corp | Wiring board and electronic device |
| US9754830B2 (en) | 2012-07-20 | 2017-09-05 | Fujitsu Limited | Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device |
| US10283464B2 (en) | 2017-07-11 | 2019-05-07 | Fujitsu Limited | Electronic device and manufacturing method of electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3313250B2 (en) | 2002-08-12 |
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