JPH0878391A - Dry etching method - Google Patents

Abstract

PURPOSE: To control the side etching quantity in highly accuracy while the etching damage to a substrate is reduced. CONSTITUTION: By forming a side etching introduction layer 4 on a substrate, an emitter layer 5 is subject to isotropic etching by using a radical or gas so as to introduce a side etching while the layer 4 is anisotropically etched by using ions. The side etching quantity can be controlled in higher accuracy than that in the case where the side etching through over-etching is introduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method used for manufacturing semiconductor integrated circuits and the like, and more particularly to a method for controlling the side etching amount in anisotropic etching with high accuracy.

[0002]

2. Description of the Related Art In manufacturing a semiconductor integrated circuit, it is often necessary to introduce side etching due to the structure of active elements and through holes. In such cases, isotropic etching such as wet etching, gas etching, or etching with neutral radicals is widely used. However, for example, when a mesa having a height of 1 μm is formed by isotropic etching, the side etching amount is about 1 μm, which is the same as the height of the mesa, and a fine pattern cannot be processed. In addition, since the side etching amount is uniquely determined by the height of the mesa, it cannot be controlled.

As a general method for controlling the side etching amount, there is a method using overetching. FIG. 4 shows mesa etching by this method. First, as shown in FIG. 4A, the material to be etched 2 is deposited on the substrate 1, patterned by the photoresist 3, and then etched by dry etching. At this time, the etching plasma should be controlled under the condition that the material 2 to be etched can be selectively etched with respect to the substrate 1 and an ionic component capable of anisotropic etching and a neutral radical capable of isotropic etching coexist. To use. When the etching of the material to be etched is completed, the substrate 1 is exposed, but when the etching is further continued, the anisotropic etching due to the ions in the plasma is stopped, but the etching due to the anisotropic etching due to the radicals and the like progresses, as shown in FIG. (B)
Side etching is introduced as shown in FIG.

[0004]

In this conventional dry etching method, the side etching amount is determined by the overetching time, but when it is difficult to detect the anisotropic etching end point of the material to be etched due to variations in the etching rate or the like. However, it is difficult to control the over-etching time, which causes a problem that the side etching amount varies. Further, during the over-etching, the substrate is continuously irradiated with the ions, so that a problem that the substrate is damaged by etching occurs at the same time.

An object of the present invention is to provide a dry etching method capable of controlling the side etching amount with high accuracy while reducing the etching damage to the substrate.

[0006]

According to the dry etching method of the present invention, a side etching introduction layer and a thin film made of a substance capable of etching with the same kind of plasma as the side etching introduction layer and having a high etching rate are formed on a substrate. A step of sequentially depositing and forming, and a step of performing dry etching in plasma in which both ions for anisotropically etching the thin film and the side etching introduction layer and radicals for isotropically etching exist Composed of.

[0007]

In the present invention, by providing the side etching introduction layer on the substrate, while the anisotropic etching is performed on the side etching introduction layer by the ions,
The layer to be etched on the side etching introduction layer is anisotropically etched by radicals or the like to introduce the side etching. Since the amount of side etching is determined by the time during which anisotropic etching is performed on the side etching introduction layer, it is possible to control the side etching amount with high accuracy by changing the thickness of the side etching introduction layer. .

[0008]

Next, the present invention will be described with reference to the drawings. As an embodiment of the present invention, FIG. 1 is a cross-sectional view of an emitter top type GaAs heterojunction bipolar transistor in the order of manufacturing steps until the base electrode is formed.

First, as shown in FIG. 1A, an n-type GaAs collector layer 2, a p-type GaAs base layer 3, and an n-type InGaAs side etching introduction layer sequentially grown on a semi-insulating GaAs substrate 1 by an epitaxial growth method. 4, n
The unnecessary portion of the type AlGaAs emitter layer 5 is made to have a high resistance by the proton ion implantation. This is the proton-ion-implanted damage layer 6. Next, a refractory metal such as a WSi film is formed on the entire surface of the substrate by a sputtering method, and patterned by reactive ion etching (RIE) using SF ₆ gas with a photoresist as a mask to form an emitter electrode 7. To do.

Next, as shown in FIG. 1B, the emitter layer 7 is used as a mask to etch the emitter layer 5 by reactive ion beam etching using chlorine plasma to expose the side etching introduction layer 4. This time,
Although there are both chlorine ion components for anisotropic etching and radicals and chlorine gas for isotropic etching in plasma, the etching rate of anisotropic etching by chlorine ions for AlGaAs is Since the etching rate of side etching due to radicals or the like is higher, the side etching amount in this step can be ignored.

Thereafter, as shown in FIG. 1C, the side etching introduction layer 4 is subsequently etched by reactive ion beam etching using chlorine plasma with the same mask. In this case, the etching rate of anisotropic etching for InGaAs is extremely slower than that for AlGaAs, and is generally 1/10 or less. Therefore, while etching the InGaAs side etching introduction layer, the AlGaAs emitter layer is side-etched by radicals and gas. When the etching progresses and the GaAs base layer is exposed, the etching ends and the emitter mesa is formed.

Next, as shown in FIG. 1 (d), an Au-based alloy such as AuMn is formed on the entire surface of the substrate by a vacuum deposition method, and is patterned by ion milling as a photoresist film mask. The electrode 8 is formed. At this time, short-circuiting between the emitter electrode and the base electrode due to the AuMn thin film is avoided by side etching to the emitter layer introduced previously, and the base electrode is formed in self-alignment with the emitter mesa.

As described above, in this embodiment, by providing the InGaAs layer 4 as the side etching introduction layer, Al which is necessary for preventing a short circuit between the emitter electrode and the base electrode and forming a self-alignment of the base electrode with the emitter mesa.
Since the side etching on the GaAs emitter layer 5 can be controlled with high accuracy, it is possible to form the emitter mesa with high uniformity and suppress variations in device characteristics.

On the other hand, in the conventional example, since the GaAs base layer is also etched by chlorine plasma, it is impossible to fabricate the element having the structure shown in the embodiment by dry etching. In addition, the emitter layer is made of n-type Al
If GaAs and the base layer are p-type InGaAs, the etching is almost stopped when the base layer is exposed, and side etching can be introduced into the emitter layer by overetching. Is difficult to detect, and it is difficult to exactly know the start time of overetching. Therefore, it is impossible to control the side etching amount with high accuracy, and variations in device characteristics cannot be avoided.

In this embodiment, the etching gas may be a chlorine compound such as boron trioxide (BCl ₃ ) or carbon tetrachloride (CCl ₄ ) or hydrogen chloride (HCl) other than chlorine. As InA
It may be a laminated film formed of any of In-containing materials such as 1GaAs and InGaP, or a combination thereof.
Further, as an embodiment of the invention of claim 2 shown in FIG. 2, when the position of the side etching introduction layer is about several tens nm from the emitter-base interface as in the manufacturing process of the emitter top type GaAs bipolar transistor. Also has the same effect. In this case, a depleted surface protection layer (guard ring) is simultaneously formed around the emitter mesa.

CCl is used as an etching gas.
_{If 2} F ₂ and a mixed gas of Cl ₂ and SF ₆ are used, a compound containing Al such as AlGaAs can be used as the side etching introduction layer when the material thin film to be etched is GaAs. FIG. 3 shows a cross-sectional view of a heterojunction bipolar transistor having a structure using AlGaAs as a side etching introduction layer (also serving as an emitter layer) after forming up to the base electrode.

In the above embodiments, the side etching amount can be controlled with high accuracy and etching damage to the substrate can be reduced.

[0018]

As described above, according to the present invention, by providing the side etching introduction layer between the substrate and the thin film to be etched, it is possible to perform anisotropic etching of the side etching introduction layer by ions. Then, the layer to be etched on the side etching introduction layer is isotropically etched by radicals or the like to introduce the side etching. Since the amount of side etching is determined by the time during which anisotropic etching is performed on the side etching introduction layer, it is possible to control the side etching amount with high accuracy by changing the thickness of the side etching introduction layer. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view in order of the manufacturing steps of an emitter top type GaAs heterojunction bipolar transistor for explaining an embodiment of the invention of claim 1 of the present invention up to the formation of a base electrode.

FIG. 2 is a cross-sectional view of an emitter-top type GaAs heterojunction bipolar transistor for explaining an embodiment of the second aspect of the present invention after completion of a base electrode.

FIG. 3 is a cross-sectional view of an emitter-top type GaAs heterojunction bipolar transistor for explaining an embodiment of the invention of claim 3 of the present invention after formation of a base electrode.

FIG. 4 is a sectional view showing the order of steps for explaining a conventional dry etching method.

[Explanation of symbols]

1 substrate 2 n-type GaAs collector layer 3 p-type GaAs base layer 4 n-type InGaAs side etching introduction layer 5 n-type AlGaAs emitter layer 6 proton ion implantation damage layer 7 emitter electrode 8 base electrode 9 AuMn 10 depleted on the emitter Surface protection layer (guard ring) 11 n-type GaAs emitter cap layer 12 n-type AlGaAs side etching introduction layer (emitter layer)

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 29/73 H01L 29/72

Claims (5)

[Claims] 1. A step of sequentially depositing and forming on a substrate a side etching introduction layer having a low etching rate and a thin film made of a substance capable of etching with the same type of plasma as the side etching introduction layer and having a high etching rate. And a step of performing dry etching in plasma in which both ions for anisotropically etching the thin film and the side etching introduction layer and radicals for isotropically etching exist. . 2. The dry etching method according to claim 1, further comprising the step of depositing and forming a thin film made of the same kind of material as the thin film before forming the side etching introduction layer on the substrate. 3. The dry etching according to claim 1 or 2, wherein the thin film has a GaAs film, an AlGaAs film, or a laminated structure formed by combining them, and the side etching introduction layer is a compound thin film containing In. Method. 4. The dry etching method according to claim 1, wherein the thin film is a GaAs film, and the side etching introduction layer is a compound thin film containing Al. 5. The dry etching method according to claim 1, wherein the side etching introduction layer is made of SiO ₂ or SiO ₂ containing nitrogen.