JPH0877099A - Dma controller - Google Patents

Abstract

PURPOSE: To provide the DMA controller which lightens the load on a CPU. CONSTITUTION: The DMA controller is equipped with an address register 4 which stores address information of a main memory 33 stored with parameters used for transfer, a 1st parameter register 42 which stores parameters used for current transfer, a 2nd parameter register 48 which stores parameters used for next-time transfer, a DMA address read-in control part 45 which reads the parameters out of the main memory 33 according to the address information in the address register 44 and registers them in the 2nd parameter register 48, and a DMA transfer control part 47 which controls DMA transfer on the basis of the parameters moved from the 2nd parameter register 48 to the 1st parameter register 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral device, a main memory device, or a main memory device and a peripheral device.
The present invention relates to a DMA controller that directly transfers data without going through the CPU, and particularly, a DMA that reduces the load on the CPU.
Regarding the controller.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional DMA controller 3
3 is a block diagram showing the configuration of the main part of the CPU 1. Until now, only one set of parameter registers 12 for holding parameters related to DMA transfer is provided, and the CPU 1
Registers the transfer parameters in the parameter register 12,
The control unit 6 has executed the DMA transfer based on the transfer parameter registered in the parameter register 12.

FIG. 11 is a diagram schematically showing the structure of the parameter register 12. Parameter register 12
Is an address register 2 that holds the transfer start address
0, a length register 21 for holding the number of transfer words, and a command register 22. The command register 22 holds information indicating whether there is a next transfer after the current transfer.

In the DMA controller 3 having such a configuration, since there is one set of parameter registers for holding the transfer range of the DMA data, when there are a plurality of DMA transfers in which the memory addresses are not continuous, the CPU 1 sets the parameters related to the DMA transfer. Since it is necessary to set the parameter register 12 for each DMA transfer and then activate the DMA transfer, there is a problem that the load on the CPU becomes heavy.

In order to solve such a problem, for example, Japanese Unexamined Patent Publication No. 4-264652 proposes a method of providing two sets of parameter registers 4 and 5 as shown in FIG. In such a system, when the CPU 1 sets parameters in the second parameter register 4 and instructs the start of data transfer, the contents of the second parameter register 4 are moved to the first parameter register 5. The control unit 6 starts data transfer with the I / O device 7 based on the transfer parameter moved to the first parameter register 5.

If there is a next transfer after the current transfer,
A status indicating that the second parameter is empty is set and an interrupt is issued to the CPU 1. By the interruption, the CPU 1 sets the next transfer parameter in the second parameter register. As described above, the parameter register has the two-stage configuration and has the status for notifying the setting of the parameter, which enables continuous DMA transfer to discontinuous memory addresses (physical addresses).

[0007]

In the above-mentioned conventional technique, an interrupt is issued to the CPU each time the DMA transfer of one continuous area is completed, and the CPU sets the parameter in the second parameter register, as before. However, there is a problem that the load on the CPU still remains heavy.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a DMA controller which reduces the load on the CPU.

[0009]

In order to achieve the above object, according to the present invention, an address register for storing address information of a main memory device in which a parameter used for a DMA transfer is stored and a current register used for the current transfer. The first parameter register for storing the parameters to be stored, the second parameter register for storing the parameters to be used for the next transfer, and the second parameter register for reading the parameters from the main storage device based on the address information of the address register. Parameter registration means for registering to the first parameter register, parameter moving means for moving the parameter stored in the second parameter register to the first parameter register, and DMA transfer based on the parameter moved to the first parameter register. It is characterized in that a control means for controlling is provided.

[0010]

According to the above construction, the address information of the parameters used in the DMA transfer on the main memory is stored in the address register, and the parameter registration means is
A parameter for DMA transfer is read from the main storage device based on the address information stored in the address register, and is registered in the second parameter register. Therefore, since the parameter registered in the main storage device until now is registered in the second parameter register, the interrupt to the CPU, which has been performed every DMA transfer, becomes unnecessary, and the load on the CPU is reduced.

[0011]

1 is a block diagram showing the structure of a DMA controller 30 which is an embodiment of the present invention. I / O
Data is read from and written into the device 31 by the DMA controller 30. CPU32 is DM
Writing / reading to / from the internal register of the A controller 30 is performed. In the main memory 33, the I / O device 31
The data output to or the data input from the I / O device 31 is stored. In addition, in the main memory 33,
As will be described later with reference to FIG. 7, an address table 60 holding a transfer address and a transfer size number (hereinafter, these may be collectively referred to as an address entry) that are parameters of the DMA transfer is stored. The address / data line 34 is an external bus for address signals and data signals, and the control line 35 is an external bus for control signals.

The decoder unit 40 includes a DMA controller 3
Generates a select signal to the 0 internal register. The arbiter unit 41 arbitrates the internal bus of the DMA controller 30. The table address register 44 holds the storage address of the address table 60 on the main memory 33. The first and second parameter registers 42 and 48 store transfer parameters such as a transfer address and a transfer size number required for DMA transfer.

The DMA address read control unit 45 creates an address entry (transfer address and transfer size number) for the DMA transfer based on the address information held in the table address register 44.
The control for reading from the address table 60 on the third layer and writing to the second parameter register 48 is performed. DM
The A transfer control unit 47 controls the DMA transfer based on the address entry written in the first parameter register 42. The control register 46 holds the internal state of the DMA controller 30. The data buffer 43 includes the main memory 33 to the I / O device 31.
The data output to or the data input from the I / O device 31 is held.

FIG. 2 is a diagram schematically showing the configuration of the control register 46. A table size field (Table Size) 5 for holding the size of the address table 60 (see FIG. 7) in the main memory 33.
1, a start field 52 (STAR) holding information indicating that the transfer of the address entry from the address table 60 to the second parameter register 48 has started.
T), D between main memory 33 and I / O device 31
A read field (RD) 53 holding information indicating the MA transfer direction, an address transfer error field (AERR) 54 holding information indicating that an error occurred during the transfer of the address entry, the main memory 33 and the I / O. A DMA transfer error field (TERR) 55 that holds information indicating that an error has occurred during DMA transfer between the devices 31, and a transfer end field (COM that holds information that all transfers have ended).
P) 56.

FIG. 3 is a block diagram showing the configuration of the first parameter register 42. The tristate buffers 81 and 82, the comparator 83, and the registers 84 and 8 are shown.
5, multiplexers 86 and 87, an adder 88 and a subtractor 89.

The transfer address is held in the register 84. The transfer address is read from the input signal ADRIN into the register 84 via the multiplexer 86. The transfer address is incremented by the adder 88 each time one DMA data is completed. Register 8
The number of transfer sizes is held in 5. The transfer size number is read from the input signal SIZIN into the register 85 via the multiplexer 87. The transfer size number is decremented by the subtractor 89 each time one DMA data is completed.

The tri-state buffer 81, when the OE1 signal output from the DMA transfer control unit 47 is "1",
The transfer address is output to the internal bus, and the tri-state buffer 82 outputs the OE output from the DMA transfer control unit 47.
When the two signals are "1", the transfer size number is output to the internal bus. The OE1 signal and the OE2 signal do not become "1" at the same time. The comparator 83 outputs "1" as the END signal when the transfer size number is "0".

FIG. 4 is a block diagram showing the configuration of the second parameter register 48, which includes two registers 90,
It is composed of 91. The register 90 holds the transfer address, and the register 91 holds the transfer size number.

FIG. 5 is a block diagram showing the structure of the table address register 44, which is composed of a tri-state buffer 92, a register 93, a multiplexer 94, and an adder 95. The register 93 holds the storage address on the main memory 33 of the address entry used in the next DMA transfer. This transfer address is incremented by the adder 95 each time one DMA data transfer is completed.

FIG. 6 is a diagram showing an example of the data stored in the main memory 33. Only the black area is I / I.
DMA transfer is performed to the O device 31. FIG. 7 schematically shows the configuration of the address table 60 that holds the address entries relating to the transfer data of FIG. 6, and is composed of a plurality of address entries 61 to 66 that store transfer addresses and transfer size numbers of discontinuous areas. It is configured. The address of the address entry 61 is the address table 6 concerned.
The start address is 0.

FIG. 8 is a flowchart showing the operation of the DMA address read control unit 45 when the DMA controller 30 makes a DMA transfer between the main memory 33 and the I / O device 31, and FIG. 9 is a DMA transfer control unit 47. 3 is a flowchart showing the operation of FIG. The operation when the DMA controller 30 writes data in the discontinuous address range on the main memory 33 to the I / O device 31 will be described below with reference to FIGS. 6 to 9.

First, the CPU 32 uses the main memory 3
The top address (for example, “20300”) of the address table 60 of 3 is written in the table address register 44, the table size field 51 of the control register 46 is set to “6” as the size of the address table 60, and the start field 52 is set to , "1" indicating the start of transfer, and "1" indicating that the transfer direction is from the main memory 33 to the I / O device 31 is written in the read field 53.

When "1" is written in the start field 52 of the control register 46 by the CPU 32, the DMA address read control unit 45 is activated (step A1). DMA address read control unit 45
Asserts the internal bus request signal BR0 (step A2). The arbiter unit 41 arbitrates the use of the internal bus between the DMA address read control unit 45 and the DMA transfer control unit 47. At this time, since the DMA transfer control unit 47 has not requested the internal bus, the arbiter unit 41
Asserts the internal bus permission signal BG0 to the DMA address read control unit 45 (step A3). Upon receiving the internal bus permission signal BG0, the DMA address read control unit 45 negates the internal bus request signal BR0 and makes a bus request to the control line 35 of the external bus (step A4) to grant the right to use the external bus. Acquire (step A5).

The DMA address read control unit 45 which has acquired the right to use the external bus operates the table address register 4
The data of No. 4 is output to the address / data line 34 as address data (step A6). As a result, the data of the address entry 61 which is the first data of the address table 60 of the main memory 33 is read into the second parameter register 48 (step A10). If an error occurs while reading the address entry 61 (step A7), the control register 46 is sent to the AE
RR is asserted (step A8). The control register 46 sends an interrupt signal IN to the CPU 32.
CPU3 asserts that TRQ is asserted and an error has occurred.
2 is notified (step A9).

On the other hand, the second parameter register 48 of the data of the address entry 61 does not generate an error.
When the reading to the end is completed, the second parameter register 48 sets the V signal indicating that the data is valid to "1". At the same time, the DMA address read control unit 4
5 sets the NEXT signal to "1". When the NEXT signal becomes "1", the value of the table size field 51 is decremented by 1 in the control register 46.

The DMA address read control unit 45 stops reading the next address entry 62 until the V signal output from the second parameter register 48 becomes "0". When the V signal becomes “0”, the DMA address control unit 45 sets the data of the next address entry 62 to the second data.
Parameter register 48. The DMA address read control unit 45 continues to write the address entry of the address table 60 to the second parameter register 48 until the table size field 51 of the control register 46 becomes "0" (steps A11, 1).
2).

At this time, the DMA transfer control unit 47 receives the second parameter when the V signal output from the second parameter register 48 becomes "1" (step B1), as shown in the flowchart of FIG. The data (address entry) of the register 48 is transferred to the first parameter register 42.
And set the CLR signal to "1" (step B
2). The second parameter register 48, when the CLR signal output from the DMA transfer control unit 47 becomes “1”,
The V signal is set to "0".

The DMA transfer control unit 47 starts the DMA transfer from the main memory 33 to the I / O device 31, based on the address entry written from the second parameter register 48 to the first parameter register 42. D
The MA transfer control unit 47 asserts the internal bus request signal BR1 (step B3). The arbiter unit 41 is DMA
The use of the internal bus is arbitrated between the address read control unit 45 and the DMA transfer control unit 47. After arbitration, the arbiter unit 41 asserts the internal bus permission signal BG1 (step B4). DM receiving the internal bus permission signal BG1
The A transfer control unit 47 negates the internal bus request signal BR1 (step B5).

The DMA transfer control unit 47 makes a bus request to the control line 35 of the external bus (step B6) and acquires the right to use the external bus (step B6). The DMA transfer control unit 47, which has acquired the right to use the external bus, uses the data in the register 84 (address field) of the first parameter register 42 as an address and sets the address / data line 34.
To the data buffer 43 (step B11).
If an error occurs during this data reading (step B8), TERR of the control register 46 is asserted (step B9). The control register 46 asserts the interrupt signal INTRQ to the CPU 32 and notifies the CPU 32 that an error has occurred (step B10).

The data read into the data buffer 43 without any error is sent to the I / O device 31. The DMA transfer control unit 47 increments the register 84 (address field) of the first parameter register 42 and decrements the register 85 (size field). When the register 85 becomes “0”, the first parameter register 42 sets the END signal to “1” to notify the DMA transfer control unit 47 that the transfer is completed. The DMA transfer control unit 47 continues the DMA transfer until the END signal becomes "1" or an error occurs.

When the DMA transfer ends normally, the DMA transfer control unit 47 determines whether or not the next transfer needs to be performed.
Judgment is made based on the V signal output from the parameter register 48 of No. 1, and when it is "1", the DMA transfer is performed by the above method, and when it is "0", it waits until the V signal becomes "1" (step B12).

When all data transfer is completed without error, the table size field 51 of the control register 46 is "0", the V signal from the second parameter register 48 is "0", and the V signal from the first parameter register 42 is. Since the END signal becomes "1", this causes the control register 46 to transfer end field (COMP) 5
Set 6 to “1” and assert INTRQ to C
The PU 32 is notified that the data transfer is completed.

According to the present embodiment, the storage address of the address table 60 provided on the main memory 33 for holding the address entry (transfer address and transfer size number: transfer parameter) of the DMA transfer is the table address. The DMA address read control unit 45 stored in the register 44, based on the address information stored in the table address register 44,
Address entry for DMA transfer to main memory 3
3 is read from the address table 60 and written in the second parameter register 48, interrupts to the CPU 32, which have been performed for each DMA transfer so far, are unnecessary, and the load on the CPU is reduced.

[0034]

As described above, according to the present invention, in order to register the transfer parameter (address entry) registered in the main storage device in the second parameter register, the DMA transfer is performed for each DMA transfer. Since the interrupt to the CPU that has been performed is unnecessary, the load on the CPU is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a diagram schematically showing a configuration of a control register.

FIG. 3 is a block diagram showing a configuration of a first parameter register.

FIG. 4 is a block diagram showing a configuration of a second parameter register.

FIG. 5 is a block diagram showing a configuration of a table address register.

FIG. 6 is a diagram showing data stored in a main memory.

FIG. 7 is a diagram schematically showing a configuration of an address table.

FIG. 8 is a flowchart showing an operation of a DMA address read control unit.

FIG. 9 is a flowchart showing an operation of a DMA transfer control unit.

FIG. 10 is a block diagram of a conventional DMA controller.

FIG. 11 is a diagram schematically showing a configuration of a parameter register 12.

FIG. 12 is a block diagram of a conventional DMA controller.

[Explanation of symbols]

30 ... DMA controller, 31 ... I / O device, 32 ...
CPU, 33 ... Main memory, 34 ... Address / data line, 35 ... Control line, 42 ... First parameter register,
44 ... Table address register, 45 ... DMA address read control unit, 46 ... Control register, 47
... DMA transfer control unit, 48 ... Second parameter register, 60 ... Address table

Claims (1)

[Claims] 1. An address register for storing address information of a main memory device in which a parameter used for a DMA transfer is stored, a first parameter register for storing a parameter used for a current transfer, and a next parameter used for the next transfer. A second parameter register for storing the parameter to be stored, parameter registration means for reading the parameter from the main memory based on the address information of the address register, and registering the parameter in the second parameter register; A parameter moving means for moving the stored parameter to the first parameter register, and a control means for controlling the DMA transfer based on the parameter moved to the first parameter register. Parameter stored in parameter register 2 A DMA controller characterized in that, when the data is moved to the first parameter register, the next parameter stored in the main memory is registered in the second parameter register.