JPH0877068A - Multiprocessor system and memory allocation optimizing method - Google Patents

Abstract

PURPOSE: To enable memory allocation which makes the most of the capability of a cache. CONSTITUTION: The multiprocessor system which operates data on a memory in specific cache line units is equipped with a data recognition means 12 which recognizes data only to be written when a program analysis part 11 which takes an analysis for generating an executable object program for a source program, a cache size recognition means 14 which recognizes the size of a cache line of its system, and a data arranging means 15 which arranges data only to be read on the same cache line where read and write data accessed at the same time with the data only to be read so that plural data accessed by the program at the same time are stored in the cache from the memory at the same time when a code generation part 13 performs code generation according to the result of the analysis.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system to which a plurality of processors each having a cache are connected and a method for optimizing memory allocation.

[0002]

2. Description of the Related Art In recent years, the rate of memory access processing is extremely low compared to the rate of processor arithmetic processing, and even if processor arithmetic processing is faster,
There is a problem that the performance of the entire system does not improve because the access processing to the memory does not become faster.

In order to solve this problem, there is a technique called cache. The cache is a small-capacity high-speed memory arranged in or near the processor, and plays a role as a high-speed buffer for data on the memory accessed by the processor.

On the other hand, the multiprocessor technology has been developed and many processors each having a cache have been connected to each other. In a multiprocessor system, a large number of processors each hold a copy of memory in its cache, so that it becomes necessary to maintain data consistency between the caches. A technology called "snoop" is a technique for ensuring the consistency of this data.

There are various methods for the snoop function. In any of the methods, for example, when a plurality of processors having a cache sequentially update common data in a memory, the target data is cached by each processor. Be consistent by passing between in turn.

However, when data is shared among a large number of processors, snooping between caches increases the number of operations for data consistency (data passing), and the snooping operation connects the processors. However, there was a problem that the multi-processor system performance was not improved due to the saturation of the bus.

[0007]

In a computer system in which a plurality of processors each having a cache are connected as described above, bus traffic increases in order to ensure consistency of cache data of each processor. However, the multiprocessor system performance may be degraded.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a multiprocessor system and a method for optimizing memory allocation, which make the most of the cache capability.

[0009]

SUMMARY OF THE INVENTION The present invention is a multiprocessor system in which a plurality of processors each having a cache are connected, in which data on a memory is operated in predetermined cache line units. A data recognizing means for recognizing read-only data when performing an analysis to create an executable target program for the source program, and a cache size recognizing means for recognizing the size of a cache line in the own system. When performing code generation according to the result of analysis, based on the recognition results by the data recognizing means and the cache size recognizing means, a plurality of data accessed by a program at the same time are stored in a cache from a memory , Read only data read above Wherein the Mino write data data to be accessed at the same time is provided with the data arrangement means for arranging the same cache line on which is arranged.

Further, when arranging the data by the data arranging means and there are a plurality of cache lines in which the read-only data should be arranged, the read-only data is copied into a plurality of cache lines. It is characterized by further comprising copy data arranging means for arranging.

According to the present invention, a lock variable is added to a data structure, and when the data structure is accessed, the lock variable is set before the data structure is accessed, and the lock variable is added after the access to the data structure is completed. In a multiprocessor system in which a data structure shared by multiple processors is exclusively controlled by resetting, it is used in a program when performing an analysis to create an executable target program for a source program. A lock variable searching means for searching a lock variable for exclusively controlling a data structure, a data structure searching means for searching a data structure protected by the lock variable searched by the lock variable searching means, and an analysis result. In response to the code generation, the lock variable search means and the data Based on the search result by data structure retrieving means, characterized in that below one of the protected data structure by lock variable only equipped with a data structure allocation means to avoid the allocation in one cache line.

A copy data arrangement for allocating a copy of read data to be accessed in a portion other than the allocated data structure in the cache line between setting and resetting a lock for protecting the data structure. It is characterized by further comprising means.

Further, a buffer confirmation means for recognizing a buffer for input / output processing when performing analysis for creating an executable target program for the source program, and code generation according to the analysis result, And an allocation unit for allocating no more than one buffer for input / output processing in one cache line based on the recognition result by the buffer recognition unit.

[0014]

With such a configuration, in a multiprocessor system in which a plurality of processors each having a cache are connected, it is possible to improve the performance by utilizing the capacity of the cache.

That is, by arranging read-only data on the same cache line where read / write data that is accessed at the same time as read-only data is arranged, when executing processing for one data, Since the data will also exist in the cache,
The required number of data transfers from memory is reduced.

Further, when there are a plurality of cache lines in which the read-only data should be arranged, the read-only data is copied and arranged in each of the cache lines in which the read / write data is arranged, so that the caches are cached. It is possible to reduce the processing such as the delivery of the data.

Further, when the data structure shared by the multiprocessors is exclusively controlled, the data structure protected by the lock variable is set to 1 in one cache line.
By allocating less than this number, it is possible to prevent the lock control from making it impossible to access a data structure that originally does not require a lock.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a computer system according to an embodiment of the present invention. As shown in FIG. 1, the computer system according to the first embodiment includes a plurality of processors 1a, 1b, ...
The shared memory 2 shared by b, ... Has a multiprocessor system configuration connected by a bus 3.

In the multiprocessor system to which the present invention is applied, data transfer between the cache memory and the processor or the shared memory 2 is performed for each predetermined unit, that is, for each cache line.

The processor 1a is provided with a cache 4a and an optimizing means 5a. The function of the optimizing means 5a is realized by executing the optimizing program (compiler) stored in the shared memory 2 on the processor 1a. The other processors 1b, ... Can be similarly provided with the optimizing means 5b ,.

The optimizing means 5a has a function as shown in FIG. As shown in FIG. 2, the optimizing means 5a includes a program analyzing section 11 and a data recognizing means 1.
2, a code generation unit 13, a cache line size recognition unit 14, and a data arrangement unit 15.

The program analysis unit 11 analyzes a source program written in a predetermined programming language to create a computer-executable target program. The program analysis unit 11
Performs lexical analysis, syntactic analysis, semantic analysis, etc. on the source program.

The data recognizing means 12 recognizes the existence of the data to be read only among the data used in the program, based on the result analyzed by the program analysis section 11.

The code generation unit 13 includes the program analysis unit 1
A code serving as a target program is generated according to the analysis result in 1 and the recognition result by the data recognition means 12.

The cache line size recognizing means 14 is
It recognizes the cache line size of the local system where the program operates. The data arranging unit 15 determines the arrangement of the data in the shared memory 2 among the codes generated by the code generating unit 13. The data arranging means 15 arranges the read-only data recognized by the data recognizing means 12 in the same cache line as the cache line in which the read / write data accessed simultaneously with the read-only data is arranged. To do. As a result, simultaneously accessed data can be simultaneously brought from the shared memory 2 to the cache.

In the configuration shown in FIG. 2, the program analysis section 11 and the code generation section 13 constitute a compiler. Further, the compiler is provided with the functions of the data recognizing means 12 and the data arranging means 15. Further, the cache line size recognition means 14 is realized by the function of the OS (operating system) in the computer system, for example.

Next, the operation of the first embodiment will be described. The optimizer 5a optimizes the cache implemented in the system when the source program is compiled. First, the program analysis unit 11 analyzes a source program stored in a storage device (not shown) to be compiled. At this time, the data recognition means 12 identifies the data used only for reading. Data recognition means 12
The data recognized by is considered in the data arrangement by the data arrangement means 15.

The code generation unit 13 includes the program analysis unit 1
A code is generated based on the analysis result of 1. At this time, the code generation unit 13 generates a code relating to data in consideration of the cache line size of its own system identified by the cache line size recognition unit 14.

FIG. 3 shows the optimizing means 5 of the first embodiment of the present invention.
It is a flow chart which shows a flow of processing of data arrangement means 15 in a. The data arranging unit 15 arranges the code relating to the data generated by the code generation unit 13 in consideration of the cache line so that the cache can be effectively used.

First, the data arranging means 15 arranges the read / write data in the cache line (step A).
1). After that, the data arranging means 15 determines whether or not there is read-only data (data recognized by the data recognizing means 12) to be accessed around the read / write data that has been arranged in step A1 (near before and after the program execution process). Is checked (step A2).

If the target data exists, the data arranging means 15 checks whether or not the read-only data is still arranged (step A).
3). If it is not arranged yet, the data arranging means 15 arranges the read-only data in the same cache line as the read / write data arranged in step A1 (those around the currently read-only data). (Step A4).

If it is determined in step A3 that read-only data has already been placed in any of the cache lines, the data placement means 15
Do not arrange the read-only data.

Thus, for all the read / write data, if there is read-only data in the vicinity of each,
This data is placed in the same cache line as the read / write data.

FIG. 4 is a diagram for specifically explaining how data is arranged in the cache line of the shared memory 2. Note that the program shown in FIG.
It is shown by the format of the source program.

Function 1 in the program shown in FIG.
First refers to "reference data A" and then "updates data B". Here, the data A is used only for reading.

In this case, the data B to be read / written is placed in a predetermined cache line in step A1. The data A is identified as existing around the process of "updating the data B" in step A2, and in step A4, as shown in FIG. 3 (b), the rest of the cache line in which the data B is arranged. Is placed in the part.

By arranging the data A and the data B in the same cache line, when the program is executed (the process shown in FIG. 4A), the data A is transferred from the shared memory 2 when the "reference to the data A" is made. The data B transferred to the cache and simultaneously arranged in the same cache line is also transferred to and stored in the cache. Therefore, when executing the process of “updating the data B”, since the data B already exists in the cache, it is not necessary to transfer the data from the shared memory 2 again. That is, the cache can be effectively used.

Next, a second embodiment of the present invention will be described. In the second embodiment, as in the first embodiment, the optimizing means 40a, 40b, ... According to the second embodiment are provided on the computer system shown in FIG.

The optimizing means 40a has a function as shown in FIG. As shown in FIG. 5, the optimizing unit 40a includes a program analyzing unit 41, a data recognizing unit 42, a code generating unit 43, a cache line size recognizing unit 44, a data arranging unit 45, and a copy data arranging unit 46. There is.

The program analysis unit 41 analyzes a source program written in a predetermined programming language to create a computer-executable target program. The program analysis unit 41
Performs lexical analysis, syntactic analysis, semantic analysis, etc. on the source program.

The data recognizing means 42 recognizes the presence of the data to be read only among the data used in the program, based on the result analyzed by the program analysis unit 41.

The code generation section 43 includes a program analysis section 4
A code serving as a target program is generated according to the analysis result in 1 and the recognition result by the data recognition means 42.

The cache line size recognition means 44 is
It recognizes the cache line size of the local system where the program operates. The data placement means 45 determines the placement of the data in the shared memory 2 among the codes generated by the code generation unit 43. The data arranging unit 45 arranges the read-only data recognized by the data recognizing unit 42 on the same cache line as the cache line on which the read / write data that is accessed simultaneously with the read-only data is arranged. To do. As a result, simultaneously accessed data can be simultaneously brought from the shared memory 2 to the cache.

The copy data arranging means 46 makes a copy of the read only data when the data arranging means 45 has already arranged the data to be read only in another cache line, The data is arranged in the same cache line in which data to be read / written which is accessed simultaneously with the data is arranged.

Next, the operation of the second embodiment will be described. The optimizer 40a optimizes the cache implemented in the system when the source program is compiled. First, the program analysis unit 41 analyzes a source program to be compiled, which is stored in a storage device (not shown). At this time, the data recognition unit 42 identifies the data used only for reading. Data recognition means 4
The data recognized by 2 is taken into consideration in the data arrangement by the data arrangement unit 15 and the copy data arrangement unit 46.

The code generation section 43 includes a program analysis section 4
A code is generated based on the analysis result of 1. At this time, the code generation unit 43 takes into consideration the cache line size of the own system identified by the cache line size recognition unit 44, and performs code generation regarding data.

FIG. 6 shows the optimizing means 4 of the second embodiment of the present invention.
It is a flow chart which shows a flow of processing of data arrangement means 45 and copy data arrangement means 46 in 0a. The data arranging unit 45 arranges the code relating to the data generated by the code generating unit 43 in consideration of the cache line so that the cache can be effectively used.

First, the data placement means 45 places the read / write data in the cache line (step B).
After that, the data arranging unit 45 determines whether or not there is read-only data (data recognized by the data recognizing unit 42) to be accessed around the read / write data that has been arranged in step B1 (near the front and rear of the program execution process). Is checked (step B2).

Here, if the target data exists, the data arranging means 45 checks whether or not the read-only data is still arranged in another cache line (step B3).

If the data is not arranged yet, the data arrangement means 45 makes the read-only data the same as the read / write data arranged in step B1 (the data present in the periphery of the currently read-only data). It is placed in the cache line (step B4).

If it is determined in step B3 that read-only data has already been placed in any of the cache lines, copy data placement means 4
6 makes a copy of the read-only data (step B5).

Then, the copy data arranging means 46 arranges the data created by copying in the same cache line where the data to be read / written which is accessed simultaneously with the data is arranged (step B).
6).

FIG. 7 is a diagram for specifically explaining how data is arranged in the cache line of the shared memory 2. Note that the program shown in FIG.
It is shown by the format of the source program.

Function 1 in the program shown in FIG. 7 (a)
First refers to “data A” and then “updates data B”. Function 2 first refers to “data A”
Then, "data C is updated" subsequently. Here, the data A is used only for reading.

In this case, the data B and the data C to be read / written are placed in the predetermined cache lines in step B1. Function 1 data A
Are identified in step B2 as being in the vicinity of the "update data B" process, and step B4
In FIG. 7, as shown in FIG. 7B, the data B is placed in the remaining portion of the cache line.

Further, in step B3, the data A
Is determined to have already been placed in another cache line, a copy of data A is made and the data read / written that is accessed simultaneously with data A, that is, the rest of the cache line in which data C is placed. Place in the part of.

By arranging the data A and the data B in the same cache line, when the program is executed (the processing of the function 1 shown in FIG. 7A), the data A is shared when the "reference to the data A" is made. The data B transferred from the memory 2 to the cache and simultaneously arranged in the same cache line are also transferred to the cache and stored. Further, when the copy of the data A is referred to in the processing of the function 2, the data C arranged in the same cache line as the copy of the data A is also transferred and stored in the cache. Therefore, when the process of “updating the data C” is executed, the data C already exists in the cache, and it is not necessary to transfer the data from the shared memory 2 again. Also, since the read-only data is copied and placed in different cache lines, the data B
Even if the cache line in which is arranged exists in the cache of a certain processor, the processing of transferring this data to the cache of another processor becomes unnecessary. That is, the cache can be effectively used.

Next, a third embodiment of the present invention will be described. In the third embodiment, the optimizing means 70a, 70b, ... According to the third embodiment are provided on the computer system shown in FIG. 1 as in the first embodiment.

Generally, in a multiprocessor system,
There is a lock operation as a method of exclusive control of shared data in the shared memory 2. In the lock operation, a lock variable is prepared on the shared memory 2 for a certain shared data, the lock variable is secured before the shared data is processed, and the lock variable is cleared after the shared data is accessed.

When the process executed on the processor tries to secure the lock variable, if another process has already secured the lock variable, the process waits until the lock variable is cleared. , And the lock variable is secured as soon as it is cleared. This prevents multiple processors from accessing the same data at the same time, resulting in inconsistent data. The computer system of the third embodiment performs such exclusive control.

The optimizing means 70a has a function as shown in FIG. As shown in FIG. 7, the optimizing unit 70a includes a program analyzing unit 71, a lock variable searching unit 72, a data structure searching unit 73, and a code generating unit 7.
4 and data structure allocation means 75.

The program analysis unit 71 analyzes a source program written in a predetermined programming language to create a computer-executable target program. The program analysis unit 71
Performs lexical analysis, syntactic analysis, semantic analysis, etc. on the source program.

The lock variable retrieval means 72 retrieves the lock variable used in the program based on the result analyzed by the program analysis section 71. The data structure retrieving unit 73 retrieves a data structure protected by the lock variable retrieved by the lock variable retrieving unit 72 in the program analyzed by the program analysis unit 71.

The code generating section 74 includes a program analyzing section 7
A code to be a target program is generated according to the analysis result in 1. Based on the program analyzed by the program analysis unit 71 (lock variable search unit 72, data structure search unit 73), the data structure allocation unit 75 stores the data structure protected by the lock variable in one cache line. The allocation is performed so that only one or less is arranged.

In the configuration shown in FIG. 8, the program analysis unit 71 and the code generation unit 74 form a compiler. The program analysis unit 71 is further provided with the functions of the lock variable search means 72 and the data structure search means 73.

Next, the operation of the third embodiment will be described with reference to the flow chart shown in FIG. First, the program analysis unit 71 analyzes a source program to be compiled. At this time, the lock variable retrieval means 72 retrieves the lock variable used in the program (step C1). Also, the data structure search means 7
3 retrieves the data structure protected by the lock variable retrieved by the lock variable retrieval means 72 (step C2).

The code generator 74 is connected to the program analyzer 7
A code is generated based on the analysis result of 1. The data structure allocating means 75 sets the data structure searched in step C2 for the code relating to the data generated by the code generation unit 74 to the data structure protected by the lock variable in one cache line.
Allocation is performed so that only less than or equal to the number is arranged (step C3).

FIG. 10 is a diagram for specifically explaining how data is arranged in the cache line of the shared memory 2. Note that the program shown in FIG. 10A is shown in the format of a source program for convenience.

Function 1 in the program shown in FIG.
First "locks the lock variable A", "updates the data structure B", and "unlocks the lock variable A". Subsequently, the "lock variable C is locked", the "data structure D is updated", and the "lock variable C is unlocked".

In this case, the lock variable A and the lock variable C are retrieved in step C1, and the data structures B and D protected by different lock variables A and C are retrieved in step C2. In step C3, the data structure allocation means 75 arranges the data structures B and D in different cache lines, as shown in FIG. 9B.

By forcibly allocating the data structure B and the data structure D to different cache lines, it is possible to prevent the other data structure from becoming unusable because one data structure is locked and the other data structure is allocated to each cache line. The created data structure can be effectively used.

Next, a fourth embodiment of the present invention will be described. In the fourth embodiment, as in the first embodiment, the optimizing means 100a, 100b, ... According to the fourth embodiment are provided on the computer system shown in FIG. Fourth
The computer system in the embodiment also performs exclusive control similar to that in the third embodiment.

The optimizing means 100a has a function as shown in FIG. As shown in FIG.
The optimization means 100a includes a program analysis unit 101, a lock variable search unit 102, a data structure search unit 103, a code generation unit 104, and a data structure allocation unit 10.
5 and the copy data arranging means 106.

The program analysis unit 101, for a source program written using a predetermined programming language,
This is an analysis for creating a target program that can be executed by a computer. Program analysis unit 101
Performs lexical analysis, syntactic analysis, semantic analysis, etc. on the source program.

The lock variable retrieval means 102 retrieves the lock variable used in the program based on the result analyzed by the program analysis unit 101. The data structure search means 103 is a lock variable search means 1 in the program analyzed by the program analysis unit 101.
To retrieve the data structure protected by the lock variable retrieved by 02.

The code generator 104 is for generating a code to be a target program according to the analysis result of the program analyzer 101. The data structure allocation means 105, based on the program analyzed by the program analysis unit 101 (lock variable search means 102, data structure search means 103), stores the data structure protected by the lock variable in one cache line. The allocation is performed so that only one or less is arranged. Further, the data structure allocation means 105 arranges the data referred to from the acquisition to the release of the lock variable for protecting the data structure in the area other than the portion where the data structure is arranged in the cache line. To do.

The copy data arranging means 106 arranges the data, which is arranged by the data structure allocating means 105 and is referred to during the period from the acquisition to the release of the lock variable for protecting the data structure, to another cache line. If so, a copy of the data is placed only if the data is for reference only.

In the configuration shown in FIG. 11, the program analysis unit 101 and the code generation unit 104 constitute a compiler. The program analysis unit 101 is further provided with the functions of the lock variable search unit 102 and the data structure search unit 103, and the code generation unit 104 is further provided with the functions of the copy data arrangement unit 106 and the data structure allocation unit 105. There is. Reference numeral 102 denotes a lock variable search means, which searches for a lock variable used in the program. Reference numeral 104 is a means for searching a data structure protected by a lock variable. In the optimizing compiler of the present invention, only one data structure protected by a lock is arranged in one cache line based on the program analyzed by the program analysis unit. Then, in the cache line, the data to be referenced is arranged at a place other than the portion where the data structure is arranged, from the time the lock protecting the data structure is acquired to the time it is released. Also, if the data has already been placed in another cache line, a copy of the data is placed only if the data is referenced only.

Next, the operation of the fourth embodiment will be described with reference to FIG.
This will be described with reference to the flowchart shown in FIG. First,
The program analysis unit 101 analyzes a source program to be compiled. At this time, the lock variable search means 102 searches for the lock variable used in the program (step D1). Further, the data structure search means 103 searches for a data structure protected by the lock variable searched by the lock variable search means 102 (step D2).

The code generator 104 generates a code based on the analysis result of the program analyzer 101. The data structure allocation unit 105 is the code generation unit 1
For the code relating to the data generated by 04, set the data structure searched in step D2 to 1
Allocation is performed so that no more than one data structure protected by a lock variable is arranged in one cache line (step D3).

After that, the data structure allocation means 1
The step 05 examines whether or not there is data to be referred to from the acquisition of the lock variable that protects the data structure to the release of the data structure that has been arranged in step D3 (step D4).

Here, if the target data exists, the data structure allocation means 105 checks whether or not the data has not been placed in another cache line (step D5).

If not already arranged, the data structure allocation means 105 arranges the data in an area other than the portion where the data structure arranged in step D3 is arranged (step D6).

If it is determined in step D5 that the target data (data referred to during lock) has already been placed in any cache line, the copy data placement means 106 determines that A copy of the data is created (step B5).

Then, the copy data placement means 106
The data created by copying is arranged in the same cache line in which the data structure is arranged only when the data is reference only (step D8).

FIG. 13 is a diagram for specifically explaining how data is arranged in the cache line of shared memory 2. Note that the program shown in FIG. 13A is shown in the format of a source program for convenience.

Function 1 in the program shown in FIG. 13 (a)
First locks "lock variable A", "references data B", "updates data structure C", and "unlocks lock variable A". Then, "lock lock variable D", "reference data B", and "update data structure E"
Then, the “lock variable D is unlocked”.

In this case, the data structures C and E protected by different lock variables A and C in step D3 are arranged in different cache lines.
Further, as shown in FIG. 13B, the data structures C and E
The data B, which is a read-only target that is referenced between the acquisition and release of the lock variables A and D that protect the data, is arranged in the remaining portion of the cache line in which the data structure C is arranged, Also, a copy of the data B is placed in each of the remaining portions of the cache line where the data structure E is placed.

By forcibly arranging the data structure C and the data structure E in different cache lines, it is possible to prevent the other data structure from becoming unavailable because one data structure is locked, and the data structure is further protected. The data that is referenced from the time the lock variable is acquired to the time it is released is also placed in the same cache line, so when the data structure is stored in the cache, the data that is already referenced already exists in the cache. Therefore, there is no need to transfer the data from the shared memory 2 again. Further, even if the data structure is locked, the referenced data itself exists in the cache for each data structure, and therefore can be referenced.

In the above-mentioned first to fourth embodiments, the case where the data or data structure is arranged in the cache line has been described, but the areas used as the buffers for input / output processing should be arranged in the same manner. You can

FIG. 14 is a diagram showing how data is arranged by a compiler composed of a program analysis section and a code generation section. The program shown in FIG. 14A uses "buffer1" and "buffer2" as buffers for input / output processing. The program analysis unit analyzes the program to be compiled and retrieves the definition of the buffer, and the code generation unit, for each retrieved buffer, as shown in FIG. Make sure that no more than one I / O buffer is allocated to each. That is, after a certain cache line is arranged, another cache line is not arranged even if there is an empty area in the cache line.

By allocating no more than one buffer for input / output processing in one cache line, data in the cache line is transferred between cache memories each time a different buffer is used. Does not occur.

[0093]

As described in detail above, according to the present invention, in a multiprocessor system in which a cache is provided for each processor, it is possible to improve the performance by utilizing the capacity of the cache. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a functional configuration of an optimizing unit according to the first exemplary embodiment of the present invention.

FIG. 3 is a flowchart showing a processing flow of a data arranging means 15 in the optimizing means 5a according to the first embodiment of the present invention.

FIG. 4 is a diagram for specifically explaining how data is arranged in a cache line in the first embodiment of the present invention.

FIG. 5 is a block diagram showing a functional configuration of an optimizing unit according to a second exemplary embodiment of the present invention.

FIG. 6 is a flowchart showing a processing flow of a data arranging unit 45 and a copy data arranging unit 46 in the optimizing unit 40a according to the second embodiment of the present invention.

FIG. 7 is a diagram for specifically explaining how data is arranged in a cache line according to the second embodiment of the present invention.

FIG. 8 is a block diagram showing a functional configuration of an optimizing unit according to a third exemplary embodiment of the present invention.

FIG. 9 is a flowchart for explaining the operation of the third embodiment of the present invention.

FIG. 10 is a diagram for specifically explaining how data is arranged in a cache line according to the third embodiment of the present invention.

FIG. 11 is a block diagram showing a functional configuration of an optimizing unit according to a fourth exemplary embodiment of the present invention.

FIG. 12 is a flowchart for explaining the operation of the fourth embodiment of the present invention.

FIG. 13 is a diagram for specifically explaining how data is arranged in a cache line according to the fourth embodiment of the present invention.

FIG. 14 is a diagram for specifically explaining how an area used as a buffer for input / output processing according to the present invention is arranged in a cache line.

[Explanation of symbols]

11, 41, 71, 101 ... Program analysis unit 12,
42 ... Data recognition means, 13, 43, 74, 104 ... Code generation section, 14, 44 ... Cache line size recognition means, 15, 45 ... Data placement means, 46, 106 ... Copy data placement means, 72, 102 ... Lock variable search means, 73, 103 ... Data structure search means, 75, 10
5 ... Data structure allocation means.

Claims (10)

[Claims] 1. A multiprocessor system in which a plurality of processors each having a cache are connected, and data in a memory is operated in a predetermined cache line unit, which is executable for a source program. Data recognition means that recognizes the data to be read only when performing analysis to create the target program, cache size recognition means that recognizes the size of the cache line in the local system, and code depending on the analysis result. At the time of generation, based on the recognition result by the data recognizing means and the cache size recognizing means, the read-only data is read so that a plurality of data accessed simultaneously by the program are simultaneously stored in the cache from the memory. At the same time as the A multiprocessor system comprising: a data arranging unit arranged on the same cache line where the read / write data to be accessed is arranged. 2. When arranging the data by the data arranging means, when there are a plurality of cache lines in which the read-only data should be arranged, the read-only data is copied into a plurality of cache lines. 2. The multiprocessor system according to claim 1, further comprising copy data arranging means for arranging. 3. When a lock variable is added to a data structure and the data structure is accessed, the lock variable is set, the data structure is accessed, and the lock variable is reset after the access to the data structure is completed. Due to
In a multiprocessor system that exclusively controls the data structure shared by multiple processors, the data structure used in the program is exclusively controlled when performing analysis to create an executable target program for the source program. Lock variable searching means for searching a lock variable, a data structure searching means for searching a data structure protected by the lock variable searched by the lock variable searching means, and code generation according to an analysis result. At the time of execution, a data structure allocation means for allocating no more than one data structure protected by a lock variable in one cache line based on the search results by the lock variable search means and the data structure search means. And a machine characterized by Multiprocessor system. 4. Copy data allocating a copy of read-only data to be accessed in a portion other than an allocated data structure in a cache line between setting and resetting a lock for protecting the data structure. 4. The multiprocessor system according to claim 3, further comprising arranging means. 5. A multiprocessor system in which a plurality of processors each having a cache are connected, and data in a memory is operated in a predetermined cache line unit, which is executable for a source program. Buffer confirmation means for recognizing an input / output processing buffer when performing analysis for creating an object program, and input / output based on the recognition result by the buffer recognizing means when code generation is performed according to the analysis result. A multiprocessor system comprising: allocation means for allocating no more than one processing buffer in one cache line. 6. A multiprocessor system in which a plurality of processors each having a cache are connected, and data in a memory is operated in a predetermined cache line unit, which can be executed for a source program. Recognized when the data to be read is recognized when performing the analysis for creating the target program, the size of the cache line in the local system is recognized, and when the code is generated according to the analysis result. Depending on the size of the cache line, read-only data that is recognized at the same time as read-only data can be accessed at the same time as the read-only data that was previously recognized so that multiple data that the program accesses simultaneously can be stored in the cache from memory at the same time. Placed on the same cache line where is placed A method for optimizing memory allocation, comprising: 7. When the read-only data is arranged on the same cache line where the read / write data accessed at the same time as the read-only data is arranged, the cache line to which the read-only data should be arranged is 7. The memory allocation optimizing method according to claim 6, wherein when there are a plurality of data, the read-only data is copied and arranged in a plurality of cache lines. 8. When a lock variable is added to the data structure and the data structure is accessed, the lock variable is set, the data structure is accessed, and the lock variable is reset after the access to the data structure is completed. Due to
In a multiprocessor system that exclusively controls the data structure shared by multiple processors, the data structure used in the program is exclusively controlled when performing analysis to create an executable target program for the source program. Search the lock variable to be searched, search the data structure protected by the searched lock variable, and generate the code according to the analysis result. A method for optimizing memory allocation, characterized in that only one or less is allocated in the memory. 9. Allocating a copy of read-only data that is accessed between setting and resetting a lock protecting the data structure in a portion of the cache line other than the allocated data structure. 9. The method of optimizing memory allocation according to claim 8. 10. A multiprocessor system in which a plurality of processors each having a cache are connected, and data in a memory is operated in a predetermined cache line unit, which can be executed for a source program. Recognize the I / O processing buffer when performing analysis to create the target program, and recognize the I / O processing buffer in one cache line when generating code according to the analysis result.
A method for optimizing memory allocation, characterized in that only less than or equal to each number is allocated.