JPH087682B2 - Knowledge-based processor - Google Patents

Description

The present invention relates to a knowledge base processing device having a frame type as a knowledge base.

(B) Conventional technology With the development of knowledge engineering, the application of artificial intelligence technology to industries has expanded remarkably, and the knowledge base system is a typical example. The knowledge base system is a knowledge base that stores specialized knowledge specific to the problem domain in a certain format,
The knowledge base is composed of an inference mechanism which is separated and is a control mechanism for executing inference using the knowledge in the knowledge base. The frame model proposed by Minsky using the representation of knowledge for constructing the knowledge base as a model is a typical one along with the rule model (see "Introduction to Knowledge Engineering" by Haruki Ueno, published by Ohmsha).

In a frame-based knowledge-based system that uses a frame model as a knowledge representation model, the names of knowledge and concepts are frames, and the various attributes of knowledge and concepts in one frame and the relationships with other frames (knowledge and concepts) are slot. Thus, various aspects of the slot (attributes, structural properties, etc.) are represented by the facet, and the actual value corresponding to the facet is represented by the view. In other words, frame, slot,
Knowledge or concept is expressed in four groups, a Fasset and a Valieux. Since the feature of the frame-type knowledge base can express the rank relation of knowledge and concept by inheritance of slot, the abstract property is described in the upper frame, and only the attributes and properties unique to the frame are described in individual frames. The point is that it can be described by differential programming.

In the frame type knowledge base, a plurality of frame type data are often represented by a linked list as shown in FIG. Therefore, a flexible frame-type data structure can be realized for embedding data having various attributes in slot values or facet values, and for newly adding / deleting frames, slots, or facets.

(C) Problems to be solved by the invention However, in the representation of frame type data as shown in FIG. 4, the pointers of the linked list are sequentially traced when referencing or changing each field such as a frame, slot, or facet (for example, facet set). To refer to the value of 222 (Variyu 222), it is necessary to follow the sequence frame 1 → frame 2 → slot 21 → slot 22 → facet 221 → facet 222) (because frame, slot, and facet are just numbers) Since it is represented by a character string or a linked list, if you want to refer to the value of facet 222, you have to search sequentially for fields that have the same character string as the given facet 222 name). For this reason, there is a drawback that referencing and changing each field is very slow, and the operation of traversing this list occupies a large proportion of the basic arithmetic processing in frame type data. It has been a major cause of lowering the processing efficiency of the entire system.

D) Means for Solving the Problems The present invention is a knowledge base processing apparatus having a frame type of knowledge base consisting of a frame, a slot, a facet, and a version, and includes any one of a frame, a slot, and a facet. Searcher generating means for generating a searcher from the storage means, and storage means for storing the data of the view which is immediate data or pointer data corresponding to the searcher,
It has a judging means for judging whether the value-of-value data is immediate data or pointer data, and an auxiliary storage means for storing concrete data corresponding to the value-value pointer data.

E) The action data, the value data of the pointer, or the value data of the pointer, is stored in the storage means in correspondence with the searcher generated from the action frame, the slot, and the facet. By storing specific data in the auxiliary storage means, the frame-type data is retained only by the conventional linked list so that each field search process when referencing a frame, slot, facet, etc. or changing a view can be done. In this case, list traversing, which is a type of linear search, becomes unnecessary and speeds up.

F) Embodiment FIG. 1 is a schematic configuration diagram showing an embodiment of the device of the present invention, and FIG. 2 is a schematic diagram of a frame data structure memory (3) for storing frame type data consisting of a frame, a slot, a facet and a view. It is a block diagram.

(1) is a CPU that performs frame type knowledge processing as a knowledge base processing device, and (2) is frame type knowledge base interpretation /
System memory that stores execution programs and user-defined programs. (3) is a frame data structure memory that stores frame-type data consisting of frames, slots, facets, and versions. It includes a retrieving means for producing, and a storage means for storing the data of the view which is immediate data or pointer data corresponding to the retrieving means.

(4) is a linked list data storage memory as auxiliary storage means for storing a linked list, (5) is a vector data storage memory for storing structure data such as character strings and vectors / arrays, and (6) is a CPU (1 ) Is an instruction register for issuing a command to the structure memory (3), and (7), (8), and (9) are stored in the vector data storage memory (5), respectively, and serve as search keys for frame-type data. A frame pointer register, a slot pointer register, a face pointer register, (10) that holds the address information in the vector data storage memory (5) corresponding to the frame name, slot name, and facet name expressed by any character string ) Is a view register used when changing the slot value and the reset value.

(11) is a tag / information field separation circuit for separating a tag section indicating the data type of the value data output from the structure memory (3) and an information field indicating pointer data or immediate data as address information, (12) ) Is a judgment output control circuit as judgment means for judging the data type of the information field by the tag section separated by the separation circuit (11) and controlling the output to the system data bus, (13)
Is an output data latch for temporarily storing the information field data separated by the separation circuit (11).

(14) and (15) are the address list multiplexer 1, the address multiplexer 2, (16), (17), and (18), which select addresses for the linked list data storage memory (4) and the vector data storage memory (5), respectively. These are an output data latch (13), a link list data storage memory (4), a data buffer 1, a data buffer 2 and a data buffer 3 between the vector data storage memory (5) and the system data bus, respectively. Also, (C), (D),
(A) is a system command bus, system data bus, and system address bus for the CPU (1) to directly read and write to the system memory (2), linked list data storage memory (4), and vector data storage memory (5), respectively. Is.

Now, a case of referring to a certain value (that is, a value) will be described. This face value is represented by three (frame-a, slot-b, facet-c). First, the CPU (1) sets an instruction code corresponding to the facet reference function get-facet in the instruction register (6) in order to request the frame data structure memory (3) to perform the facet reference processing. Further, the CPU (1) stores the address information in the vector data storage memory (5) corresponding to each of the three character strings of frame-a, slot-b and facet-c, which are search keys, in the system memory (2). From the name table of the character atom registered in the system command bus (C),
The data is read using the system data bus (D) and the system address bus (A) and set in the frame pointer register (7), the slot pointer register (8), and the reset pointer register (9).

Thus, the frame data structure memory (3) is searched by the built-in associative data search mechanism.
a, slot-b, facet-c), a searcher (address) is generated, a facet value corresponding to this searcher is searched for, and output to the tag / information field separation circuit (11). The frame data structure memory (3) will be described in detail later.

The output of the asset value data is, for example, an information field (i) indicating the substance of the data as shown in FIG. 3A, and an attribute of the information field (data type, immediate data, pointer as shown in FIG. 3B). It is composed of a tag field (t) indicating information) and two fields are separated by a tag / information field separation circuit (11).

The separated tag information is sent to the judgment output control circuit (12), while the data of the information field is once latched in the output data latch (13). Judgment output control circuit (1
2) decodes the tag information and enables the data buffer 1 (16) when the data of the information field is an immediate value, so that the immediate data held in the output data latch (13) is transferred to the system data bus (D). Is output to. At the same time, the tag information (in this case, immediate data) decoded by the output control circuit (12) is sent to the CPU (1) via the system command bus (C).
Since the CPU (1) reads the data output to the system data bus (D) once as immediate data, the CPU (1) finishes executing the facet reference function get-facet. The timing at which the CPU (1) should read the data on the system data bus (D) is notified to the CPU (1) by the ack signal included in the system command bus (C) from the judgment output control circuit (12). .

On the other hand, when the data of the information field is the pointer of the linked list data, the tag information decoded by the judgment output control circuit (12) (in this case, the linked list data pointer) is the system command bus (C). ) Is sent to the CPU (1) and the link list pointer value held in the output data latch (13) is sent to the address multiplexer 1 (14), which is further sent from the judgment output control circuit (12) to the address multiplexer 1 (14). When the SELLIST signal for (14) is turned on, the output data latch (input from the system address bus (A) and the output data latch (12)) of the two address inputs to the address multiplexer 1 (14) is output ( The input from 12) is selected and output to the linked list storage memory (4). The link list data storage memory (4) stores the link list data corresponding to the preset value.
The cell contents corresponding to the linked list pointer value from (14) are output from the linked list data storage memory (4) to the data buffer 2 (17). Judgment output control circuit (1
At this point, 2) enables the data buffer 2 (17) and sends an ack signal to the CPU (1). CPU
In (1), since the judgment output control circuit (12) has previously notified that the data output to the system data bus (D) is the head cell of the linked list data,
Data buffer 2 (17) to system data bus (D)
The data output to is read as a binary tree cell. After that, read the linked list from the system data bus (D).
Directly from the CPU (1) via the data buffer 2 (17). However, the address for the linked list data storage memory (4) at this time is selected by the address multiplexer 1 (14) from the system address bus (A) when the SELLISTD signal from the CPU (1) is turned on. It is given to the link list data storage memory (4).

When the information field data is a vector data pointer, the tag information (in this case, a vector data pointer) decoded by the determination output control circuit (12) is transferred via the system command bus (C). The vector pointer value sent to the CPU (1) and held in the output data latch (13) is output to the system data bus (D) via the data buffer 1 (16) and read by the CPU (1). At the same time, the vector pointer value held in the output data latch (13) is sent to the address multiplexer 2 (15). Furthermore, the Selvector signal from the judgment output control circuit (12) to the address multiplexer 2 (15) is turned on, and two address inputs to the address multiplexer 2 (15) (input from the system address bus (A) and output data latch ( Of the inputs (13), the inputs from the output data latch (13) are selected and output to the vector data storage memory (5). The vector data storage memory (5) stores vector data (the number of vector data n as vector data header information, and n vector data strings below that) corresponding to the cassette version. When the vector pointer value from the address multiplexer 2 (15) is set, the corresponding vector data header information (vector data number n) is transferred from the vector data storage memory (5) to the data buffer 3
It is output to (18). At this time, the judgment output control circuit (12) enables the data buffer 3 (18) and sends an ack signal to the CPU (1). Since the CPU (1) has previously been notified from the determination output control circuit (12) that the data output to the system data bus (D) is the vector data number n, the data buffer 3 (1
The data output from 8) to the system data bus (D) is read as the number of vector data n. Then the CPU
(1) is the vector pointer value previously read via the data buffer 1 (16) (vector data start address value)
Then, based on the number n of vector data read via the data buffer 3 (18), n vector data are transferred via the system data bus (D) to the data buffer 3 (18).
Continuously read directly via (burst data transfer). However, the address for the vector data storage memory (5) at this time is SELVECTOR from the CPU (1).
When the D signal is turned on, the address from the system address bus (A) is transferred to the address multiplexer 2 (1
Vector data storage memory (5) selected by 5)
Given to.

In the above, the reference process of the asset value has been described. However, the assignment (change) process of the asset value (for example, a search key (frame-a slot-b facet
Use the facet-value "variable" in the facet corresponding to c).
A function that substitutes (put-facet frame-a slot-b facet-c "fa
cet-value ") execution), the CPU (1) also sets the facet-value represented by the tag as shown in Fig. 3A to the value register (10), and By requesting the substitution process to the frame data structure memory (3), it is possible to realize exactly the same high speed as in the case of the reset reference process. The process ends when the data is sent from the frame data structure memory (3) to the CPU (1).

Next, the frame data structure memory (3) will be described with reference to FIG. (19) is the instruction register (6)
Structure memory control circuit (20), which decodes the instructions from and controls the entire frame data structure memory (3),
(21), (22) and (23) are frame pointer register (7), slot pointer register (8), face pointer register (9) and view register (10) which are input registers to the structure memory (3). ) Value is held once, key buffer A1, key buffer A2, key buffer A
3 、 Variyu buffer A, (24) is key buffer A1 (2
0), key pointer A2 (21), key pointer which is a search key stored in key buffer A3 (22), a frame pointer, a slot pointer, and a hash pointer. A generating circuit, (25) is a bulk memory as a storage means for storing a customized value corresponding to the hash address (searcher) generated by the hash address generating circuit (24). The bucket accessed by the cache address is status (a code indicating the status in each bucket, which is either blank, deleted, or occupied with the key stored), frame pointer value, slot pointer value, and forward pointer. It is composed of five values, a set pointer value and a reset value. (26), (27),
(28), (29) and (30) are the status, frame pointer value (storing key), slot pointer value (storing key) and face pointer in one bucket read from the bulk memory (25), respectively. Status (store key), reset value Status buffer that temporarily holds the value, key buffer B1, key buffer B2, key buffer B3, key buffer B (31) is status buffer (26)
The word detection circuit that detects the status (blank state, deleted state, occupied state) held in the, (32) is the key buffer A1.
(20), Key buffer A2 (21), Key buffer A3 (22)
(33) A key match detection circuit that compares the search key held in the key and the stored key held in key buffer B1 (27), key buffer B2 (28), and key buffer B3 (29) to detect a match, (33) Performs registration, deletion, rearrangement of frame type structure data, rehash processing at the time of key collision, and control of the hash address generation circuit (24) according to the output states of the word detection circuit (31) and the key coincidence detection circuit (32). This is a hash calculation control circuit.

Now, similar to the above, frame-a, slot-b, facet-c
A description will be given of the process of referring to the subset value represented by. The instruction code is stored in the instruction register (6) by the CPU (1) as search key data.
The frame pointer value corresponding to frame-a, slot-b, facet-c, the slot pointer value, and the facet pointer value are the frame pointer register (7), the slot pointer register (8), and the facet pointer register (9). When stored in the memory, the structure memory control circuit (19), the key buffer A1 (20), the key buffer A2 (21), and the key buffer, respectively.
Input to A3 (22). The instruction code from the instruction register (6) is decoded by the structure memory control circuit (19) and used to generate a control signal for each block in the structure memory.

The key data held in the key buffer A1 (20), key buffer A2 (21), and key buffer A3 (22) is sent to the hash address generation circuit (24), where the frame pointer value, slot pointer value, and reset pointer are set. Value 3
A hash address generated from one set of data is calculated. (For a specific calculation method of the hash address, see “Information Processing” Vol. 24. No. 4, 1983, pp. 391 to 395, “Hash hash address”. Law "Reference by Tetsuo Ida).

The hash address calculated by the hash address generation circuit (24) is given to the bulk memory (25), and the bucket ((status, frame pointer value, slot pointer value, face set value 5 sets of pointer value and reset value))
Are collectively read from the bulk memory (25) and stored in the status buffer (26), the key buffer B1 (27), the key buffer B2 (28), the key buffer B3 (29), and the valid buffer B (30), respectively. The status code held in the status buffer (26) is decoded by the word detection circuit (31), and if it is blank or deleted, the facet value reference processing (get-facet frame-a slot-b facet-c) is performed. ), The facet corresponding to the search key (frame-a slot-b facet-c) does not exist in the frame-type data. Therefore, an error code indicating that is found from the word detection circuit (31) in the structure memory. CP via control circuit (19)
Sent to U (1).

If the status code is occupied, the search key (contents of key buffer A1 (20), key buffer A2 (21), key buffer A3 (22)) and storage key (key buffer B1
(27), Key buffer B2 (28), Key buffer B3 (29)
Content) is compared by the key coincidence detection circuit (32). This is because the injectivity (one-to-one correspondence) between the search key and the hash address value is not necessarily taken. When the search key and the stored key are matched by the key match detection circuit (32), there is no key collision, so a match detection signal is sent to the structure memory control circuit (19). At the same time, the output enable signal for the variable buffer B (30)
OUTEN is sent from the key match detection circuit (32), the preset value held in the valid buffer (30) is output to the tag / information field separation circuit (11), and the data ready signal is sent to the tag / information field. It is sent to the separation circuit (11) and the facet valley is taken in.

On the other hand, if the search key and the storage key do not match by the key match detection circuit (32), there is no one-to-one correspondence between the search key and the hash address value (this is the key collision state). Therefore, the key match detection circuit (3
2) The key mismatch detection signal is a structural memory control circuit (19)
To the hash operation control circuit (33). The hash operation control circuit (33) sends a rehash instruction (recalculation of the hash address value) to the hash address generation circuit (24). The hash address generation circuit (24) uses the hash address value calculated immediately before and the number of rehashes to calculate
Calculate the next hash address value and bulk memory (25)
Give to. This process is performed until the search key and the storage key match. Such a retrieval process is called a rehashing method.

Average number of searches (an average of hash count prob until the reference value is found) in the search process by the rehashing method
E (prob) is, for example, "Journal of Japan Society for Management Engineering" Vol.30, No.
3, 1979, p. 224 to p. 230, "Associative information model capable of compact processing system" Using the algorithm of rehashing method as described in Masayuki Ida, E (prob) =-( 1 / ρ) ln (1-ρ).

Here, ρ is the ratio of all buckets in the hash area.

From the above equation, the average number of searches is about 2 even if ρ is 80% or more.
It only needs to be done once.

Although the above description has been made of the hue reference processing, the hue value substituting processing is almost the same.

According to the present invention, a retrieval element is generated from three elements of a frame, a slot, and a facet, and the retrieval data is stored in the bulk memory in association with the retrieval element, which is immediate data or pointer data. By storing the basic data pointed to by the pointer data in the linked list data storage memory or vector data storage memory, any data structure such as linked list data or vector data can be embedded in the view, and the advantages of linked list representation It is possible to eliminate the need for referencing each field and list traversing process at the time of modification, which was required when frame type data was held only by the links list while maintaining the arbitrariness and flexibility of information. it can. Then, CP reference processing for each field and change processing for the view
A command from U causes the CPU to process in the frame data structure memory that has a built-in high-speed associative data search mechanism.
While reducing the burden of (1), basic processing such as frame generation / erasure, slot, and reference or change of facet value can be performed at high speed. As a result, the processing efficiency of the entire knowledge base system can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the device of the present invention, and FIG.
FIG. 3 is a schematic configuration diagram of a frame data structure memory according to the present invention, FIGS. 3A and 3B are diagrams showing a data structure of a reset value, and FIG. (1) ... CPU, (2) ... system memory, (3) ...
... frame data structure memory, (4) ... linked list data storage memory (auxiliary storage means), (5) ... vector data storage memory (auxiliary storage means), (11) ... tag / information field separation circuit, ( 12) …… Judgment output control circuit (judgment means), (19) …… Structure memory control circuit, (2
4) ... hash address generation circuit (searcher generation means), (25) ... bulk memory (storage means), (32) ...
… Key match detection circuit, (33) …… Hash operation control circuit.

Claims (1)

[Claims] 1. A knowledge base processing apparatus having a frame-type knowledge base consisting of a frame, a slot, a facet, and a view, and a searcher generating means for generating a searcher from three arbitrary frames, a slot and a facet. , Storing means for storing the value data of the immediate data or pointer data corresponding to the searcher, determining means for determining whether the value data of the value data is immediate data or pointer data, and concretely corresponding to the pointer data of the value Knowledge-based processing device, comprising: auxiliary storage means for storing various data.