JPH0876733A - Image processing processor and image data processor or graphics computer using the same - Google Patents

Abstract

PURPOSE: To reduce hardware scale of a graphics computer and to reduce the cost by integrating a frame buffer with a main memory and graphics-processing it with a CPU. CONSTITUTION: The frame buffer 109 is arranged on the main memory 103, and this device is provided with a DMAC 101 reading out the pixel data from the frame buffer 109 for display, an FIFO receiving the pixel data and outputting them to a color palette, a memory 118 storing a procedure 120 that the CPU 100 plots for the frame buffer 109. In particular, the memory 118 storing the plotting procedure 120 incorporates a pattern table and a multilevel development plotting procedure 119 using a mask processing mask table. Thus, the frame buffer 109 is integrated with the main memory 103, and the graphics- processing by the CPU 100 is made possible and the hardware scale of the graphics computer is reduced, and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing processor for performing image processing such as drawing of display information (graphics) such as characters and figures, and displaying and outputting it, and an image data processing device or a graphics computer using the image processing processor. In particular, the present invention relates to an image data processing device that develops binary data such as characters and symbols into multivalued data at high speed.

[0002]

2. Description of the Related Art Character codes, graphic data, etc. are stored,
An image processor for drawing, displaying, or printing graphics based on these and an image data processing device or a graphics computer using the same store data (hereinafter referred to as pixel data) corresponding to pixels of a display screen. Therefore, a storage device called a frame buffer is used.

In order to draw graphics, the pixel position and pixel data are calculated from character codes and graphic data, and the pixel data is written into the frame buffer according to the pixel position. In order to display an image, there is a display process in which pixel data corresponding to pixels on a display screen are sequentially and repeatedly read from a frame buffer in synchronization with raster scanning of a display device.

As an example of a character drawing device that develops binary data such as characters into multivalued data and draws it in a frame buffer, it is described on pages 194 to 199 of the document "HD64410 ARTOP User's Manual" (first conventional technique). ) Has been.

This document shows that binary data composed of 16 × 16 bits represented by “0” and “1” as shown in FIG. 2 is expanded into multi-valued data. . The binary data is, for example, character data or symbol data (hereinafter, simply referred to as character data). These character data groups are stored in the character generator ROM (CGRO
The data is arranged in M) and stored, a character code is assigned to each character data, and the character data is accessed by this character code.

Therefore, the address on the memory of the character data corresponding to the character code can be obtained by numerical calculation according to the characteristics of the array. Character data whose correspondence with such a memory address is clear is as shown in FIG.
Originating at the point of row number 1 and column number 1, 16 pixels in X direction,
It can be considered as a coordinate system composed of 16 pixels in the Y direction.

Character data represented by these two values and addresses of the character data on the CGROM are converted into multivalued data (colored, multitone) and multivalued data which are converted into addresses on the frame buffer. Is.

As a second conventional technique, there is a technique for speeding up a drawing method including masking of binary data.
No. "Image processing device".

According to this, multi-valued expansion of binary data,
This is a technology related to multi-coloring for display, and the drawing technology discussed here has a slightly different background in how to handle color components.

That is, since the RGB color components are taken into consideration for display, one pixel is composed of three components, and therefore the amount of data to be handled is large compared to the basic technique of multi-valued expansion described above. It is a complicated process.

Here, by paying attention to one color component, the same idea as the multi-valued expansion performed in drawing can be obtained.

The feature of this technique is to use a RAM for storing multi-valued data corresponding to "1" of binary data, and further, expanded data for a plurality of pixels is stored in this RAM. . As a result, a plurality of pixels can be processed and the expansion processing can be speeded up.

In the multi-value expansion processing, the mask processing is performed on the data of the portion corresponding to "0" of the binary data with respect to the data of the RAM storing the multi-value data for the number of pixels to be subjected to the multi-value expansion. It is realized by.

[0014]

According to the first prior art, all pixel data of the character code are multivalued one by one, so that there is a problem that they cannot be processed at high speed.

Further, in the speed-up method in the second conventional technique,
The portion corresponding to "0" of the binary data is always subject to mask processing and is not converted to a specific color. Therefore, there is a problem that the drawing cannot be performed without the mask processing, and the drawing with the background of characters as shown in FIG. 5 cannot be performed.

Further, when attempting to realize this speed-up method in a system using a CPU, the following problems occur if there is a limit to the memory access when writing the result of simultaneously expanding a plurality of pixels to the frame buffer. appear.

That is, the CPU may place a limit on memory access in order to speed up internal processing.

The memory access limitation is "COMPUT
ER ARCHITECTURE A QUANTITATIVE APPROACH "94 ~ 9
As described on page 7, refer to memory access in byte units, and if the size is larger, for example, in word units or longword units, the address must be an even number or a multiple of 4. Must be satisfied.

That is, for example, when writing to the frame buffer in units of long words, it must satisfy that the write destination address is a multiple of 4.
In other cases, writing with a smaller size is allowed.

Therefore, for example, in a system in which one pixel is composed of 1 byte, that is, 8 bits, when the graphics computer writes in the frame buffer composed of the memory, the limitation of this memory access is taken into consideration. This means that you can only write in pixel units.

In order to efficiently perform memory access such as writing to the frame buffer, it is effective to access a plurality of pixels at a time in the maximum unit of the memory transfer size of the system, but it is possible to arbitrarily specify the frame buffer. If the physical address that is the result of converting the coordinate point of does not satisfy the memory access restriction, it cannot be used.

An object of the present invention is to provide an apparatus for executing multivalued expansion at high speed.

Another object of the present invention is to reduce the time required for the transparent processing and to perform the processing efficiently.

Another object of the present invention is to provide an apparatus which is compatible with both high-speed multi-value expansion processing and high-speed transparent processing.

Another object of the present invention is to efficiently write the result of image processing such as drawing into the frame buffer.
An object of the present invention is to provide a device that can access with a data transfer amount according to a memory access restriction.

[0026]

The first feature of the present invention is to:
An extraction unit that reads out binary data of a plurality of pixels, a multi-valued pattern storage unit that holds a multi-valued pattern having a plurality of multi-valued data for one pixel data, and a plurality of pixels read out by the extraction unit And a selection unit for selecting multivalued data corresponding to binary data from the multivalued pattern storage unit.

A second feature of the present invention is that an extraction unit that reads out binary data of a plurality of pixels, a mask pattern storage unit that holds a mask pattern for masking predetermined pixel data of the plurality of pixel data, and the extraction described above. A selection unit for selecting a predetermined mask pattern from the mask patterns for processing predetermined pixel data of binary data of a plurality of pixels read by the unit; and a mask processing unit based on the selected mask pattern. To have.

A third feature of the present invention is that it has a boundary determining section for determining a writing start position of pixel data from an address of pixel data to be written in the frame buffer, and a writing section for writing in the frame buffer according to the writing start position. It is in.

By combining these features, the following processing becomes possible.

The binary data extraction unit inputs the physical address of the memory converted from the coordinate point which is the position information for the binary coordinate, and reads the memory information having the address.

Next, data for a plurality of consecutive pixels is cut out and output from the read information in which one pixel is represented by 1 bit.

On the other hand, in the multi-valued pattern storage circuit, all combinations of a plurality of pixels of the cut out binary data are stored in advance by the multi-valued pattern generation circuit.

Further, the mask pattern storage section stores combinations of all mask patterns generated for a plurality of pixels of the cut out binary data.

Based on the contents of the multi-valued pattern storage unit and the mask pattern storage unit, a plurality of cut-out binary data, information regarding the presence / absence of mask processing, information regarding the frame buffer access restriction from the boundary determination unit, and the transfer count information To select one pattern each.

When the selected multi-valued pattern is drawn in the frame buffer, the drawing is performed after performing the masking process for a plurality of pixels at the same time using the selected mask pattern.

When extracting binary data in the first multi-valued expansion, the relationship between the write destination address of the frame buffer and the memory access restriction is determined.
Judgment is made by the boundary judgment circuit, and only the number of dots obtained by the result is read out.

This is because in order to efficiently write data to the memory of the frame buffer, if the write destination address of the frame buffer is subject to memory access restrictions and it is not possible to access with the selected multi-valued pattern size, it will be This is because it is necessary to return to the most adjacent address that can be accessed with the size of the value pattern and access.

Further, in this case, pixels that should not be originally drawn are generated. Against this, the mask result which is the output result of the mask pattern storage circuit selected by the information from the boundary judgment circuit is also generated. By performing mask processing using a pattern, it is possible to draw without changing the original data.

As a result, the expansion result for a plurality of pixels can be efficiently written in the frame buffer without considering the memory access limitation.

[0040]

With respect to the extracted binary data of a plurality of pixels, it is held in advance in the multi-valued pattern storage unit and the mask pattern storage unit according to the expansion condition to the multi-valued data and the position of the pixel data to be processed. By selecting multi-valued and mask pattern data, it is possible to simultaneously perform multi-valued expansion and drawing processing on a plurality of pixels in response to mask processing and memory access restriction. Therefore, it is possible to suppress the increase in the number of program steps and increase the processing speed.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A block diagram of a binary data drawing method according to the prior art is shown in FIG.

Among these components, the binary data physical address calculation unit 301 is related to the operation of multi-value expansion.
A binary data storage unit 302, a 1-pixel data extraction unit 303,
An I / O determination unit 304, multi-valued data 0 (305), and multi-valued data 1 (306). Further, the multi-valued data physical address calculation unit 307, the mask processing unit 308, the drawing unit 309, and the frame buffer 310 are related to the drawing including the transparent processing of the multi-valued expanded data.

The binary data physical address calculation unit 301
Binary coordinate position (Xs, Y given to the binary data drawing device
s) has a function of converting the physical address of the binary data storage unit 302, which is a memory.

Data in byte units is stored in the memory indicated by this address, which is the data amount of 8 pixels of binary data.

The obtained address is the one pixel data extraction unit 3
When the cutout of all the data input to 03 is completed, the address is updated to the address indicating the next pixel forming the character.

The binary data storage unit 302 is a memory for storing a binary data group, and receives a memory address which is an output result of the binary data physical address calculation unit 301 as an input,
The data corresponding to the address is extracted by the 1-pixel data extraction unit 3
Output to 03. Although the transfer unit of the memory differs depending on the system, when the data is transferred in a byte unit, data of 8 pixels of binary data expressing 1 pixel by 1 bit is output to the 1 pixel data extraction unit 303. .

The 1-pixel data extraction unit 303 cuts out the data of 8 pixels output from the binary data storage unit 302 for each pixel and outputs the data to the I / O determination unit 304. A shifter or the like is used to cut out one pixel. The cutout is performed once by one multi-valued expansion, and when the cutout of all the data sent from the binary data storage unit is completed,
Input new 8 pixel data.

The I / O determination unit 304 determines whether the binary data for one pixel output from the one-pixel data extraction unit 303 is 0 or 1. If the result of this determination is that the binary data is 0, the multivalued data 0
(305), and when it is 1, multi-valued data 1 (30
6) is selected and output to the mask processing unit 308.

The multi-valued data 0 (305) and the multi-valued data 1 (306) are areas for storing multi-valued data corresponding to binary data 0 and 1 preset in the binary data drawing device. .

The multi-valued data physical address calculation unit 307
Multivalued coordinate position (Xd, Yd) given to the multivalued expansion device
It has the function of calculating the corresponding physical address on the memory that constitutes the frame buffer, using as input. This address is updated to the next write destination address each time writing is performed. The obtained address is output to the mask processing unit 308 and the drawing unit 309.

The mask processing unit 308 has information regarding the presence / absence of mask processing, and the multi-valued data physical address calculation unit 30.
Address information of the write destination of the frame buffer from 7, data in the frame buffer having that address,
Multi-valued data 0 (305) and multi-valued data 1 (30
6) is input. For information regarding the presence or absence of mask processing,
It is given from a mode control register or the like existing outside the binary data drawing device.

Differences in drawing results depending on the presence or absence of mask processing will be described with reference to FIGS. FIG. 5 shows a drawing result when the transparent process by the mask process is not executed. As shown in this figure, the background of the character is filled with the color corresponding to "0" of the original binary bit map data. FIG. 6 shows a drawing result when the transparent process is executed. The data of the background frame buffer is displayed except for the portion corresponding to “1” of the original binary bit map data. Further, in the transparent processing, only the part corresponding to “0” of the original binary bitmap pattern is drawn, which is the opposite of the drawing result of FIG. It is possible to obtain a drawing result.

The drawing unit 309 has a function of writing the multi-valued data, which is the output result of the mask processing unit 308, into the memory having the address of the output result of the multi-valued data physical address calculation unit 307.

The frame buffer 310 is an area configured by a memory such as a RAM for storing drawing data.

FIG. 4 shows a processing procedure of the binary data drawing device by the components of FIG.

This process is carried out by following STEP 1 to STE.
P9, and one character is drawn by repeating the pixels constituting the character.

At STEP 1, the memory address corresponding to the given coordinate point is calculated. The coordinate point is a coordinate point which marks a character at the lower left corner point of the constituent pixel data, and is given from the outside of this multi-value expansion procedure. Further, the calculation for obtaining the address is carried out by the address corresponding to the origin of the coordinate system of the predefined binary data and the memory width in the X direction given to this coordinate system.
It is performed by the binary data physical address calculation unit 301.

In STEP 2, a process for extracting data for one pixel from the data having the address obtained in STEP 1 is performed. In binary data, one pixel is represented by 1 bit. Therefore, in this step, the process of extracting the pixel data for one pixel from the pixel data for a plurality of pixels accessed in bytes, words, long words, etc., which are memory access units using a normal bus, is performed. Is.

When all the pixels of the data have been extracted, the address obtained in STEP 1 is updated, and the data required for the next expansion is input from the binary data storage section. This processing is performed by the 1-pixel data extraction unit 303.

At STEP 3, the I / O of the one pixel data extracted at SETP 2 is determined. That is, when the extracted data is 0, the color data stored in the multivalued data 0 (305) is selected, and when the extracted data is 1, the color stored in the multivalued data 1 (306) is selected. Select data. This processing is performed by the I / O determination unit 304. S
In TEP4, the memory address of the frame buffer which is the drawing destination is calculated. This processing is performed by the multi-valued data physical address calculation unit 307.

At STEP 5, it is determined whether or not the mode is the transparent processing mode. Information about this mode is given from the outside of the binary data drawing device. If the transparent process is not performed, the process proceeds to STEP6. If the transparent process is performed, the process proceeds to STEP7.

STEP 6 is a sequence that occurs when the transparent process is not performed. Here, CL0 or CL1 selected in STEP3 is written in the memory having the address obtained in STEP5. As a result, the drawing for one pixel is completed, and the process proceeds to the end judgment of STEP9.

STEP 7 is a sequence that occurs when the transparent processing is performed. Here, the data of the address calculated in STEP 5 is read. That is, the data in the frame buffer of the writing destination is held.

STEP 8 is a sequence that occurs when the transparent processing is performed as in STEP 7. here,
A process of deciding the data to be drawn in the frame buffer is performed according to the selection result in STEP3. C according to STEP3
When L0 is selected, the data in the write destination frame buffer read in STEP 7 is used as the drawing data. When CL1 is selected in STEP3, CL1 is used as it is as drawing data.

STEP 9 is an end determination process of the multi-valued expansion means. Repetition of the process of STEP 2 transition is controlled until multi-valued development and drawing of all pixels forming a character are performed. After drawing all the pixels, the multi-valued expansion means ends.

Therefore, since all pixel data of the character code are multivalued one by one, they cannot be processed at high speed.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention in which the graphics computer is downsized and the time required for drawing is shortened.

The graphics computer of the present embodiment is composed of a microcomputer 126 having an operating frequency of 20 MHz for controlling drawing and display, a main memory 103 having a data width of 16 bits, which is composed of a DRAM and a frame buffer 109, and a ROM. And a second memory 108 having a data width of 16 bits for storing the application program 133 and the graphic data 132, and a plurality of pixel data continuously read from the main memory 103 are output in synchronization with the display. A raster buffer 104 that is temporarily stored, a color palette 105 that determines the brightness of the three primary colors of red, green, and blue from pixel data, and a display control signal conversion means that receives a display control signal 125 and converts it into a signal used by each means. 124 and stores large-capacity graphic data and application programs An external memory 134 consisting of such as CD-ROM unit or the hard disk device, a liquid crystal display 106 in the vertical direction 240 pixel synchronization timing in the horizontal direction 320 pixels conforming to the NTSC system television.

In FIG. 1, the color palette 105 and the liquid crystal display 106 are represented by the abbreviations CPLT and LCD, respectively. Below, these abbreviations are used. Here, LCD is used as the display of the graphics computer.
Although the 106 is used, the LCD 10 is used without changing the essence of the present invention.
Instead of 6, it is possible to use another raster scan type display such as a cathode ray tube.

The microcomputer 126 is composed of a CPU 100, which is an arithmetic means, and a ROM, and has a third data width of 16 bits for storing a drawing procedure and a display control procedure.
The data width is 1
A display control signal 125 for synchronizing the 6-bit fourth memory 128, the direct memory access controller 101 which reads pixel data from the frame buffer 109 in display and transfers it to the raster buffer 104, and the LCD 106 is generated. PWM signal group generation means 10
2, a second bus 127 which is an internal bus of the microcomputer 126, and a first bus 107 which is an external bus.
And a bus state controller 123 for connecting to each other and an oscillator 122 for generating a system clock 121. FIG.
Direct memory access controller 101 and bus state controller 123 are the abbreviations for each DMA
Notated as C and BSC. Below, these abbreviations are used.

Below, the part relating to the drawing of the present embodiment will be explained.

The CPU 100 executes the application program,
It is a calculation means for generating graphics data such as characters and figures in response to the request. The operation is to calculate the pixel position in the frame buffer 109 and its pixel data according to the drawing procedure stored in the third memory 118 based on the figure data such as characters and figures given by the application program, and the BSC 123 and the first section. The pixel data is written in the position of the pixel via the bus 107 of FIG.

The BSC 123 connects the second bus 127 and the first bus 107 and, at the same time, supplies the row address for directly connecting the main memory 103 composed of DRAM to the microcomputer 126 via the first bus 107. The column address is multiplexed and bus control signals such as the row address strobe and the column address strobe are generated.
Further, by comparing the row address in the previous access and the row address in the current access to the main memory 103, the access in the high speed page mode is automatically detected, and the access in the high speed page mode is automatically generated. . The BSC 123 automatically performs the high-speed page mode access to the main memory 103 or the frame buffer 109 without adding any logical means.

In graphics drawing processing, in most cases, one pixel is first accessed and then the adjacent pixel is accessed. For example, in filling a rectangular area, writing horizontal lines is repeated in the vertical direction. Further, generally, in the frame buffer, pixels in the horizontal direction are arranged at consecutive addresses, and in the present embodiment as well, the same arrangement is provided for speeding up display access. In such a case, the writing of the horizontal line is a writing to consecutive addresses. Therefore, the BSC 123 automatically executes the high-speed page mode access, so that the time required for drawing can be shortened.

The third memory 118 stores a drawing procedure 120 including a multivalued expansion procedure 119 as a drawing procedure. These procedures are sequentially loaded into the CPU 100 via the second bus 127 and executed by a call from the application program. The CPU 100 draws graphic elements and character elements in the frame buffer by executing these procedures. This procedure includes a plurality of independent procedures depending on the graphic element to be drawn.

These procedures were constructed as a graphics library that can be called from an application program written in a high-level language. As a high-level language, it corresponds to C language standardized by American National Standards Institute (ANSI).

In response to the DMA request signal 110 synchronized with the horizontal scanning of the LCD 106, the DMAC 101 continuously sends pixel data for one raster from the frame buffer 109 via the second bus 127, the BSC 123, and the first bus 107. The read data is transferred to the raster buffer 104. At this time, the DMAC 101 requests bus access to the BSC 123 by the bus arbitration signal 113 in order to use the second bus. In response, the BSC 123 sends the bus arbitration signal 1
The CPU 100 is stopped by 13, and the DMAC
The bus access right is given to 101. The DMAC 101, which has obtained the bus access right, continuously issues a read access for a predetermined pixel from the raster start address preset by the CPU 100.

Since a plurality of pixels can be obtained by one access, the number of read access is a value obtained by dividing the number of pixels of one raster by the number of pixels included in one word. For example, in this embodiment, the data width of the first bus is 16 bits, and the pixel data is 8 bits (simultaneous display color 256 colors).
The word contains two pixels. One raster (horizontal pixel row) of the frame buffer 109 and the LCD 106 is 32
Since the number of pixels is 0, it is accessed 160 times.

The BSC 123 can make access to a specific address space to DRAM according to the setting. In this embodiment, the frame buffer 10
In order to inexpensively configure the main memory 103 containing 9
RAM was used. Therefore, the main memory 103 is arranged in the specific address space, and the access to this space is D
Access to RAM was set in BSC123. This setting is performed by the CPU 10 according to the application program.
0 implements.

According to this setting, the BSC 123 makes the DMAC
The address issued by 101 is multiplexed into a row address and a column address, and a DRAM is provided for the first bus 107.
Perform a random read cycle of. Here, if the same row address as that of the preceding DRAM access is used, the high speed page cycle is executed. Furthermore, DM
Since it is an access by AC101, BSC123 is D
The MA write signal 111 is generated, and the pixel data read from the frame memory 109 is written in the raster buffer 104 during the read access cycle.

262144 words X1 used in this embodiment
The access time of a 6-bit DRAM is 80 nsec, the cycle time is 150 nsec, and the number of words in the same row address is 512. The system clock 121 is 20 MHz. Therefore, the BSC123 is set so that the access cycle of the DRAM is 4 clocks for random access issued from the row address and 2 clocks for high speed page access. This setting is performed by the CPU 100 according to the application program.

The first access for one raster is random access because the row address of the DRAM is often different from the previous access. The row address may change during the continuous access of one raster. This change is at most once due to the presence of 512 words in the same row address and the access of 160 words per raster. Also, the refresh cycle is at most once during the transfer of one raster. Therefore, the number of cycles required to access one raster is about 322 to 326 cycles, and the time is 16.1 microseconds to 16.3 microseconds. 16.2 on average
Microseconds.

The occupied time of the first bus per second is 1
It is a value obtained by multiplying the access time per raster by the number of rasters in one screen (the number of pixels in the vertical direction) and further by the vertical synchronizing frequency. The number of rasters on one screen is 240, and LCD
Since 106 is based on the NTSC system of television, the vertical synchronizing frequency is 59.9 Hz. From the above, the occupied time of the first bus per second is 233 msec. The bus occupancy rate is 23.3%.

Returning to FIG. 1 again, the frame buffer 109
The vertical scanning of will be described.

When the DMAC 101 transfers the pixel data for one raster from the frame buffer 109 to the raster buffer 104, the second interrupt signal indicates that the transfer is completed.
Notify the CPU 100 via 131. The CPU 100 executes the display control procedure 129 stored in the third memory as an interrupt process. The display control procedure 129 counts the number of notifications of transfer end of the DMAC 101, and DMs based on the number of notifications.
It is determined whether the raster to which the AC 101 has finished the transfer is the last raster in the vertical direction on the screen of the LCD 106.

DMAC10 if not the last raster
Reinitialize 1. The contents are the start address of the raster to be sent next, the number of words to be transferred corresponding to the pixel data for one raster, and the DMAC 101 waiting for the DMA request signal 110. Here, when the size of the frame buffer 109 and the size of the LCD 106 are equal, the source address of the DMAC 101 is incremented for each access, so it is not necessary to set the start address of the raster to be sent next as the source address. It has already been generated.

On the other hand, when the notification number indicates the last raster, the notification number is cleared, the start address of the first raster, the number of words to be transferred corresponding to the pixel data of one raster, and the DMAC 101 is DMA. Request signal 110
Put in a waiting state. The vertical scanning of the frame buffer 109 can be realized by the CPU 100 sequentially executing the above procedure. By realizing the vertical scanning by software in this way, it is possible to reduce the cost of the graphics computer.

The frame buffer 109 is replaced by the LCD 1
By making the screen wider than that of 06 and using the display control procedure 129 described above, smooth scroll processing is possible. It is generally known that smooth scroll processing can be realized by repeatedly moving the display area in the frame buffer little by little. Since the display control means 129 is a procedure for designating the start address of the raster, the smooth scroll processing is performed by changing these addresses little by little.

The pixel data for one raster transferred to the raster buffer 104 is read one by one by the pixel read signal 116, and the entry number 112 of the CPLT 105 is read.
become. The reading order is FIFO between words.
In order, the order is from the MSB side in the same word. The reading timing is synchronized with the horizontal scanning of the LCD 106. The entry number 112 is taken into the CPLT 105 by the pixel clock 117. Entry number 1 here
12 is 8 bits, and 256 colors from 0 to 255 can be designated. CPU10 according to the application program
0 presets the above 256 colors in the CPLT 105. The CPLT 105 converts the color designated by the entry number 112 into an analog RGB signal 115, and the LCD 1
Output to 06.

Next, the synchronization method of each unit will be described.

The display control signal generating means 102 receives the system clock 121 and outputs a horizontal synchronizing signal 213 for controlling the horizontal scanning or vertical scanning of the LCD 106, a horizontal display period signal 211, a vertical synchronizing signal 212 and a vertical display period signal 210. appear. The CPU 100 sets the cycle, phase and pulse width of these four PWM signals according to the application program. The horizontal synchronizing signal 213 is a signal indicating the end of one horizontal scanning of the LCD 106 and the start of the next horizontal scanning. The horizontal display period signal 211 is a signal indicating a display start position and a display end position in each horizontal scan of the LCD 106. The vertical synchronizing signal 212 is a signal indicating the end of one vertical scanning of the LCD 106 and the start of the next vertical scanning. The vertical display period signal 210 is a signal indicating a display start position and a display end position in each vertical scan of the LCD 106. The display area of the LCD 106 is determined by combining the horizontal display period indicated by the horizontal display period signal 211 and the vertical display period indicated by the vertical display period signal 210.

Further, the display control signal generating means 102 requests the CPU 100 for interrupt processing in synchronization with the vertical display period signal 210. The request for interrupt processing is at the start and end of the vertical display period. In this embodiment, interrupt processing is requested via the first interrupt signal 130. In response to this interrupt processing request, the CPU 100 causes the third memory 11
8 and the drawing procedure or display control procedure 129 is activated. As a result, L generated in drawing and display
The disturbance on the screen of the CD 106 is reduced. In particular,
In response to a request for interrupt processing at the end of the vertical display period, the display control procedure 129 executes the above-described display area changing processing. By doing this, LC is displayed during smooth scrolling.
Distortion such as a border does not occur on the screen of D106. Further, in response to a request for an interrupt process at the start of the vertical display period, a drawing process in which the vertical scanning speed is slower than the vertical scanning speed of the LCD 106 is activated. As a result, the unsightly display of an incomplete graphic in the middle of drawing on the screen of the LCD 106 does not occur. As such a drawing process, single-function procedure 1
There are polygon filling processing and rectangular area copying processing belonging to 20. Not only is the activation of these drawing processes synchronized with vertical scanning, but these drawing processes are scanned in the same direction as the vertical scanning direction of the LCD 106. By doing so, the vertical scanning of drawing does not overtake the vertical scanning of the LCD 106, and the vertical scanning of drawing is L.
The vertical scanning of the CD 106 was not overtaken.

Next, the conversion means 124 will be described. The conversion means 124 is means for supplying a signal related to display in a form suitable for each constituent means. This means includes a system clock 121, a horizontal sync signal 213, and a vertical sync signal 21.
2 and the horizontal display period signal 211 and the vertical display period signal 210
To transfer pixel data for one raster from the frame buffer 109 to the raster buffer 104.
A DMA request signal 110 requested to the AC 101,
The pixel read signal 116 indicating the timing of outputting the entry number 112 to the raster buffer 104, and the CP
A pixel clock 117 indicating the timing of fetching the entry number 112 and the timing of outputting RGB115 to the LT 105, and a synchronization signal 11 indicating the timing of vertical scanning and horizontal scanning for the LCD 106 by one signal line.
4 is generated. You may perform these conversions by the means to which the signal after conversion is input. In that case, the conversion means 124
Becomes useless.

An embodiment for shortening the execution time of a process involving multi-value expansion such as character drawing will be described below with reference to the drawings. Further, in the following description, one pixel of multi-valued data is represented by 8 bits, but the number of bits of one pixel is not particularly specified in the present invention. In addition to the drawing of characters, multi-valued expansion also occurs in a surface fill pattern and the like. In this embodiment, the description will be made with respect to characters, but the drawing is not limited to characters and the multi-valued expansion method of the present invention can be applied as long as the drawing involves multi-valued expansion.

FIG. 7 shows the functional blocks related to the multi-valued expansion procedure 119 in the drawing procedure 120 in the third memory 118 storing the multi-valued expansion drawing procedure of the present invention. The multi-value expansion procedure is one process in a series of drawing, and necessary data is given from the drawing procedure 120.

The binary coordinate position 601 will be expanded to 2
It is a memory that shows the coordinate position of the value data in the coordinate system,
It is composed of two data of X coordinate and Y coordinate.
From this data, the multilevel expansion procedure 119 calculates the memory address where the binary data is stored and reads the data.

The multi-valued coordinate position 602 is a memory indicating the coordinate position for drawing in the coordinate system of the multi-valued data of the frame buffer, and is composed of two data of X coordinate and Y coordinate. From this data, the multi-valued expansion procedure 119 calculates the memory address of the frame buffer for drawing the data after the multi-valued expansion, and uses it for mask processing and drawing processing.

The multilevel data 0 data 603 is a memory which stores multilevel data corresponding to binary data 0.
This data is defined before processing involving multi-value expansion of characters and the like. The multi-value expansion means 119 reads the color data corresponding to "0" of the binary data from here. Further, the color data stored in this area is changed by the drawing procedure 120 or directly from the CPU.

The data 604 of the multivalued data 1 is a memory which stores multivalued data corresponding to 1 of the binary data.
This data is defined before processing involving multi-value expansion of characters and the like. The multi-value expansion means 119 reads the color data corresponding to "1" of the binary data from here. Further, the color data stored in this area is changed by the drawing procedure 120 or directly from the CPU.

A mask processing presence / absence 605 is a memory for setting information as to whether or not the mask processing is performed on the result of multi-value expansion.

The transfer count 606 is a counter that represents the number of pixels forming a character from the components in the X and Y directions, and is initially set to X direction = 16 and Y direction = 16 when drawing a character. The number of transfers is updated every time drawing is performed by the number of pixels drawn by the multi-valued expansion procedure 119, and the value indicated by the number of transfers is the remaining number of transfers.
In the multi-value expansion procedure 119, after performing multi-value expansion in the X direction, Y
Perform multi-valued expansion of directions. As a result, the number of transfers is reduced by one in the Y direction each time the X direction changes from 16 to 0.

From the above information, the multivalued expansion procedure 119 is 2
This is a memory that stores a procedure for expanding the value data into multivalued data, performing a transparency process by masking if necessary, and drawing the expanded multivalued data in the frame buffer.

The basic idea of the multi-valued expansion procedure 119 is to prepare multi-valued data patterns consisting of all combinations of a plurality of pixels, and prepare a multi-valued data group which is conventionally performed for each pixel. This is to associate a plurality of pixels extracted from the above with a multi-valued data pattern. Further, a mask pattern, which is a combination of information on whether or not to perform the masking process for the plurality of pixels to be extracted, is prepared, and the extracted binary pixels, the address of the drawing destination frame buffer, the presence or absence of the masking process, By selecting a multi-valued pattern and a mask pattern from factors such as the number of transfers, it is possible to realize simultaneous multiple image processing while supporting mask processing and memory access restrictions.

Here, a method of coping with the memory access restriction by the mask processing will be described with reference to FIG. However, here, the memory access limit is that when accessing the memory in long words (4 bytes), the address must be a multiple of 4 words (2 bytes)
When accessing with, it must be a multiple of 2. It is assumed that there are no particular restrictions on access in byte units. Here, it is assumed that the access boundary in the long word and the arbitrarily designated write destination address of the frame buffer have an address which is a multiple of 4 + 1.

The operation to be executed here is to efficiently write the data for four pixels which have been multivalued into the memory,
By writing four pixels in a longword size to the frame buffer at the same time, the number of memory accesses is reduced and the system performance is improved. In order to perform simultaneous writing of 4 pixels while absorbing memory access restrictions,
The following processing is executed.

Data based on the binary coordinate position is output from the binary data storage unit to the binary data extraction unit. The binary data extraction unit extracts data for the number of pixels to be simultaneously processed from the sent data for a plurality of pixels (bits).
However, this extraction is adjusted depending on the relationship between the memory forming the frame buffer, the address resulting from the conversion of the multi-valued coordinate position into the physical address of the memory, and the number of times the multi-pixel simultaneous multi-valued expansion is performed. . First, regarding the relationship between the memory of the frame buffer and the converted physical address, extraction is performed corresponding to the effective number of data in the 4-byte data to be written in longword. In the case of the example in FIG. 8, among the positions where the data A, B, C, and D to be transferred in the longword are stored, the position corresponding to A is not the position where the drawing result is written, so the effective number of data is 3 In response to this result, the binary data extraction unit cuts out data for three pixels as right-justified 4-bit data. At this time, for the leftmost 1-bit data,
Appropriate data of 0 or 1 is embedded so as not to affect the subsequent processing. Next, regarding the number of times the multi-pixel simultaneous multi-value expansion is performed, whether the multi-value expansion for the binary data group is the first multi-value expansion, the multi-value expansion in the middle, or the last It is due to the multi-valued expansion of. In other words, is it the first transfer to write the data expanded by simultaneous processing to the frame buffer?
This is to cope with the fact that the position of the valid data differs depending on whether the transfer is an intermediate transfer or the final transfer. For the first transfer, the positions of valid data are consecutive 4
It is located right justified in the pixel. In the middle, all four pixels become valid data. Furthermore, the position is left-justified in the last transfer. In the extraction of the binary data in the initial transfer, only the binary pixel number corresponding to the effective pixel number of the frame buffer is right-justified as described in relation to the address limitation of the frame buffer. Since all the pixels transferred in the middle are valid pixels, the binary data after the first extraction is converted to 4
Extract for each pixel. In the final transfer, the remaining binary data that follows the data extracted during the transfer in the middle is left-justified and is extracted with 4 bits. In this case, appropriate data of 0 and 1 are embedded in the positions other than the valid data on the right side.

With such a binary data cutout method, the shift between the effective pixel position and the longword access boundary due to the memory access restriction is transferred by the first transfer and the final transfer binary data cutout method. Adjust and transfer in the middle without considering the limitation of memory access
Subsequent processing can be executed.

On the basis of the binary data thus extracted, the multi-value expansion corresponds to the table storing the combination of the multi-value data for four pixels by performing a table search. Multivalued data for four pixels is obtained. The table search is performed by considering the multi-valued data of four pixels as a numerical value and analyzing the correspondence with the table using the numerical value as an address. Separately from this, the extracted binary data, the type of address shift related to the address restriction, and the information about the previous transfer,
One corresponding data is obtained from the mask pattern table that stores the combination of the mask positions for four pixels. For this correspondence, for example, in the case of the first transfer in the figure, it is determined from the address shift that the data corresponding to the position of the frame buffer A is not the position to be originally written,
The position of C, which is the position to be masked, is determined from the extracted binary data, and a pattern in which 0 is embedded in all 8 bits of 1 byte corresponding to the position to be masked is selected. If it is selected not to perform the mask processing depending on the operation mode, it is not necessary to mask the position of C, so the position of A, which is a mask for absorbing the address shift, is masked. Select the pattern to be used. The logical product of the combination pattern of the multi-valued data for four pixels and the mask pattern obtained in this way, and the logical product of the data at the positions A to D of the frame buffer and the inverted value of the mask pattern, The write data is finally generated in the frame buffer by taking the logical sum of the logical product results.

Regarding the transfer in the middle, since the problem of the memory access restriction is solved by the first transfer, only the position to be masked when the mask processing is selected is focused and the mask pattern is selected. Further, regarding the last transfer, the same processing content is obtained except that the relationship of the position where the mask processing for absorbing the memory access restriction is performed is different from that of the first transfer.

In the case where binary data of, for example, 8 pixels is developed by such simultaneous processing of a plurality of pixels, the memory access restriction is not imposed in comparison with the conventional method which requires writing to the frame buffer 8 times. Even if it takes twice, the same processing can be performed by accessing three times.

FIG. 9 shows a functional block diagram of the multivalued expansion procedure 119. However, the binary data physical address calculation unit 301, the binary data storage unit 302, the multivalued data 0 (305), and the multivalued data 1 (3 that overlap with the basic configuration shown in FIG.
06), the multi-valued data physical address calculation unit 307, and the frame buffer 310 have exactly the same functions, and a description thereof will be omitted here.

The boundary judgment unit 806 has a function of judging the relationship with the memory access restriction from the address of the drawing position in the frame buffer output from the multivalued data physical address calculation unit 307.

The judgment is made on the multi-valued data physical address calculation unit 30.
The lower 2 bits of the drawing destination address of the frame buffer output from 7 are decoded to determine which of the states corresponds. The lower 2 bits of the drawing destination address are decoded because, in this example, the memory access is restricted because the address must be a multiple of 4 when transferring in longword (4 bytes). Is.

As the decoding result in this example, four states of states (1), (2), (3) and (4) shown in FIG. 10 appear.
Each state is as follows: State (1) Address is a multiple of 4 and memory access is not restricted State (2) Address is a multiple of 4 + 1 and memory access is restricted State (3) Address is a multiple of 4 +2 The case (4) where the address is a multiple of 4 +3 and the memory access is restricted is shown. In this embodiment, these states are set to bo
Called und 0, bound 1, bound 2, and bound 3. This information is stored in the plural pixel extraction unit 801, the pattern selection unit 802,
The processing is output to the address correction unit 807, and the processing corresponding to each bound is selected in each block.

The multi-pixel data extraction unit 801 uses the binary data for 8 pixels output from the binary data storage unit 302, the information from the boundary determination unit 806, and the transfer count 6
It has a function of extracting binary data to be subjected to multi-value expansion based on the information from 06. The extracted data is transferred to the pattern selection unit 802 as selection information for selecting the corresponding pattern from the multi-valued pattern storage unit 804 or the mask pattern selection unit 806. This selection information is 16 kinds of information having a value from 0 to F when performing the 4-pixel simultaneous processing.

FIG. 11 shows the internal configuration of the multiple pixel extraction unit 801.
Shown in

The X-direction binary data storage unit 3020 is a register for storing 16 pixels of binary data transferred from the binary data storage unit. In this embodiment, 16 objects are drawn.
The character data is composed of x16 dot pixels. Therefore, all the continuous data in the X direction are stored in this register.

The extraction register 3021 is an area for storing binary data for four pixels extracted from the pixel data in the X direction stored in the X direction binary data storage unit 3020.

The sequence control unit 3022 determines that the transfer count is 6
06 and the output information of the boundary determination unit 806, it has a function of managing the operation of the multiple pixel data extraction unit 801.

The operation of the sequence controller 801 is shown in FIG.

In STEP 1, of the information from the transfer count 606, according to the information on the transfer count in the X direction, when the transfer count is 16, the process branches to STEP 2 and subsequent steps,
Otherwise, the process branches to STEP 6 and subsequent steps. The transfer count 606 is information indicating the number of remaining pixels to be drawn, and the character data is composed of 16 pixels in the X direction. Therefore, this determination is to determine whether it is the first transfer in the X direction.

STEP 2 is executed when it is determined in STEP 1 that the transfer is the first transfer in the X direction. here,
From the calculation result of the binary data physical address calculation unit 301,
The binary data storage unit 30 stores the pixel data having this address.
The data is read from 2, and stored in the X-direction binary data storage unit 3020. By this transfer, 16-bit data corresponding to 16-pixel binary data is stored in the register.

In STEP 3, the boundary determination unit 806
The subsequent processing is selected from the information indicating the relationship with the memory access restriction, which is the output result of.

Each processing corresponding to the determination result in STEP 3 is performed.

When bound 0, the data for four pixels is transferred to the extraction register 3021 from the MSB side of the X-direction binary data storage unit 3020 which stores binary data.

In the case of bound 1, data of 3 pixels is transferred to the extraction register 3021 from the MSB side of the X-direction binary data storage unit 3020 which stores binary data.

In the case of bound 2, data of two pixels is transferred from the MSB side of the X-direction binary data storage unit 3020 storing binary data to the extraction register 3021.

In the case of bound 3, data of one pixel is transferred to the extraction register 3021 from the MSB side of the X-direction binary data storage unit 3020 which stores binary data.

Each pixel data transferred from the 1X direction binary data storage unit 3020 to the extraction register 3021 is input to the pattern selection unit as right-justified numerical values.
Therefore, the representation range of data digitized by each bound is 0 to 15 when bound 0, 0 to 7 when bound 1, 0 3 when bound 2, and 0 1 when bound 3.

STEP 5 prepares for the extraction of the next pixel.
This is a process of shifting out the data already transferred to the extraction register in the 16-bit register. Since the amount of extracted data is different depending on bound, the shift amount is 4 bit left shift for bound 0, 3 bit left shift for bound 1, 2 bit left shift for bound 2, and bound 3 for bound 3, respectively. It is a 1-bit left shift. When shifting, 0 is input from the LSB side.

STEP 6 is a sequence executed when the number of transfers in the X direction in STEP 1 is other than 16. S
In TEP6, it is determined whether or not the number of transfers in the X direction is larger than 3. Whether the transfer count is greater than 3 has the following meaning.

In the series of multi-valued expansion processing, the sequence of simultaneous 4-pixel processing is executed except for the first transfer. Therefore, when the remaining number of transfers is 3 or less, it indicates that the process is the final process in the X direction. That is, this determination is for the final processing in the X direction or for other processing. As a result of this determination, at the time of the final transfer, the process proceeds to STEP 7, and at other times, the pixel data for every four pixels is extracted as in the case of the bound 0 of STEP 4.

In STEP 7, the data for 4 pixels, that is, the 4-bit data is transferred from the MSB side of the 16-bit register storing the binary data to the extraction register.

STEP 7 is a sequence executed when it is determined in STEP 6 that the process is the final process in the X direction, and in this case as well, data of 4 pixels is extracted. Therefore, although data other than pixels is also extracted depending on bound, in this case, the operation of ignoring data other than pixels is performed by the function of the pattern selection unit 802.

At STEP 8, the termination of the entire character drawing process is determined from the number of transfers 606 in the Y direction.
If unprocessed data remains in the Y direction as a result of the determination, the process proceeds to STEP 9 for updating the binary data memory address for reading the next binary data in the X direction.

STEP 9 updates the address in the Y direction,
Prepare to read the next binary data in the X direction.

An operation example according to the above sequence is shown in FIG.
This is shown in FIGS. 14, 15 and 16.

FIG. 13 shows the X direction binary data storage unit 3020 and the extraction register 3 when the number of transfers = 16 and bound 0.
021 shows the state change. The data value input from the binary data storage unit 302 is "1000101011101000".
Is shown. The sequence control unit 3022 uses the transfer register information for the X direction and the bound information to extract the register 3 for extraction.
4-bit data is transferred to the 021 from the MSB side of the X-direction binary data storage unit 3020. After that, the data in the X-direction binary data storage unit 3020 is shifted to the left by 4 bits so that the data becomes "1010111010000000". In the figure, the hatched portion on the LSB side indicates “0” embedded by the left shift.

FIG. 14 shows the state change when the number of transfers = 16 and the bound is 2. Binary data storage unit 30
It is assumed that the data value input from 2 indicates “1000101011101000”. The sequence control unit 3022 right-justifies and transfers 2-bit data from the MSB side of the X-direction binary data storage unit 3020 to the extraction register 3021 based on the transfer count information and the bound information in the X direction. Therefore,
“0010” is set in the extraction register 3021.
Next, the sequence control unit controls the X-direction binary data storage unit 30.
By shifting 20 to the left by 2 bits, the data becomes "0010101110100000".

Number of transfers = 16 and bounds are 1, 3 respectively
14, the number of bits transferred to the extraction register 3021 and the number of shifts of the X-direction binary data storage unit 3020 after transfer are 1 bit and 3 as compared with the case of bound 2 in FIG.
The operation is similar except that it is a bit.

FIG. 15 shows the X-direction binary data storage unit 3020 and the extraction register 3 when 16 <the number of transfers <3 and bound.
021 shows the state change. The binary data storage unit 3020 in the X direction has been set to "1010111010" by extraction up to the present
000000 ”is stored. The sequence control unit 3022 sets the X-direction binary data storage unit 30 except when the transfer count = 16.
Extraction register 3021 for 20 data in units of 4 bits
Transfer to. Therefore, in this case, “1010” is transferred to the extraction register 3020 from the MSB side of the X-direction binary data storage unit 3020. After that, the X-direction binary data storage unit 3020 is shifted left by 4 bits and its value is "1110".
It becomes 10000000000 ”.

FIG. 16 shows X when the number of transfers is <3 and bound2.
Directional binary data storage unit 3020 and extraction register 302
1 shows the state change of 1. Only the two bits on the MSB side have meaning in the X-direction binary data storage unit 3020 as binary data, and the hatched portion on the LBS side is "0" embedded by the shift operation. Even in such a case, the sequence control unit 3022 transfers 4-bit data from the MSB side to the extraction register 3021. Therefore, the value stored in the extraction register 3021 is "0100".

The multi-valued pattern generator 803 has 1
Multi-valued data 0 (3
05) and multivalued data 1 (306) are combined for a plurality of pixels, all patterns are generated and output to the multivalued pattern storage unit 804. In the present embodiment, 16 patterns are generated because 4 pixels are simultaneously processed.

FIG. 17 shows the configuration of the multi-valued pattern generating section 803. As shown in FIG. 17, the created pattern data generation circuit 1001 calculates how many combinations there are and the combination data depending on the number of pixels to be simultaneously processed. In the case of the 4-pixel simultaneous processing as in the present embodiment, it is calculated that there are 16 combinations, and a bit pattern representing 0 to 15 is generated as the combination data. This information is selected as multi-valued data 0 (305) and multi-valued data 1 (306) as a bit selection signal,
The number of writes to the multi-valued pattern data buffer 1002 is controlled.

As the pixel selection signal 1003 output from the creation pattern generation unit, bit patterns which are combination data of a plurality of pixels are sequentially output. In the case of simultaneous processing of 4 pixels, "0000" expressing 0 is 1 from the MSB side at the beginning.
"000" that is output sequentially bit by bit and then represents 1
“1” is output at the end, and “1111” representing 15 is output. When this information output for each bit is 0, multi-valued data 0 is selected, and when it is 1, multi-valued data 1 is selected. To do.

The buffer control signal 1004 is the selected multi-valued data 0 (305) or multi-valued data 1 (306).
To control writing to a predetermined position of the multi-valued pattern data buffer 1002.

The multi-valued pattern data buffer stores the selected multi-valued data 0 (305) or multi-valued data 1 (306) by the number of pixels to be simultaneously processed.
It is a buffer for outputting to 04.

When the multi-valued pattern generation process is activated in synchronization with the re-writing of the multi-valued data 0 (305) and the multi-valued data 1 (306), a dedicated instruction for activation is recognized. You may have.

The multi-valued pattern storage section 804 has a function of storing, as the output result of the multi-valued pattern generation circuit 803, a combination pattern of multi-valued data for pixels to be simultaneously processed. FIG. 18 shows the contents stored in the multi-valued pattern storage unit 804. In this way, 16 types of tables CLT0 to 15 are created.

As shown in FIG. 19, the mask pattern storage unit 805 has a function of storing MST0 to MST15, which is a combination of all mask data corresponding to the number of pixels to be simultaneously processed. Therefore, in this embodiment, it is composed of 16 kinds of combination data like the multi-valued pattern.

Returning to FIG. 9 again, the description will be continued.

The pattern selection unit 802 uses the information output from the plural pixel data extraction unit 801, the boundary determination unit 706, and the presence / absence of mask processing 605 to determine the multi-valued pattern storage unit 80.
The multi-valued pattern stored in 4 and the mask pattern stored in the mask pattern storage unit 805 have a function of selecting one pattern corresponding to the input information. Here, the binary data for four pixels input from the multiple pixel data extraction unit 801 is treated as a 4-bit numerical value. Therefore, hexadecimal numbers 0 to F are treated as data.

A procedure for selecting required information in the multi-valued pattern storage unit and the mask pattern storage unit from the information input to the pattern selection unit 802 will be described with reference to FIGS.
1, shown in FIG. Hereinafter, the case without the mask processing will be described with reference to FIG. 20, and the case with the mask processing will be described later with reference to FIGS. 21 and 22.

First, FIG. 21 will be described.

The pattern selection starts with the determination of the presence / absence of mask processing. In SETP1 depending on the presence or absence of mask processing,
When there is no mask processing, the processing branches to SETP2, and when there is mask processing, the processing branches to SETP19 shown in FIG. Now,
In STEP 2 executed when the masking process is performed, a process of selecting a corresponding multi-valued pattern from the multi-valued pattern storage unit is executed. In this processing, binary data for a plurality of pixels output from the multi-pixel extraction unit is treated as a numerical value expressed in a binary number, and a multi-valued pattern corresponding to the numerical value is selected to select a corresponding multi-valued pattern. I do. Therefore, the value obtained by treating the binary data of a plurality of pixels as a numerical value is n
In this case, the selected multi-valued pattern is CLT (n).

The subsequent processing from STEP 3 is processing for selecting a mask pattern. First, depending on whether or not it is the first transfer of multi-valued expansion, if it is the first transfer, proceed to STEP 4, otherwise, SETP1.
Branch to 1.

The management of the transfer sequence such as the first transfer, the middle transfer, and the last transfer is determined based on the transfer count 606 input to the multi-value expansion procedure 119. In the multi-value expansion procedure 119, the number of times of transfer is stored by subtracting the number of pixels which is actually multi-value expanded each time. That is, in the multi-valued expansion procedure 119, the number of remaining multi-valued expanded pixels is managed, and the transfer sequence is divided into three sequences of the first transfer, the intermediate transfer, and the last transfer based on the number of pixels. , Multi-valued expansion is performed with the procedure corresponding to it. The determination of the transfer sequence is the first transfer when the number of transfers stored in the multi-valued expansion procedure 119 and the number of transfers 606 input in the multi-valued expansion procedure 119 match, and the transfer order is determined by the multi-valued expansion procedure 119. When the stored transfer count is equal to or less than the number of pixels to be processed at the same time, the last transfer is performed.
Transfers are in progress except the case.

As a result of the determination of the transfer sequence as described above, if it is the first transfer, the process of STEP 4 is executed.
STEP4 is input from the downstream determination unit 806,
This is to determine whether or not the type of the transfer destination address of the frame buffer with respect to the memory access restriction is bound 0. When the bound 0 is the first transfer, the MST 15 is selected from the mask storage unit in STEP 5. In other cases, STEP 6 boun
Whether it is d1 or not is determined, and if it is bound1, ST
Select MST7 from EP7. In other cases, SET8 determines whether it is bound2 or not. B
If it is sound 2, MST 3 is selected in STEP 9, otherwise MST 1 is selected in STEP 10, and the series of processes is ended.

If the result of the determination is STEP3, that is, if it is other than the first transfer, it is determined in STEP11 whether the transfer is in the middle. As a result of this determination, when it is determined that the transfer is in the middle, the MST 15 is selected regardless of the bound information. When the transfer is not in the middle, that is, when the transfer is the final transfer, the bound information is determined in STEPs 13, 14, and 16, respectively.
When d 1 is MST 14, when bound 2 is MST 12,
When bound 3, MST8 is selected. In particular, when the last transfer is bound 0, the number of remaining transfers is always 0. Therefore, the end is selected without executing the process.

FIG. 21 shows the pattern selection procedure when the mask processing is performed as a result of the determination of the presence or absence of the mask processing in STEP 1. STEP 19 shows the selection of the multi-valued pattern in the multi-valued pattern storage unit, which is the same determination method as the selection method of STEP 2 when the mask processing is not performed. Next, STEP 20 is a process corresponding to STEP 3 when there is no masking process, and is a process of determining whether or not the transfer is the beginning of the transfer sequence. If it is determined in STEP 20 that the transfer is the first transfer, the processing from STEP 21 onward is executed. STEP21
The subsequent process is a process corresponding to STEP 4 when there is no masking process, and is a process for determining the relationship with the memory access restriction from the boundary determination unit. When bound is 0, the MST corresponding to the number n in which the extracted binary data is a binary number
Select (n). When bound 1 is set, when the extracted binary data is treated as a numerical value, the bit having the weight of the cube of 2 is set to 0, the numerically converted number m is obtained, and the selected mask pattern is MST (m). . Also, when bound 2 is used, 3 of 2 when the extracted binary data is treated as a numerical value
The bit having the weight of the power of 2 and the bit having the weight of the power of 2 are set to 0, the numerically converted number m is obtained again, and the selected mask pattern is MST (m). Also, when bound3, the 2 of 3 when the extracted binary data is treated as a numerical value
The mask pattern to be selected is MST by setting the bit having the weight of the power of 2 and the bit having the weight of the power of 2 and the bit having the weight of the power of 2 to 0, and recalculating the numerical value m.
(M).

FIG. 22 shows the pattern selection procedure when the execution sequence is determined in STEP 20 as a result of intermediate transfer and final transfer. STEP 31 is a determination as to whether the transfer is in the middle. As a result of this determination, if the transfer is in the middle, the process goes to STEP 32, otherwise, the process goes to STEP 3.
Move to 3.

STEP 32 shows the procedure for selecting a mask pattern in the case of intermediate transfer, and selects MST (n) corresponding to the number n in which the extracted binary data is a numerical value.

When the transfer sequence is the last transfer, it is determined from the information from the boundary determination unit which type corresponds to, as in STEP 13 and subsequent steps in the case where no mask processing is performed, and for each type, Select a mask pattern. Steps 35 and 36 are the procedure for determining the mask pattern in the case of bound 1, and the bit having the weight of 2 3 and the bit having the weight of 2 2 when the extracted binary data is treated as a numerical value. Bits having a weight of 2 squared are set to 0, and the numerically converted number m is obtained, and MST (m) is obtained as the mask pattern to be selected. STE
P38 and 39 are the procedure for determining the mask pattern at the time of bound 2, and when the extracted binary data is treated as a numerical value, the bit having the weight of 2 3 and the bit having the weight of 2 2 are set. The number m which is digitized again is obtained, and the mask pattern to be selected is MST (m). STEP4
0 and 41 are the mask pattern determination procedures at the time of bound 2, which are 2 when the extracted binary data is treated as a numerical value.
The bit m having the weight of the third power of 0 is set to 0 to obtain a new numerical value m, and MST (m) is calculated as the selected mask pattern. Each pattern corresponding to all cases is selected by the selection procedure of the multivalued pattern and the mask pattern as described above.

Further, the multi-valued pattern selection unit stores the number of transfers 606 input to the multi-valued expansion procedure 119 for managing the transfer sequence, and transfers the stored number of pixels each time the multi-valued expansion is performed. Subtract from the number of times. By this processing, information that is one element of pattern selection, that is, the initial transfer, the intermediate transfer, or the final transfer is generated.

When the memory access restriction is imposed, the address modification unit 807 modifies the address data to the nearest adjacent address which satisfies the memory access restriction, and outputs it to the multiple pixel mask processing unit 808. Further, the correction of the address is realized by clearing the lower 2 bits of the frame buffer physical address to 0.

The multiple pixel mask processing unit 808 has a function of writing multivalued data in the frame buffer in units of multiple pixels. This writing is performed on the data after the following logical operation is performed between the data corresponding to the writing position of the frame buffer, the selected multi-valued pattern, and the selected mask pattern. That is, as shown in FIG. 23, the logical product of the multi-valued pattern and the mask pattern, the logical product of the inversion value of the mask pattern and the frame buffer data, and the logical sum of the above two data are used to obtain the mask position of the mask pattern. At the 0 position,
The data of the corresponding frame buffer is embedded. However, when the MST15 is selected as the mask pattern, the write operation can be performed without considering the data in the frame buffer, and thus the selected multi-valued pattern is directly framed without performing such a logical operation. Draw in the buffer.

As described above, according to this embodiment,
It is possible to perform multi-value development processing and mask processing for multiple pixels at the same time off-line without performing multi-value development, mask processing, and drawing processing on a pixel-by-pixel basis, and to handle multiple pixels simultaneously while absorbing memory access restrictions. Will be able to. Therefore, the drawing time is about 1 / simultaneous processing pixel.
Therefore, the processing time can be significantly reduced.

Next, an embodiment in which the method for speeding up multivalued expansion in the above embodiment is applied to the drawing procedure 120 will be described.

FIG. 24 shows a processing flow when the CPU performs the multi-value expansion / drawing processing. The procedure for drawing this character exists as one stored content of the drawing procedure 120 in the third memory 118.

Generally, in many cases, a high-level language is used as an interface with a programmer when executing processing such as character drawing as an application program. Particularly in the C language, processing is structured by defining functions as one function. In this embodiment as well, a series of procedures for drawing characters is treated as one function. Generally, character data is stored in a ROM such as a character generator in the form of several pixels × several pixels per character, but here it is assumed to be stored in the form of 16 × 16 pixels.

If the character drawing procedure is expressed in the form of a function, T
COPY (Xs, Ys, dx, dy, Xd, Yd) 16
00 is useful. Here, TCOPY means performing copy processing for converting binary data to multivalued data, Xs and Ys are source coordinates of binary data, dx is the number of pixels to be transferred in the X direction, and dy represents the number of pixels to be transferred in the Y direction, and Xd and Yd represent coordinates of the transfer destination of other data after multi-value expansion. In this embodiment, dx = 16 and dy =
Assuming 16 pixels, the number of pixels actually transferred is 16 x 1
The following description will proceed with 6 pixels, that is, 256 pixels.

The number of transfers in the Y direction is stored in the storage 1601 as dy.
Means to store the value of. This value is used for the end determination 1608 of the character drawing process. The number of transfers in the X direction storage 1602 stores the value of dx, which is transferred to the multi-valued expansion procedure 119 and used for determining the transfer sequence. Transfer the coordinate position (Xs, Ys) of the binary data to the multi-value expansion procedure 16
Reference numeral 03 indicates that the coordinates of the lower left corner of the binary data indicated by the rectangular area that is the transfer source is transferred to the multi-value expansion procedure 119. Further, the coordinate position (Xd, Yd) of the multivalued data is transferred to the multivalued expansion procedure 160, and the coordinate of the lower left corner corresponding to the transfer destination of the frame buffer as the transfer source is transferred to the multivalued expansion procedure. . The multi-valued expansion procedure that receives each coordinate position converts each coordinate position into an address on the memory and uses it.

Transfer the number of transfers in the X direction to the multivalued expansion procedure 1
Reference numeral 605 is used by the multi-valued expansion procedure for determining the transfer sequence. The multi-value expansion procedure subtracts data corresponding to the number of pixels for which multi-value expansion and drawing have been performed based on the information on the number of times the transfer has been performed. Determine if it is in sequence. Further, this value is used as information on the determination standard of the transfer end determination 1606 in the X direction. If the result of this determination in the X direction is that it has not yet ended, the multivalued expansion procedure 119 is repeated again.
This repetition is a case in which the binary data shown in FIG. 2 is multivalued expanded, and when the 4-pixel simultaneous processing of this embodiment is executed,
If the memory access restriction is not applied, it is repeated 4 times, and even if it is applied, it is repeated 5 times. On the other hand, when it is determined that the X-direction transfer is completed, Y
1607 is executed by subtracting 1 from the number of transfers in the direction. And
Until the transfer count in the Y direction becomes 0, the transfer count in the X direction is repeatedly executed from the transfer 1605 to the multilevel expansion procedure.

In this series of processing, when the binary data as shown in FIG. 2 is multivalued and drawn in the frame buffer, the number of memory accesses to the frame buffer does not depend on the memory access limit, and the mask processing is performed. X direction 4 if none
16 times in the Y direction, that is, a total of 64 memory accesses. This value is 25 in the multi-valued expansion method of the prior art.
Six times.

In the present embodiment, the number of memory accesses when the mask process is executed is 8 times in the X direction and 16 times in the Y direction, which is 128 times in total. (Since the memory access for reading the data in the frame buffer for the mask processing is included, the number of times of access in the X direction is double that when there is no mask processing.) On the other hand, the conventional technique requires 512 times of memory access.

[0177]

As described above, according to the present embodiment, the CPU can easily perform the multi-value expansion of a plurality of pixels simultaneously. Further, since the multi-valued pattern data is arranged in the memory, the multi-valued expansion processing can be executed off-line and a plurality of dots can be handled at the same time. Therefore, even if the multi-valued expansion / drawing process is executed by the CPU, the performance is not deteriorated.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration example of a graphics computer.

FIG. 2 is an example diagram of binary data.

FIG. 3 is a functional block diagram of a conventional multilevel expansion device.

FIG. 4 shows an operation procedure of a conventional multi-valued expansion device.

FIG. 5 is a drawing result without transparency processing.

FIG. 6 is a drawing result with transparency processing.

FIG. 7 is a diagram showing a configuration example of a drawing procedure including a multi-value expansion procedure.

FIG. 8 is a conceptual diagram of avoiding memory access restriction by mask processing.

FIG. 9 is a diagram showing a configuration example of a multi-valued expansion device.

FIG. 10 is an explanation of the operation of the boundary determination unit.

FIG. 11 is an internal configuration of a multiple pixel extraction unit.

FIG. 12 shows an operation procedure of a multiple pixel extraction unit.

FIG. 13 is an example of extracting a plurality of pixels.

FIG. 14 is an example of extracting a plurality of pixels.

FIG. 15 shows an example of extracting a plurality of pixels.

FIG. 16 is an example of extracting a plurality of pixels.

FIG. 17 is a configuration example of a multi-valued pattern generation unit.

FIG. 18 is a configuration diagram of a multi-valued pattern storage unit.

FIG. 19 is a configuration example of a mask pattern storage unit.

FIG. 20 is a pattern determination procedure.

FIG. 21 is a pattern determination procedure.

FIG. 22 is a pattern determination procedure.

FIG. 23 is a configuration example of a multi-pixel mask processing unit.

FIG. 24 is a flowchart of multivalued rendering processing by the CPU.

[Explanation of symbols]

100 ... CPU, 101 ... DMAC, 102 ... Display control signal generating means, 103 ... Main memory, 104 ... Raster buffer, 105 ... Color palette, or CPLT, 106
... LCD, 107 ... First bus, 108 ... Second memory, 109 ... Frame buffer, or FB, 110
... DMA request signal, 111 ... DMA write signal, 112
Entry number, 113 ... Bus arbitration signal, 114 ... Synchronous signal, 115 ... Three primary color signals, or RGB signal, 116
... Pixel read signal, 117 ... Pixel clock, 118 ... Third memory, 119 ... Multi-valued development procedure, 120 ... Single function procedure of drawing, 121 ... System clock, 122 ... Oscillator, 123 ... Bus state control means, or BSC ,
Reference numeral 124 ... Conversion means, 125 ... Display control signal, 126 ... Microcomputer, 127 ... Second bus, 128 ... Fourth memory, 129 ... Display control procedure, 130 ... First interrupt signal, 131 ... Second interrupt Signal, 132 ... Graphic data, 133 ... Application program, 134 ... External memory, 200 ... First PWM timer, 201 ... Second PW
M timer, 202 ... Third PWM timer, 203 ... Fourth
PWM timer, 204 ... 1/8 minute cycle, 205 ...
Pixel clock generating means, 210 ... Vertical display period signal, 2
11 ... Horizontal display period signal, 212 ... Vertical synchronization signal, 21
3 ... Horizontal sync signal, 301 ... Binary data physical address calculation unit, 302 ... Binary data storage unit, 303 ... Single pixel data extraction unit, 304 ... I / O determination unit, 305 ... Multi-valued data 0, 306 ... Multi Value data 1, 307 ... Multi-valued data physical address calculation unit, 308 ... Mask processing unit, 309 ... Drawing unit, 310 ... Frame buffer, 601 ... Binary coordinate position, 602 ... Multi-valued coordinate position, 603 ... Multi-valued data 0 Data, 604 ... Data of multi-valued data 1, 605 ... Information regarding presence / absence of mask processing, 606 ... Information regarding number of transfers, 801 ... Multiple pixel data extraction unit, 802 ... Pattern selection unit, 803 ... Multi-valued pattern generation unit, 804 ... Multi-valued pattern storage unit, 805 ... Mask pattern storage unit, 806 ...
Boundary determination unit, 807 ... Address correction unit, 808 ...
Multiple pixel mask processing unit, 1001 ... Creation pattern data generation unit, 1002 ... Multi-valued pattern data buffer, 10
03 ... Pixel selection signal, 1004 ... Buffer control signal, 3
020 ... X-direction binary data storage unit, 3021 ... Extraction register, 3022 ... Sequence control unit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location G09G 5/36 520 N 9377-5H H04N 1/40 1/46 H04N 1/46 C (72) Invention Akihiro Katsura 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory, Hitachi Ltd.

Claims (9)

[Claims] 1. An extraction unit for reading out binary data of a plurality of pixels, a multi-valued pattern storage unit for holding a multi-valued pattern having a plurality of multi-valued data for one pixel data, and a read-out by the extraction unit. An image processing processor, comprising: a selection unit that selects multi-valued data corresponding to the binary data of a plurality of pixels that have been selected from the multi-valued pattern storage unit. 2. A boundary determination section for determining a writing start position of pixel data from an address of pixel data to be written in the frame buffer, and a writing section for writing to the frame buffer according to the writing start position. And image processing processor. 3. An extraction unit for reading binary data of a plurality of pixels, a mask pattern storage unit for holding a mask pattern for masking predetermined pixel data of the plurality of pixel data, and a plurality of units read by the extraction unit. A selection unit for selecting a predetermined mask pattern from the mask patterns for processing predetermined pixel data of binary data of pixels;
An image processing processor comprising: a mask processing unit based on the selected mask pattern. 4. A boundary determination section for determining a writing start position of pixel data from an address of pixel data to be written in the frame buffer, and a writing section for writing to the frame buffer according to the writing start position. And image processing processor. 5. An image processing processor, comprising: a boundary determination section for determining a writing start position of pixel data from an address of pixel data to be written in a frame buffer, and a writing section for writing in a frame buffer according to the writing start position. . 6. A memory unit for holding binary pixel data, an extraction unit for reading out binary data of a plurality of pixels, and a multi-valued pattern holding multi-valued pattern for one pixel data. A value pattern storage unit, a selection unit for selecting multivalued data corresponding to binary data of a plurality of pixels read by the extraction unit from the multivalued pattern storage unit, and the processed image data in the memory. A graphic computer comprising: an image processor having a writing unit for writing; and an output display unit for outputting and displaying pixel data from the memory under the control of the image processor. 7. The image processing processor according to claim 6, further comprising a boundary determination unit that determines a write start position of pixel data from an address of pixel data to be written in the memory unit, A graphic computer characterized in that a selection unit is controlled by a computer. 8. A memory unit for holding binary pixel data, an extraction unit for reading out binary data of a plurality of pixels, and a mask pattern storage for holding a mask pattern for masking predetermined pixel data of the plurality of pixel data. A selection unit for selecting a predetermined mask pattern from the mask patterns for processing predetermined pixel data of binary data of a plurality of pixels read by the extraction unit, and based on the selected mask pattern An image processing processor having a mask processing section, a writing section for writing the processed image data in the memory, and an output display section for outputting and displaying pixel data from the memory under the control of the image processing processor. A graphic computer characterized by that. 9. The image processing processor according to claim 8, further comprising: a boundary determination unit that determines a writing start position of pixel data from an address of the pixel data to be written in the memory unit, and the image processing processor responds to the result of the boundary determination unit. A graphic computer characterized in that a selection unit is controlled by a computer.