JPH087672B2 - Subtraction cell - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a subtraction cell, and more particularly to an optimum subtraction cell to be constructed using CMOS (complementary insulated gate field effect) transistors.

PRIOR ART The most common method of performing a binary subtraction (AB) is to invert each bit of the subtraction (B) and add it to the subtracted number (A) with a binary adder, Moreover, the carry input for the least significant bit is set to "1" and input to obtain the subtraction result. At this time, if N-bit subtraction is performed, the highest-order N-th bit arithmetic cell has a different circuit configuration from the others due to the code processing.
The N-1 operation cells at the bit can be configured by the same unit circuit. At this time, a circuit which receives the subtraction (B) and inverts the same to form the same unit circuit is also taken into the unit circuit, and this is called a "subtraction cell". Specifically, it is a circuit having a configuration in which an inverter is added immediately before the B input of the full adder. FIG. 3 shows a circuit in which this subtraction cell is composed of a conventional logic circuit. Subtracted signal A
And a subtraction signal B and a borrow input signal C _i are input, and a difference output signal D and a borrow output signal C _o are output.
1 and 2 are NOR gates, 3 and 4 are AND-NOR composite gates, and 5 to 7 are N
An AND gate 8 is an inverter, which is composed of all known CMOS gates. NOR gate 1 and compound gate 3, N
EX by combining OR gate 2 and compound gate 4
It has the function of an OR (exclusive OR) gate. Therefore, the difference output signal D and the borrow output signal C _o are respectively expressed by the following equations.

D = AC _i C _o = A + C _i (A) Problems that the invention may solve Now, the subtraction time when the input signals A, B and C _i are synchronously input to the subtraction cell of FIG. The output signal D is 8,1,3,2,
Gate 5 because it is obtained after propagating through the gate of 5 stages of 4
The delay time is equal to the number of stages, and the borrow output signal C _o is
Since it passes through the gates of 3, 6 and 7, the delay time is 5 gates.

The present invention is intended to provide an all-subtraction cell that is optimal for constructing a faster subtractor and divider by significantly reducing the operation time of the conventional subtraction cell.

Means for Solving the Problems The present invention speeds up the subtraction cell by using a novel CMOS composite gate.

That is, the present invention has the first, second, third, fourth, and fifth inputs, where the first, second, and third inputs are both high logic levels in the first case or the first case. When at least one of the second case in which the first, fourth and fifth inputs are both high logic levels, the output becomes a low logic level, and the first, second and third inputs are all low logic level. In the case of 3 or at least one of the fourth, where the first, fourth, and fifth inputs are all low logic levels, the output becomes a high logic level, and the inputs other than the above first to fourth cases In the case of the condition, the output has the first and second logic gates which are in the high impedance state, and the sixth and seventh inputs. When both the sixth and seventh inputs are the high logic level of the fifth, When the output is at the low logic level and the sixth and seventh inputs are both at the low logic level sixth, the output is at the high logic level,
The output has a third logic gate whose output is in a high impedance state under input conditions other than the sixth case and the eighth, ninth, and tenth inputs, and the eighth and ninth inputs are both high logic. In the case of the seventh level or at least one of the cases where the eighth and tenth inputs are both high logic level, the output becomes the low logic level, and the eighth and ninth inputs are both low. In the ninth case of the logic level or in the case of at least one of the tenth cases where the eighth and tenth inputs are both the low logic level, the output becomes the high logic level, and the outputs other than the seventh to tenth cases. A fourth logic gate whose output is in a high impedance state under the input condition is provided, and the subtracted signal is supplied to the second input of the first logic gate and the second input of the second logic gate. And an inverted signal of the subtracted signal is input to the fifth input of the first logic gate and the second input of the second logic gate. Input to the fourth input of the logic gate, the sixth input of the third logic gate, and the tenth input of the fourth logic gate, and the subtraction signal is input to the third input of the first logic gate. Input and the fifth of the second logic gates
Input and the seventh input of the third logic gate and the fourth input
Input to the ninth input of the logic gate, and the inverted signal of the subtraction signal is input to the fourth input of the first logic gate and the third input of the second logic gate. An input signal is input to the first input of the first logic gate, and an inverted signal of the borrow input signal is input to the first input of the second logic gate and the eighth input of the fourth logic gate. Input to, and connect the outputs of the first and second logic gates in common to obtain a differential output signal, and connect the outputs of the third and fourth logic gates in common to obtain a borrow output signal. It is characterized by being configured.

Effect According to the present invention, the subtraction speed is much wider than the conventional one.
A subtraction cell with a CMOS transistor configuration can be obtained, and CM
It is ideal for constructing OS dividers, multi-input subtractors, etc.

Example An example of the present invention is shown in FIG.

Input subtracted signal A, subtracted signal B, borrow input signal C _i ,
It is a subtraction cell of a CMOS transistor configuration that outputs a difference output signal D and a borrow output signal C _o . Logic gates 1 and 2 have CMOS transistor configurations, and both have the same function. The logic gate 1 (also 2) inputs five input signals a to e and outputs f = 0 when a = b = c = 1 (high logic level) or a = d = e = 1. (Low logic level)
When a = b = c = 0 or a = d = e = 0, the output f = 1, and under the input conditions other than the above, the output f is in the high impedance state. Reference numeral 3 denotes a 2-input (input signal g, h) logic gate, which has an output k = 0 when g = h = 1 and an output k = when g = h = 0.
The output k is in the high impedance state under the other input conditions.

Reference numeral 4 is a 3-input (input signal l, m, n) logic gate. When l = m = 1 or l = n = 1, the output k = 0 and l = m = 0 or l = When m = 0, the output k =
The output k is in the high impedance state under the other input conditions. Reference numerals 5, 6 and 7 are publicly known CMOS inverters.

10-14,20-24,30,31,40-42 are P-channel transistors, 15-19,25-29,32,33,43-45 are N-channel transistors, both transistors are both , The source is shown with an arrow. The outputs of the logic gates 1 and 2 are commonly connected to obtain the difference output signal D at the connection point f, and the outputs of the logic gates 3 and 4 are commonly connected to obtain the borrow output signal C _o at the connection point k.

The output of the logic gates 1, 2 and the difference output signal D for the input signals A, B, C _i are shown in the truth table of Table 1, and the logic gates 3, 4
And the borrow output signal C _o are shown in the truth table of Table 2.

As an example, when A = 0, B = 0, C _i = 0, the P-channel transistors 10, 11, 14 are turned on at the same time, the output of the logic gate 1 is 1, and the logic gate 2 has a high output impedance. Then, the differential output signal D becomes 1, the N-channel transistors 43 and 45 are simultaneously turned on, the output of the logic gate 4 becomes 0, the logic gate 3 becomes a high output impedance, and the borrow output signal C _o becomes It becomes 0.

From the truth table of Tables 1 and 2, it can be seen that D and C _o are expressed by the following equations and operate as subtraction cells.

D = AC _i C _o = A + BC _i + C _i A Next, the subtraction time of the subtraction cell of FIG. 1 is estimated. If the input signals A, B, C _i are input at the same time, the inverters 5, 6,
In step 7, each ,, ▲ ▼ is obtained simultaneously, and A, B, C
_Since the six signals _i ,,, ▲ ▼ are input to the logic gates 1 to 4, the difference output signal D is a delay time of two gates of one inverter and one logic gate (1 or 2). Similarly, the borrow output signal C _o can also be obtained with the delay time of one stage of inverter and one stage of logic gate (3 or 4) and two stages of gate.

Accordingly, the subtraction time subtraction cell according to the present invention, as compared with the conventional subtraction cells (FIG. 3), the difference output signal D, borrow output signal C _o together, will have been reduced by a factor of approximately 2.5 minutes .

The internal structure of the logic gates 1 to 4 is not limited to that shown in FIG. 1, and any structure may be used as long as it is a compound gate having an anti-function. For example, in the case of the logic gate 1, if C _i is input at substantially the same timing as A and B, the configuration as shown in FIG. 2 is faster. This is the P-channel, N-channel, transistor 1 in FIG.
4 and 15 are connected to the power supply (V _DD ) and the ground side, respectively, and the numbers and symbols are completely corresponding to those in Fig. 1. This is because the signal C _i , A, B arrives one stage earlier than the inverter, so that it comes later by bringing the transistor to which C _i , A, B is input to the fixed potential point side. Transistor input to, 11,1
The load capacity of 3,16,18 is minimized to reduce the propagation delay time.

As described above, according to the present invention, it is possible to obtain a subtraction cell having a CMOS transistor configuration, which has a subtraction speed about 2.5 times that of a conventional circuit. It is optimal for constructing vessels and the like, and its effect is extremely large.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a specific circuit configuration diagram of a subtraction cell according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing another embodiment of the logic gate 1 in FIG. FIG. 3 is a circuit configuration diagram of a conventional subtraction cell. 1,2,3,4 …… Logic gate, 5,6,7 …… Inverter, A ……
Minuend signal, B ...... subtraction signal, C _i ...... borrow input signal,
C _o …… borrow output signal, a to e …… input signal, f, k ……
Output, g, h, l, m, n ... Input signal.

Claims (1)

[Claims] 1. A first case or a first circuit having first, second, third, fourth and fifth inputs, wherein the first, second and third inputs are both high logic levels. , The fourth and fifth inputs are both at a high logic level in the second case, and the output is at a low logic level, and the first, second and third inputs are at a low logic level. Or the above first, fourth, fifth
Output is at a high logic level when at least one of the fourth inputs is at a low logic level.
When the input condition is other than the case, the output has the first and second logic gates which are in a high impedance state and the sixth and seventh inputs, and both the sixth and seventh inputs have the high logic level. In the fifth case, the output becomes a low logic level, and the sixth,
When the seventh input is a low logic level in the sixth case, the output becomes a high logic level, and when the input condition is other than the fifth and sixth cases, the output is in a high impedance state. An eighth, a ninth and a tenth inputs, wherein the eighth and ninth inputs are both at a high logic level in the seventh case, or the eighth and tenth inputs are both a high logic level at the eighth level. In at least one of the cases, the output becomes a low logic level and the eighth and ninth inputs are both at a low logic level in the ninth case, or the eighth and tenth inputs are both at a low logic level in the tenth case. The output has a high logic level in at least one of the cases, and the output has a fourth logic gate in which the output has a high impedance state under the input conditions other than the seventh to tenth cases. The second input of the first logic gate and the second logic gate Input the second input of
The inverted signal of the subtracted signal is supplied to the fifth input of the first logic gate, the fourth input of the second logic gate, the sixth input of the third logic gate, and the fourth logic. The 10th input of the gate and the subtraction signal are input to the third input of the first logic gate, the fifth input of the second logic gate, and the seventh input of the third logic gate. And the ninth input of the fourth logic gate, and the inverted signal of the subtraction signal is input to the fourth input of the first logic gate and the second input of the second logic gate.
And a borrow input signal to the first input of the first logic gate, and an inverted signal of the borrow input signal to the first input of the second logic gate. And the eighth input of the fourth logic gate, the outputs of the first and second logic gates are commonly connected to obtain a differential output signal, and the third and fourth logic gates are connected. A subtraction cell, characterized in that the outputs of are commonly connected to obtain a borrow output signal.