JPH087564A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize a semiconductor storage device capable of attaining the high speed of sense operations, capable of making electric charging and discharging currents to a bit line small and capable of reducing a power consumption. CONSTITUTION:Gate circuits Gio, the inverse of Gio amplifying signals in a direction from bit lines to input-output gates are provided in parallel with switching circuits Sio, the inverse of Sio for connections between bit lines and after sense operations. switching circuits Sio, the inverse of Sio arc released temporarily and simultaneously gate circuits Gio, the inverse of Gio are activated. Thus, signals of bit lines can be read out at high speed without impairing driving abilities of sense-amplifiers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as DRAM.

[0002]

2. Description of the Related Art With the recent increase in capacity of semiconductor memories,
The number of memory cells connected to bit lines is increasing.
As a result, the load capacitance of the bit line increases, the ratio of the memory cell capacitance to the bit line load capacitance decreases, the initial signal voltage applied to the sense amplifier decreases, and it hinders the speeding up of the sense operation. ing. In order to improve this point, conventionally, a method of dividing a bit line to secure an initial signal voltage above a certain level has been adopted.

FIG. 6 shows a Japanese Patent Laid-Open No. 61-
It is a figure which shows the structural example of the conventional semiconductor memory device described in 123093 gazette. This device is an example in which the bit line of each column is divided into a plurality.

In the figure, BLi0, * BLi0, BLi1,
* BLi1, ... Is a divided bit line pair in the i-th column,
WL00 to WL0n, WL10 to WL1n, ... Are word lines, C00 to C0n, C10 to C1n, .. are memory cells belonging to the same column, PRE0, PRE1 ,.
Are precharge circuits, SA0, SA1, ... Sense amplifiers, BK0, BK1, ... are divided blocks (memory array), Si0, * Si0, Si1, * Si1 ,.
.. is a switch circuit that connects bit lines of the block in series or opens them, Q1 and Q2 are transfer gates controlled by the column selection signal Y, and DB and * DB are data buses, respectively.

The memory cells C00 to C0n have a bit line pair B.
Memory cells C10 to C connected to Li0 and * BLi0
1n is connected to the bit line pair BLi1, * BLi1
It is divided into blocks K0 and BL1. Each block B
Sense amplifiers SA are provided for K0, BK1, ...
0, SA1, ... Are provided and these sense amplifiers S
A0, SA1, ... are block selection signals BS0, BS
Activated by 1, ...

FIG. 7 is a diagram showing a detailed configuration example of each part of FIG. 6, and FIG. 7A shows a bit line precharge circuit PRE,
(B) and (c) are bit line connection switch circuits S
i, (d) and (e) respectively show configuration examples of the sense amplifier SA.

As shown in FIG. 7A, the precharge circuit PRE has N-channel MOS transistors Q3 to Q5 whose gates are connected to the supply line of the precharge signal P.
The sources of the precharging transistors Q3 and Q4 are connected to the supply line of the power supply voltage (1/2) V _CC , and are equalized between the drains of the transistors Q3 and Q4 connected to the bit line pair BLi0 and * BLi0. Transistor Q5 is connected. When the precharge signal PRE is applied, the precharge circuit PRE0 having such a configuration causes the bit lines BLi0 and * BLi0 to have the same potential (1/2).
Precharge to V _CC -V _th ). The same applies to the precharge circuits PRE1, ... Of the other blocks.

The switch circuit Si shown in FIG. 7B is N
It consists of a channel MOS transistor Q6.
The switch circuit Si shown in (c) is formed by connecting the sources and drains of a transistor Q6 and a p-channel MOS transistor Q7 of the opposite conductivity type of the transistor Q6. The switch circuit Si shown in FIG. 7B is made conductive by inputting the clock signal φ1 to the gate of the transistor Q6. Further, the switch circuit Si shown in FIG. 7 (c) supplies the clock signal φ1 and its inverted signal * φ1 having complementary levels to the gates of the transistors Q6 and Q7, so that both transistors Q6 and Q7 are supplied.
6 and Q7 are turned on at the same time.

The sense amplifier SA shown in FIG. 7 (d) comprises N-channel MOS transistors Q8 and Q9 whose sources are connected to the supply line of the signal BS0, and the gate of the transistor Q9 and the drain of the transistor Q8 are connected to the bit line BLi0. Connected, and the gate of the transistor Q8 and the drain of the transistor Q9 are connected to the bit line * BLi0
It is connected to the. Further, the sense amplifier SA shown in FIG. 7E has a P-channel MOS transistor Q10 whose source is connected to the drain of each of the transistors Q8 and Q9 of the sense amplifier SA shown in FIG. It has a flip-flop configuration in which the drains of Q11 are connected to each other, so-called CMOS inverters are cross-coupled. Bit line pair BL for both sense amplifiers
Data having complementary levels of i0 and * BLi0 are latched and amplified.

In the semiconductor memory device having such a configuration, when one of the word lines WL00 to WL0n of the block BK0 is selected and the cell in the i-th column belonging to this word line is selected, the block select signal is selected. By BS0,
Only the sense amplifier SA0 is activated. As a result, the difference voltage between the bit lines BLi0 and * BLi0 is enlarged by the sense amplifier SA0, and in this state, all switch circuits Si are
0, * Si0, Si1, * Si1, ... Are held in a conductive state. As a result, each bit line BLi0, * BL
i0, BLi1, and * BLi1 are connected in series. Further, the column selection signal Y is supplied to the gates of the transistors Q1 and Q2 at a high level to control the gates Q1 and Q2 to be in a conductive state, the bit line pair is connected to the data buses DB and * DB, and the data buses DB and * DB. The data is read out on the DB.

The advantage of the bit line division described above is that the load capacitance of each sense amplifier during the sensing operation is small, that is, the load capacitance of only one set of divided bit line pairs is sufficient.

[0012]

However, in the above-mentioned conventional semiconductor memory device, the switch circuits Si0, *
When SIO, Si1, * Si1, ... Are made conductive and the bit line pair is connected, the load capacitance of the sense amplifier increases to the value before the bit line division. Therefore, the voltage once amplified on the bit line pair is reduced, the driving capability of the sense amplifier is impaired, and the time required to finally generate a required differential voltage on the data buses DB and * DB is shortened. Never.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of speeding up a sensing operation, reducing the charge / discharge current of a bit line, and reducing power consumption. To do.

[0014]

In order to achieve the above object, a semiconductor memory device according to the present invention, in which a bit line is divided into a plurality of memory arrays, has a sense amplifier provided for each memory array and an adjacent memory. It has switch means for connecting the bit lines belonging to the array to each other, and gate means connected in parallel with the switch means for the bit lines.

Further, in the semiconductor memory device of the present invention, the adjacent memory arrays share a sense amplifier for every two adjacent memory arrays. In addition, the gate means,
Further, the sense amplifier is activated sequentially from the side far from the output port, and the sense amplifier has two terminals for applying an operating voltage, and a fixed voltage is applied between these two terminals.

In the semiconductor memory device of the present invention, the potential of the bit line is set to the first potential and then selectively changed to the second potential.
In order to discharge the bit line, a transistor is provided between each bit line and the second potential, and the gate terminal of this transistor is controlled by the output of the sense amplifier.

[0017]

According to the semiconductor memory device of the present invention, the bit line of the next stage is subjected to, for example, an amplifying action by the gate means provided in parallel to the switch means without passing through the switch means for connecting between bit lines. Be transmitted to. In this case, the bit line signal is read at a high speed without impairing the drive capability of the sense amplifier by temporarily opening the switch unit for connecting between bit lines after the sensing operation and activating the gate unit at the same time.

The sensing operation is performed until the potential of the selected bit line reaches the potential required for rewriting in the memory cell, and then the gate means is activated.
Further, before the potential of the bit line completely reaches a predetermined voltage, the switch means for connecting between bit lines is opened and the gate means is activated to further speed up the read operation. However, in the latter case, for example, after the signal is read to the data bus, the column select gate is opened, the switch between the bit line belonging to the selected block and the sense amplifier is closed, and the sense amplifier is changed to the bit line again. It is necessary to apply the voltage required for writing.

[0019]

1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, in which the same components as those in FIG. 6 showing a conventional example are designated by the same reference numerals. That is, BL
i0, * BLi0, BLi1, * BLi1, ... Are bit line pairs divided in the i-th column, WL00, WL01 ,.
··· is a word line, C00, C01, ··· are memory cells belonging to the same column, PRE0, ··· are precharge circuits, SA0, ··· are sense amplifiers, SW0, * SW
0, ... Are switch circuits for operatively connecting the memory cells C00, C01, ... And the sense amplifiers SA0, ..., BK0, BK1 ,. Si0, * Si0, Si1, * Si
1, ... Are switch circuits for connecting the bit lines of the block in series or opening them, Q1, Q2 are transfer gates controlled by the column selection signal Y, and DB, * DB are data buses, respectively. There is.

The precharge circuit PRE0 is shown in FIG.
The N-channel MOS transistors Q3 to Q5 each having a gate connected to the supply line of the precharge signal P have the same structure as that shown in FIG. ) An equalizing transistor Q5 is connected between the drains of both transistors Q3, Q4 connected to the V _CC supply line and connected to the bit line pair BLi0, * BLi0. When the precharge signal P is applied, the precharge circuit PRE0 causes the bit lines BLi0 and * BLi0 to have the same potential (1 / 2V _CC
Precharge to −V _th ). The not-shown precharge circuits PRE1, ... Of the other blocks also have the same configuration and function.

The memory cell C00 is connected to the bit line BLi0.
Reference potential (eg ground line) V _PConnected in series between
Continued N-channel MOS transistor Q_COAnd
Pasita C_C0And transistor Q_C0of
The gate is connected to the word line WL00. Similarly,
The memory cell C01 has a bit line * BLi0 and a reference potential V
_PN-channel MOS transistor connected in series between and
Star Q_C1And capacitor C_C1Consists of
Transistor Q_C1Connected to word line WL01
Have been. Other memory cells not shown have the same configuration.
are doing.

The switch circuits SW0 and * SW0 are inserted into and connected to the bit lines BLi0 and * BLi0, respectively.
It is constituted by channel MOS transistors Q12 and Q13, and the gates of both transistors Q12 and Q13 are connected to the supply line of signal φ00.

The sense amplifier SA0 has a structure similar to that shown in FIG. 7E, and the drain and the gate are connected to each other between the supply line of the signal BS0 and its supply line of the inverted signal * BS0. An inverter including an N-channel MOS transistor Q8 and a P-channel MOS transistor Q10, and an inverter including an N-channel MOS transistor Q9 and a P-channel MOS transistor Q11 are formed by flip-flops that are cross-coupled between bit lines BLi0 and * BLi0. There is.
The sense amplifier SA is a bit line pair BLi0, * BLi.
Data having a complementary level of 0 is latched and amplified.
The sense amplifiers (not shown) of the other blocks BK1, ... Have the same configuration.

Switch circuits Si0, * Si0, Si1,
* Si1, ... Have a structure similar to that shown in FIG. 7B, and N-channel MOS transistors Q6 ₀ , * Q6 ₀ , Q inserted and connected to the bit line pair between each block.
6 _1, * Q6 _1, is constituted by ..., the gate of the transistor Q6 ₀ and * Q6 ₀ is connected to the supply line of the signal .phi.10, transistor Q6 _1, * Q6 ₁ gate is connected to the supply line of the signal φ11 Has been done. And
.. are connected in series or opened according to the input level of the signals .phi.10, .phi.11, ....

The gate circuits GT0 and * GT0 are provided in parallel with the switch circuits Si0 and * Si0 for the bit line pair. Gate circuit GT0 has signals φ20 (for example, power supply voltage V _CC level) taking complementary levels, * φ20.
The CMOS inverter is formed of a P-channel MOS transistor Q20 and an N-channel MOS transistor Q21 whose drains and gates are connected between (for example, ground level) supply lines. Then, the transistor Q2 that is an input of the gate circuit GT0
The connection point between the gates of 0 and Q21 is connected to the bit line * BLi0 between the block BK0 and the switch circuit * Si0, and the transistor Q2 is the output of the gate circuit GT0.
The connection point between the drains of 0 and Q21 is a switch circuit Si
It is connected to the bit line BLi1 between 0 and the block BK1.

The gate circuit * GT0 has complementary levels.
Signal φ20 (for example, power supply voltage V _CCLevel), * φ2
Drain or drain between 0 (eg ground level) supply lines.
And P-channel MOS transistor with gates connected to each other
Star * Q20 and N-channel MOS transistor * Q
21 composed of a CMOS inverter
It Then, the transition that becomes the input of the gate circuit * GT0
The connection point between the gates of the star * Q20 and * Q21 is block
Bit line BLi between the black circuit BK0 and the switch circuit Si0
0 connected to the gate circuit * GT0 output
The connection point between the drains of transistors * Q20 and * Q21 is
Bit line between switch circuit * Si0 and block BK1
* Connected to BLi1.

Therefore, for example, the switch circuit Si0
And * Si0 are non-conductive, the bit line BLi
Assuming that the level of 0 is the V _CC level and the level of the bit line * BLi0 is the ground level, the level of the bit line BLi1 of the memory array of the next stage is the inverter gate circuit G.
Since the signal of the ground level of the bit line * BLi0 is input to the input of i0, it becomes the level of the signal φ20, that is, the V _CC level. The level of the bit line * BLi1 of the memory array of the next stage is the inverter gate circuit * Gi.
Since the V _CC level signal of the bit line BLi0 is input to the 0 input, it becomes the level of the signal * φ20, that is, the ground level. In this way, the gate circuits Gi0 and * G connected in parallel to the switch circuits Si0 and * Si0.
Due to the presence of i0, the switch circuits Si0 and * Si0
Bit line pair BLi0, * BL
i0 data is transferred to the next bit line pair BLi1, * BLi1
Can be communicated to.

Other switch circuits Si1, * Si
The gate circuits GT0, * G described above for 1, ...
Gate circuits GT1 and * having the same structure and function as T0
GT1, ... Are connected in parallel.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. The bit line pair BLi0, * BLi0 is precharged.

First, in the initial state, the signals * RAS, * C
Both AS are high level. At this time, the precharge signal P is at a high level, and the bit line pair BLi0,
* BLi0 is preset to high level.

Next, when the signal * RAS falls from the high level to the low level, the row address is latched from the address bus and, for example, the selected word line WL0.
The level of 0 is raised from low level to high level. At this time, the precharge signal P is switched from the high level to the low level. Selected word line W
With the switching of the level of L00 to the high level, the transistor Q _C0 of the memory cell C00 becomes conductive, and the charge accumulated in the capacitor C _C0 becomes the bit line BL.
It is read to i0. In this case, while the potential of the bit line BLi0 and the bit line * BLi0 forming the bit line pair is the precharge voltage (1/2) V _CC , the bit line BLi0
An initial voltage higher or lower than the precharge voltage by ΔV is applied to 0 depending on the information stored in the memory cell C00.

Next, the signal φ00 is raised from low level to high level, and the switch circuits SW0 and * S are switched.
W0 is held in the conductive state. And the sense amplifier S
The signal BS0 for starting A0 is lowered from the high level to the low level, and conversely, the signal * BS0 is raised from the low level to the high level. As a result, the sense amplifier S
A0 amplifies the potential difference between the bit line pair BLi0, * BLi0. As a result, the potentials of the bit line pair are held at the power supply voltage V _CC level for bit line BLi0 and at the ground level for bit line * BLi0, for example.

After that, the signal φ20 falls to the high level and the signal * φ20 is set to the low level. At this time, the signal φ10 is held at the low level, and the switch circuits Si0 and * Si0 are held in the non-conductive state. Since the signal φ20 is set to the high level and the signal * φ20 is set to the low level, the level of the bit line BLi0 is the V _CC level and the bit line * BLi is set as described above.
Assuming that the level of 0 is the ground level, even if the switch circuits Si0 and * Si0 are in the non-conducting state, the level of the bit line BLi1 of the memory array of the next stage is the bit to the input of the inverter gate circuit Gi0. line*
Since the signal at the ground level of BLi0 is input, it becomes the level of the signal φ20, that is, the V _CC level. Also,
The level of the bit line * BLi1 of the memory array in the next stage is
The bit line BL is input to the inverter gate circuit * Gi0.
Since the signal at the V _CC level of i0 is input, the signal *
The level becomes φ20, that is, the ground level. In this way, the potential of the bit line pair is set to the gate circuits Gi0, * Gi.
0, Gi1, * Gi1, ... Are sequentially transmitted to the bit line on the input / output port side.

After that, the signal * CAS is lowered from the high level to the low level to latch the column address, and then the signals φ00, ... Are dropped from the high level to the low level, and the column selection signal Y is output. Is selectively raised from the low level to the high level, and the information read from the memory is transmitted to the data buses DB and * DB.

As described above, according to this embodiment,
Switch circuit for bit line connection Si0, * Si0,
.. are provided in parallel with gate circuits Gi0, * Gi0, ... Amplifying signals in the direction from the bit line to the input / output gate,
Switch circuit Si for connection between bit lines after sensing operation
Since 0, * Si0, ... Are temporarily opened and the gate circuits Gi0, * Gi0, ... Are activated at the same time, the bit line signal can be read at high speed without impairing the driving capability of the sense amplifier. You can

The sense operation is performed until the potential of the selected bit line reaches the potential necessary for rewriting to the memory cell, and then the bit line signal amplification gate circuits Gi0, * Gi0 ,. Even if it is configured to activate, the same effect as the above-described effect can be obtained. Also, before the potential of the bit line completely reaches a predetermined voltage, switch circuits Si0, * Si0, ...
.. are opened and gate circuits Gi0, * Gi are opened
The read operation can be further speeded up by activating 0, .... However, in the latter case, after reading the signal to the data buses DB and * DB, the column selection gate is opened, the switch circuit between the bit line belonging to the selected block and the sense amplifier is closed, and the bit from the sense amplifier is closed. It is necessary to apply the voltage necessary for rewriting to the line.

In this embodiment, the case where a sense amplifier is provided for each block (memory array) has been described as an example. However, for example, an adjacent memory array has a sense amplifier for every two adjacent memory arrays. It goes without saying that the present invention can be applied to a so-called shared sense amplifier system for sharing.

FIG. 3 is a circuit diagram showing a main structure of a second embodiment of the semiconductor memory device according to the present invention. This embodiment is different from the first embodiment described above in that an inverter as a gate circuit is provided only on one of the bit line pairs. In this case, the information from the block BK0 to the block BK1 is transmitted from the bit line * BLi0 to the bit line BLi1. Then, the connection of the buffer from the bit line BLi1 to the output port needs to invert the connection of the inverter alternately. In this case, data bus DB, * DB
Is a signal which is preset to an intermediate value between the positive and negative power supply voltages and which is delayed from the rise of the column selection signal Y for selectively activating the transfer gates Q1 and Q2, for example, a signal delayed from the CAS signal. DB and * DB should be sense-amplified. With such a configuration, in addition to the effect of the first embodiment described above, there is an advantage that the discharge current of the bit line used for passing can be halved.

FIG. 4 is a circuit diagram showing a main structure of a third embodiment of the semiconductor memory device according to the present invention. This embodiment is different from the above-described second embodiment in that the gate circuit Gi0
Inverter IV1,
IV2 has a two-stage configuration in which cascade connection is made, and the output is bit line B
The input of the gate circuit Gi0 connected to Li1 is not connected to the bit line * BLi0 but to the bit line BLi0. According to this embodiment, it is not necessary to perform the sense amplification of the data line, and the discharge current of the bit line can be reduced.

FIG. 5 is a circuit diagram showing a main structure of a fourth embodiment of the semiconductor memory device according to the present invention. In FIG. 5, TF1 and TF2 are a transfer gate formed by connecting drains and sources of N-channel MOS transistors and P-channel MOS transistors to each other, and DSA.
Is a differential amplification type sense amplifier, and Q20 is an N-channel MOS transistor as a gate circuit.

The present embodiment has a structure corresponding to a device for precharging the bit line to the V _CC level instead of precharging it to 1/2 V _CC . That is, in the present device, the bit line is precharged to the high level which is the power supply voltage V _CC level, and the transistor Q20 is connected to the sense amplifier SA only when the low level (ground level) is transmitted.
Is driven to pull the bit line BLi1 of the next stage to the ground level. Also in this embodiment,
It is possible to obtain the same effect as that of the first embodiment described above.

[0042]

As described above, according to the present invention,
The sense operation can be speeded up, the bit line charging current can be reduced, and power consumption can be suppressed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG.

FIG. 3 is a circuit diagram showing a main configuration of a second embodiment of a semiconductor memory device according to the present invention.

FIG. 4 is a circuit diagram showing a main part configuration of a third embodiment of a semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram showing a main configuration of a fourth embodiment of a semiconductor memory device according to the present invention.

FIG. 6 is a diagram showing a configuration example of a conventional semiconductor memory device.

FIG. 7 is a diagram showing a specific configuration example of a main part in FIG. 6, in which (a) is a configuration example of a bit line precharge circuit;
(B), (c) is a figure which shows the structural example of a switch circuit for bit line connection, (d), (e) is a figure which shows the structural example of a sense amplifier.

[Explanation of symbols]

BLi0, * BLi0, BLi1, * BLi1, ...
... bit line pair, WL00, WL01, ... word line C00, C01, ... memory cell PRE0, ... precharge circuit SA0, ... sense amplifier SW0, * SW0, ... ... switch circuit BK0, BK1, ... Divided block (memory array) Si0, * Si0, Si1, * Si1, ... Switch circuit Q1, Q2 ... Transfer gate DB, * DB ... Data bus

Claims (5)

[Claims] 1. A semiconductor memory device in which a bit line is divided into a plurality of memory arrays, wherein a sense amplifier provided for each memory array and a switch for connecting the bit lines belonging to an adjacent memory array to each other. And a gate circuit connected in parallel with the switch circuit for the bit line. 2. The semiconductor memory device according to claim 1, wherein the adjacent memory arrays share a sense amplifier for every two adjacent memory arrays. 3. The semiconductor memory device according to claim 1, wherein the gate means is activated in order from the side farther from the output port. 4. The semiconductor memory device according to claim 1, wherein the sense amplifier has two terminals for applying an operating voltage, and a fixed voltage is applied between these two terminals. 5. A transistor is provided between the bit line and the second potential for each bit line because the potential of the bit line is set to the first potential and then selectively discharged to the second potential. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided, and the gate terminal of the transistor is controlled by the output of the sense amplifier.