JPH087253B2 - A method for converting a switch-level circuit representation logic tree into a Boolean representation logic tree - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial field of use B. Prior art (FIGS. 2 to 5) C. Problems to be solved by the invention D. Means for solving problems E. Example E-1. Failure Modeling E-2. Boolean model of buffer and precharge circuit (Fig. 6) E-3. Modeling of logic tree (Figs. 7 and 8) E-4. Boolean representation of circuit (Fig. 1) F. EFFECTS OF THE INVENTION A. INDUSTRIAL FIELD OF APPLICATION The present invention relates generally to integrated circuits, and more particularly to a method of displaying differential cascode voltage switches by means of Boolean gates for fault simulation.

B. Prior Art In the manufacture of integrated circuits, the probability that a particular chip will not work as designed is generally quite high. Due to slight manufacturing variations, certain chips may not show the correct output for a particular input. Such failures often occur randomly for each chip. Therefore, it is a common test method to subject each chip to a test pattern and then measure the output. U.S. Pat. No. 3,927,371 discloses a method of applying a test pattern to a physical circuit and a computer simulation of the circuit and comparing the results. However, failures are usually revealed only by specific test patterns. For relatively simple integrated circuits, such as flip-flops, it is possible to create a series of test patterns that test all possible combinations of input patterns.
Therefore, such a simple chip can be fully tested. However, some advanced integrated circuits use a large number of input variables. This is, in particular,
This is the case when the integrated circuit contains storage elements and the inputs in one cycle can only be tested in the following cycle. Theoretically, it is possible to completely test all input patterns, but even the fastest automated tester cannot complete the test in a reasonable amount of time and at a relatively low cost. Therefore, when designing an integrated circuit, it is desirable to create a series of test patterns that can catch all possible failures in the circuit. The number of test patterns should be as low as possible to reduce test costs. This type of fault simulation for determining testability is described in US Pat.
No. 598. Creating these test patterns requires knowledge of circuit design as well as knowledge of failures that are likely to occur in the circuit.

The failure simulation requires a workable model of the integrated circuit, and the model is populated with failures corresponding to those that may occur in the actual chip. next,
Generate a test pattern that catches a specific failure.
That is, the test pattern produces different outputs from the model depending on the presence or absence of a fault. This pattern is
Used to test the actual integrated circuit to determine if the circuit is faulty. It is not easy to get the required test pattern, because a failure often gives the correct output for a significant portion of the input pattern. U.S. Pat. No. 4,204,633 discloses a method of generating a test pattern that makes the faults so inserted visible at the output. Needless to say,
A significant number of test patterns are needed to catch all or almost all failures. However, good selection of test patterns can significantly reduce the cost of testing, or alternatively increase the coverage of a certain number of test patterns (ie the percentage of detected failures). .

There are various levels of abstraction in the circuit model that can be used for failure simulation. For each level of simulator, VLSI Design, February 1984, 27
“A System Engineers Guide to Simulato” on page 31
A general explanation is given in an article entitled "rs)". For one type of simulator, see US Pat. No. 4,308,616.
No. specification.

The conceptually simplest is probably the switch level. An indication of switch level in a circuit is the interconnection of transistors and the like. The type of transistor, be it bipolar or MOS, depends on the technology used in the integrated circuit. Failures can be relatively easily entered into the switch level display. However, when the transistors are all interconnected according to the chip design, a very complex, non-linear circuit results. In such a switch level circuit, it is extremely difficult to evaluate the relationship between the input and the output.

Another type of representation is a Boolean model in which Boolean gates such as AND or OR gates are used. Boolean circuits are much easier to evaluate mathematically. The Boolean model may be more complex than the corresponding switch-level model, but once the model is set up, sophisticated and efficient computer simulation is possible.

Many bipolar circuit elements can be easily converted into equivalent Boolean elements. However, MOS circuit elements are much more difficult to translate MOS faults into correctly simulating Boolean elements.

One of the recently developed types of MOS circuits is the differential cascode voltage switch (DCVS). This kind of circuit is 1984
"Cascode Voltage Swit Logic Family" found in the minutes of the IEEE International Solid State Circuit Conference in San Francisco, February 22-24, 2012.
ch Logic Family) ”disclosed by Heller et al. A circuit of this kind is also described in U.S. patent application Ser. No. 554146, issued Nov. 21, 1983. One row of the DCVS circuit is shown in FIG. This circuit consists of an arbitrary number of logic trees 10, each associated with a buffer and precharge circuit (B & P) 12.
A combination of the logic tree 10 and its buffer and precharge circuit 12 is called a logic module. The buffer and precharge circuit 12 is generally the same, but the internal structure of the logic tree 10 may be different. The DCVS circuit relies in all respects on the presence of complementary signals. Each primary input has a complement and an exact version PIO _i and PI1 _i . Tree fi
The output of the logic module containing is the complement and antilog version F0 _i and F1 _i of the same logic signal. The inputs to the logic tree 10 are either the complementary inputs PI0 _i and PI1 _{i of} the primary inputs, or the complementary versions F0 _i and F1 _i of the outputs of different trees, which are collectively referred to as major nets. The interconnection shown in Figure 2 is only an example of a possible variation.

Details of the buffer and precharge circuit 12 are shown in FIG. Next, the effect of this circuit on the logic tree 10 will be described. The logic tree 10 has a complement tree output T0 and an exact tree output T1. The top two precharge P channel switches 13 and 14 separate the complement and antilog outputs T0 and T1 from the positive voltage source. The lower n-channel precharge switch 16 separates the ground node R of the logic tree 10 from ground. During the precharge period, the precharge signal controlling precharge switches 13, 14 and 16 goes low, isolating logic tree 10 from ground and connecting it to a positive power supply. Therefore, the two tree outputs T0 and T1 are charged.

The antilogarithm tree output T1 is connected to the antilogarithm output node F1 via a CMOS inverter composed of a P-channel switch 18 and an n-channel switch 20. The signal on the antilogarithmic output node F1 feeds back to the antilogarithmic tree output T1 through a P-channel feedback switch 22 connected to a positive voltage source. Feedback switch 22 is a weak gate,
The feedback circuit is made to follow the signal of the tree output T1. The feed back switch 22 compensates for leakage from the tree output T1 to ground and signal fluctuations. Therefore, during the precharge period, the high level signal on the precharged tree output T1 causes the true output node F1 to go low.

The complement tree output T0 has a similar circuit connected to the complement output node F0. In a functioning circuit, the tree output T0
The signals on and T1 are complementary to each other, as are the outputs on output nodes F0 and F1. CMOS inverter has output node F0
And F1 are complementary to the corresponding tree outputs T0 and T1.

The logic tree 10 is an NMOS, that is, an n-channel MOS switch. The logic tree 10 is controlled by any even number of network managers G0 ₁ , G1 ₁ , G0 ₂ and G1 ₂ .
In normal operation, G0 ₁ is complementary to G1 ₁ and G0 ₂ is complementary to G1 ₂ .
As mentioned above, the major nets may be the primary inputs PI0 _i and PI1 _i to the DCVS circuit and may be connected to different logic tree output nodes F0 and F1.

The structure of the logic tree 10 depends on which logic function of its major net input it is designed to represent. An example of a logical tree is shown in FIG. This logic tree 10 comprises three interconnected differential pairs 2 each controlled by complementary mages nets G0 _i and G1 _i .
Consists of four. This particular tree structure was chosen for illustration only. The magazine nets to different differential pairs 24 may be the same. Importantly, in a circuit that is normal for any signal value on the major net, only one of the switches in differential pair 24 will conduct. Furthermore, as can be seen by following the path upward from the ground node R, either the complement tree output T0 or the true tree output T1 for any combination of signals on the major nets G0 _i and G1 _i . It can be seen that there is one conduction path from only one to the ground node R. This is because the switch is working correctly,
It can be seen in the fault-free circuit where the major net G0 _i is complementary to the major net G1 _i .

The basic building block of the logic tree 10 is the differential pair 24 shown in more detail in FIG. The differential pair 24 consists of two n-channel switches 26 and 28, the gate electrodes of which are controlled by complementary magenta nets G0 and G1. The sources of both switches 26 and 28 are both connected to a common input source S. Two switches 26 and 28
Drains are output drains D0 and D1. In normal operation, one of the two switches 26 and 28 is conducting, regardless of the signal value on the major network G0,
The other is non-conductive.

If the tree outputs T0 and T1 are properly precharged, the closing net of the lower precharge switch 16 causes either the tree output T0 or T1 to be discharged, depending on the signal value of the major net. This discharge takes place in what is called the evaluation phase. After evaluation, the signal on tree output T0 must be complementary to the signal on tree output T1.

The rules for interconnecting the differential pair 24 are as follows. That is, the major nets G0 _i and G1 _i are from the primary inputs or other tree outputs T0 and T1. These major nets G0 and G1 must be in single variable antilog and complement form. Differential tree output D0
And D1 can be connected to the input S of a single differential pair 24 at the upper level of tree 10 or only to a single tree output T0 or T1. The input S of the differential pair 24 can only be connected to the output D0 or D1 of one or more lower level differential pairs, or to the ground node R.

Also, the outputs D0 and D1 of different differential pairs 24 can be dot coupled at any time. This dot combination is used to share the dependency tree, thereby reducing the number of differential pairs 24 that should perform the required logic function. Tree output T0 and
Dot coupling at T1, and possibly other internal nodes, results in a structure that is not strictly a tree, at least in the graph-theoretic sense.

During precharge, the tree outputs T0 and T1 are both held at a positive voltage, so during precharge the output node
Both F0 and F1 are low level, that is, logic 0. As a result, all switches in the logic tree are non-conducting during precharge.

D. Problems to be Solved by the Invention The DCVS circuit has many advantages. However, since the DCVS is composed of MOS switches as described above, it is difficult to simulate it as a Boolean gate.

Accordingly, it is an object of the present invention to provide a Boolean level representation of a differential cascode voltage switch circuit.

It is another object of the present invention to provide a Boolean level representation of the DCVS circuit to simulate faults which may correspond to faults in the actual chip.

E. Means for Solving the Problems In summary of the present invention, each switch level logic tree has three
A Boolean representation of a DCVS circuit, replaced by a section Boolean logic tree. Each logic switch is replaced by an AND gate and one of its inputs is suppressed by the gate network of the gate it represents. In the first section of the tree, the other input of the AND gate is connected to the input of the differential pair and the output of the AND gate is connected to the output of the differential pair. The two outputs of the first section are connected as two inputs to the second section. AND in the second section
The other input to the gate is the corresponding output of the differential pair.
The two outputs of the paired AND gates are coupled to an OR gate whose outputs are connected to the inputs of the differential pair. One of the valid outputs of the second section is connected to one of the inputs of the third section. The third section is similar to the first section except that the inputs to the differential pair are conducted to the inputs of the OR gate and the other input is connected to the output of the corresponding OR gate of the second section. Is. Failures are so introduced at all corresponding points in the three sections. Depending on the type of failure, only the first section is needed.

E. Examples E-1. Modeling Faults In a good example, in simulating possible faults inherent in a circuit using a Boolean format circuit representation translated from a switch level circuit representation. First, an important failure of the differential cascode voltage switch (DCVS) circuit will be described. It is assumed that the selected fault is in both the logic tree 10 and the buffer and precharge circuit 12. This model is based on the assumption that only one simulation failure will occur in the entire DCVS circuit. The selected simulation failures are:

1. Switch 26 or 28 in logic tree 10 is the signal on the gate
It remains open or non-conductive regardless of G0 or G1.

2. The switch 26 or 28 in the logic tree 10 is the signal on the gate.
It remains closed or nonconductive regardless of G0 or G1.

3. The signal at the output node F0 or F1 of the buffer and precharge circuit 12 drops slowly. That is, if the output node F0 or F1 is designed to transition from 1 to 0, that will eventually be the case, but it will take a very long time.

4. The signal on the output node F0 or F1 of the buffer and precharge circuit 12 remains zero regardless of the corresponding signal at the output T0 or T1.

5. The signal on the output node F0 or F1 remains 1 regardless of the signal at T0 or T1.

The simulation failure in the buffer and precharge circuit 12 is used to simulate many different physical failures in the circuit switch. The upper portion of the buffer and precharge circuit 12 is divided into two symmetrical parts, driving one complement output node F0 and the other driving the true output node F1. True output node F1
Only faults in the part driving the are analyzed here, but a similar explanation applies to the other half.

Table 1 shows the module response in the presence of this fault. The first physical failure modeled is the switch.
14 will remain open. This fault is a logic tree 10
It is only found when the input of the major net to is trying to generate a logic one followed by a logic zero on the true output node F1. Note that the output during the precharge stage is not considered observable. This fault is simulated as a slow descent fault on the true output node F1. As will be explained later, there are some inaccuracies in this simulation, but the model is nevertheless useful for simulating the behavior caused by the switch remaining open.

The second physical failure to model is that switch 20 remains open. The outputs of all combinations of inputs of the logic tree are shown in Table 2. Again, this failure is simulated as a failure of the true output node F1 to slow down.

A third failure that simulates is that switch 18 remains open. Table 3 shows the response of the antilogarithmic node output F1 in the presence of this fault. This fault is simulated as a fault in which 0 remains on the true number output node F1. To detect this, a single input pattern of primary inputs that would normally generate a logic one on the true output node F1 is sufficient. In this case, the antilogarithmic output node F1 remains 0. The precharge stage is only useful as an initialization pattern, not for actual failure simulation.

Failure of the feedback switch 22 which is left open is not simulated. Switch 22 is a logical tree 10
Are added to the buffer and precharge circuits to eliminate the glitches that result from sharing the precharge with multiple internal nodes of the. A fault in which the switch 22 remains open may re-issue mainly the glitch problem.

The lower precharge switch 16 prevents spurious discharges during precharge. If this switch 16 is closed, ie, remains conductive, this failure can cause such spurious discharges. This discharge may cause both output nodes F0 and F1 to be logic one. This problematic failure is not simulated.

If the precharge switch 16 remains open, this fault will prevent discharge of both outputs T0 and T1.
As a result, output nodes F0 and F1 remain at zero. This fault does not need to be simulated because it is dominated by the 0 fixed fault on the true output node F1 and the 0 fixed fault on the complement output node F0.

The consequences of a fault in which switches 14, 18, 20 and 22 remain closed are more complex and need to be analyzed considering the various switch sizes. These failures are not simulated. Further modeling is needed to model switch faults that lead to slow down faults at the output node F0 or F1. As explained above, slow down faults are tested by generating two patterns of primary inputs. The first pattern sets the output node F1 to 1.
The second pattern sets the normal output node F1 to 0. If the output node F1 remains 1 for the second pattern and this change is propagated to the output of the DCVS circuit, this test will detect the fault. Thus, a simulation for testing a switch 14 that has been left open programs a sequence of two patterns in which the output node F1 is set to 1 at time T and 0 at time T + 1, and then at time T +.
To test that at 1, the output node F1 remains at 1.

The slow descent failure model requires that actual chip tests be performed at intervals where the signal cannot drop.
However, the upper precharge switch 14, which remains open, means that the tree output T1 is not precharged. The fact that the output T1 cannot be precharged is
It is shown that the antilogarithmic output node F1 is maintained at 1 for a considerable period of time after it has legally become 1. It is difficult to determine how long the output node F1 is fixed at 1.

Using a slow descent model is pessimistic. Actual faults, such as the upper precharge switch 14 remaining open, are easier to physically test than modeled faults, such as a slow drop of the output node F1. However, the pessimistic model is also useful because the main concern when modeling a failure is to simulate the test procedure to ensure that the failure is highly covered.
The scope of the pessimistic model is narrower than that obtained by physical testing. Therefore, the actual coverage is at least as good as that calculated for the pessimistic model.
Further, the pessimistic model identifies failures that are not determined to be tested by the test procedure according to a pessimistic but simple model. The remaining, relatively few unknown failures can be simulated by a realistic and expensive model that determines whether the test procedure actually tests them. Realistic models are used for these few failures that require more realistic and more expensive models.

Next, the Boolean modeling (display) will be described item by item for each constituent unit of the logic module (that is, the buffer / precharge circuit 12 and the switch-level logic tree 10) in the DCVS circuit of the preferred embodiment. .

E-2. Boolean Model of Buffer and Precharge Circuit The Boolean model of buffer and precharge circuit 12 is shown at 30 in FIG. One failure inserter
32 is placed between the complement tree output T0 and the complement output node F0,
The other fault inserter 32 is likewise placed between the true output node F1 and the true output node F1. In a fault-free circuit, the fault inserter 32 simply passes any signal. The fault inserter 32 can selectively route faults onto the net. At that time, the fault inserter 32 keeps its output at the fault value regardless of the input. In a single-fault simulation, only one fault inserter 32 is activated at a time. The inserted fault is one of 0 fixed fault, 1 fixed fault, and slow drop fault. There are a few things I have to touch here. The fault inserter 32 does not invert the signal in a fault-free switch as the CMOS inverters in switches 18 and 20 do. However, the lack of inverter function is compensated for by choosing an indication for the value of the ground node R. Ground voltage is 1 at Boolean level
It is represented by. Therefore, the Boolean values for tree outputs T0 and T1 are the opposite of the switch level values.

E-3. Modeling of Logical Tree Modeling of the logical tree 10 is a more difficult problem. The logic tree can take any form as long as it fits the DCVS circuit. The resulting logical tree is not only general in construction, but can be quite large. The complexity of the Boolean representation of generalized circuits, not just DCVS circuits, increases rapidly with the number of switches in the circuit. However, the present invention reduces complexity by
It takes advantage of some unique properties of DCVS. Modeling is performed for two types of physical failures in the logical tree 10.

1. The first type of fault to model is one in which switch 26 or 28 remains open, ie non-conducting. The faulty switch is connected to the ground node R and the output T0 or
When it is in the discharge path between T1 and T1, no discharge occurs, and the output nodes F0 and F1 both become logic 0 because of the CMOS inverter. The logic tree 10 produces the correct values at the output nodes F0 and F1 for all major net inputs if the failed switch is not in the normal discharge path.

2. The second fault to model is that the switch 26 or 28 of the logic tree 10 remains closed. Consider an input pattern of a major net that normally sets the true tree output node F1 to logic 1 (0). This means that this special input pattern forms a discharge path between the ground node R and the output T1 (T0). A faulty switch that remains closed forms a discharge path to the other tree output T0 (T1). Outputs T0 and T1
If there is a discharge path in both of the above, both of the output nodes F0 and F1 become logic 1. If the special input pattern does not form a second discharge path at the other tree output T0 (T1), the logic module will still output nodes F0 and F1 in the presence of this fault.
Generates the correct function output on.

The model does not include other types of failures. In particular, it is assumed that there is no fault in the interconnection between the switches and the modules. Therefore, the input to a certain switch is
It can be equal to the output of another switch connected to it. Faults that remain closed or closed in the logic tree are identified by a gate input fixed to a particular value. Referring to FIG. 5, leaving the n-channel switch 26 open is equivalent to having the major net input G0 on its gate fixed at zero. Similarly, switch 26 remaining closed means that net G0 is 1.
Is equivalent to being fixed to. Thus, as in the case of buffer and precharge model 30 (FIG. 5), the fault is introduced on the interconnection. In this case, the fault is so injected on the major net input to the faulty switch. 0 for faults fixed at 0 and 1 respectively
Let's call it failure and 1 failure. B fault is a general name, depending on whether B = 0 or B = 1, 0 fault or 1
It is a malfunction.

Models of faults in logic trees are based on a series of mathematical theorems. This mathematical method seems necessary because there are nearly infinite kinds of logical trees. The inventors have explained these theorems, but no proof is given here. If possible, make an intuitive justification for the validity of the theorem shown.

[Theorem 1] When the DCVS circuit has only a B fault, the signal value on the major network in the faulty DCVS circuit almost matches the correct value. A near match means that if the correct value is not B, then the only kind of error value that can occur in the manager net is B. The major net that should supply B will supply B regardless of failure.

The basic characteristics of a failure-free DCVS circuit are as follows. After the evaluation, what happens to the precharge on the corresponding tree output T0 or T1 to determine the signal values on the output nodes F0 and F1 (whether the precharge remains after the evaluation, or the logic tree 10 to the ground node R). Whether it is discharged by the conduction path) must be determined. Starting from the ground node R, we move upwards towards the tree outputs T0 and T1 (the upper coincides with the upper in FIG. 4) to mark the conducting paths in the logic tree. If the source input S of the differential pair 24 is included in the conduction path, the drain output D0 or D1 is marked as in the conduction path, depending on the values of the major nets G0 and G1. Eventually the conduction path reaches one of the tree outputs T0 or T1. This marked tree output is part of the conduction path to ground node R and is discharged through this conduction path. The other, or unmarked, tree output T0 or T1 has no conductive path and is not discharged. Moving the logic tree up once can compute the stage of each major net in a fault-free DCVS circuit. The following theorem extends this to faulty circuits.

[Theorem 2] When there is no failure in the DCVS circuit or there is only 0 failure, the result of the evaluation phase of any module is calculated by moving the logic tree 10 of that module once upward. On the other hand, when the circuit has only one fault, the result of the evaluation phase of any module is calculated in three movements (passes) of upward, downward and upward.

The characteristics of this DCVS circuit do not resemble the behavior of other types of double-sided transistor networks at all. For other types of circuits, the number of paths required increases with the number of transistors in the switching network. For large networks, it is necessary to use multiple paths. In contrast, the DCVS circuit requires only a maximum of 3 paths. Theorem 2 was proved using the following five lemmas.

[Lemma 1] Let Fi be one of the output nodes F0 or F1 of the module, and let Ti be the output T0 or T1 of the corresponding logic tree. If the module is evaluated, Fi is not fixed to 0, and if one of the following (a) to (c) is true, the value of Fi is set to 1. (A) There is a conduction path from the ground node R to the output node Ti in the logic tree. (B) The output node Fi is fixed at 1. (C) The output node Fi slows down, and the condition (a) is true for the previous firing. In all other cases, the value of the output node Fi is set to 0 when the module is evaluated.

[Auxiliary Theorem 2] Considering the evaluation of a module of a DCVS circuit with no failure or 0 failure, if there is a conduction path from the ground node R to one Ti of the logic tree output, only upwards. There will be a path of movement.

This lemma is intuitive. If there is a conduction path that moves downward as well as upward, that conduction path must enter the differential pair at one of the drain outputs D0 or D1 and the other drain output D1 or D0.
So you have to get out of the same differential pair. Therefore, switches 26 and 28 must both be conducting. If there is no fault in the circuit, G0 becomes the complement of G1 and the switch 26
Only one of and 28 conducts. In the case of a zero fault only, the zero fault is manifested by the non-conducting state of both switches 26 and 28. The conduction path can change from downward to upward only if there is one fault.

[Lemma 3] Consider the evaluation of a module of a DCVS circuit with no failure or one failure. For any internal node of the logic tree 10 there is a conduction path from there to a tree output Ti (either T0 or T1). This conduction path moves upward.

[Auxiliary Theorem 4] 1 Consider the module evaluation of a faulty circuit. If there is a conduction path from the ground node R to the tree output T0 or T1, then there is a conduction path that moves only upward-downward-upward.

Lemma 4 is important because even in a faulty circuit, a wrong conducting path can be replaced by a path consisting of three unidirectional dependent paths. With the proper interconnection between the paths, all necessary combinations of dependent paths can be found in the logical tree 10.
Can be modeled by three passes through.
It does not matter if there is an additional parallel conducting path with a large number of kinks between the dependent paths moving up and down. This is because a kink has two tributary paths and a conduction path provides a tree output state.

[Auxiliary Theorem 5] Consider the evaluation of the module of a DCVS circuit with one failure.
When there is a conduction path from the ground node R to one tree output Ti, there is a conduction path that only moves upward-downward-upward. Further, this connecting path can be selected so that the end point of the last upward movement dependent path becomes the tree output.

Since the lemma 3 guarantees that there is a conduction path from any internal node in the logic tree to the tree output, the first turn of the upper-lower-upper conduction path is given to this tree output. Can be moved upwards toward.

According to the present invention, as is clear from the above theorem, DC
In the VS circuit, in the case of no failure or only 0 failure, it is possible to evaluate by passing the logic tree of the switch level display upward once from the ground node R to the tree outputs T0 and T1, On the other hand, in the case of only one failure, the evaluation can be performed by following three paths in the logical tree: upward (upward), downward (downward), and upward (upward). Therefore, as seen in FIG. 7, each switch differential pair 24 in the switch level logic tree is whether each differential pair is a circuit corresponding to the first path, the second path or the third path. Accordingly, the first, second or third Boolean type differential pair circuits 40, 42 or 44 are equally replaced. The first path is an upward path for evaluating the open / closed state of the conductive path from the ground node R to the logic tree outputs T0 and T1, and the switches 26 and 28 are ANDed, respectively.
Replaced by gates 46 and 48. The interconnection between the Boolean circuits belonging to the first path is that the interconnection is between adjacent upper and lower differential pairs in the same logic tree, or the interconnection is for a major net of primary inputs. Or other adjacent logical tree output
Identical to the interconnection between switch-level differential pairs 24, whether to the interconnection between the trees from T0 or T1. For example, in a switch-level DCVS circuit, suppose that a major net G0 or G1 is connected by an output node F0 or F1 of another logic tree 10 G0 or G1 will be driven by the same output node F0 or F1 as other logic trees.

Second path is downward, switch level circuit
24 has been replaced by Boolean differential pair 42. Since the conduction path is downward, the drains D0 # 2 and D1 # 1 are switched.
It is an input to AND gates 50 and 52 corresponding to 26 and 28. The outputs of AND gates 50 and 52 are combined in an OR gate 54 whose output S # 2 is a switch level differential pair.
Corresponds to 24 source inputs S.

Also in this case, the drains D0 # 2 and D1 # 2 and the source S
The cross coupling of # 2 is the same as the cross coupling of the switch level differential pair 24 to the drains D0 and D1 and the source S. However, the output of OR gate 54 is separately routed to the corresponding third pass Boolean circuit 44. This additional connection is necessary because the downward dependent paths of the upper-lower-upper conducting paths do not necessarily have to extend to the ground node R.

The Boolean circuit 44 for the third pass is similar to the Boolean representation 40 of the first pass. Switches 26 and 28 are AN
Replaced by D-gates 56 and 58. However, the source input S # 3 is combined at the OR gate 60 with the output of the OR gate 54 of the second pass Boolean circuit 42. As mentioned above, this additional interconnection is necessary to allow a downward to upward transition in the internal nodes of the logical tree 10.

The interconnection between the three paths is shown in FIG. Only the modeling of a single switch 26 or 28 is shown. All switches 26 and 28 of logic tree 10 are provided with similar AND and OR gates. There are Boolean trees 70, 72 and 74 for the first, second and third passes, respectively. Ground node R # 1 of the first pass Boolean tree 70
The inputs to are connected to the corresponding Boolean outputs T0 # 2 and T1 # 2 of the second path, which in this case are used as logic inputs. The second path ground node R # 2 is the output of the Boolean tree 72 and is used as the logic input to the OR gate 60 of the lowest level differential pair 44 of the third path Boolean tree 74. The other input to this OR gate 60 is the Boolean ground node R # 3, which is set to 0, similar to R # 1. In addition, OR gates 54 and 60 provide independent interaction between the second pass Boolean tree 72 and the third pass Boolean tree 74 for each switch 26 and 28 of the modeled switch level logic tree 10. Have a connection. Tree outputs T0 # 3 and T1 # 3 have two fault inserters (FI)
It is connected by 32 to the buffer and precharge model 30.

It should be noted that if the input of the magazine net is one failure, then a three-pass model is required even if the failure is not in the logic tree.

If the modeled switch 26 or 28 is gated by a major net Gi, then the fault inserter 76 is the major net Gi and the corresponding AND gates of the Boolean trees 70, 72 and 74 of all three paths. Placed between the input and. The fault inserter 76 has 0 fault or 1
So you can enter a breakdown. Magi Net Gi
Is controlling a plurality of switches 26 and 28 of different differential pairs, an additional fault inserter 78 is included to simulate these additional switch faults. The failure, even if so introduced into the manager net Gi, is not the failure of the manager net, but the failure of the controlled switch.

The model shown in FIG. 8 is for a single switch level logic tree 10 and its associated buffer and precharge circuit 12. As shown in FIG. 2, when there are a plurality of logical trees 10, each logical tree 10 is modeled by the corresponding structure of FIG. The interconnection of FIG. 2 is reproduced between the Boolean output nodes F0 and F1 of FIG. 8 and the manager net Gi.

Interconnects within a Boolean logic tree need to take into account the bidirectional nature of dot joins. Dot coupling is modeled by a combination of OR gates and fan-outs (driving multiple inputs with one output). This example will be described later.

Examination of Figures 7 and 8 reveals why the polarity of the signal at the Boolean tree output differs from the polarity of the signal at the switch level tree output. First, the polarities of the major nets G0 and G1 and the output nodes F0 and F1.
Assume that the polarity of is the same for the switch level display and the Boolean display. That is, the true value is 1 and the false value is 0. At both the switch level and the Boolean level, one of the major nets closes the n channel switch or AND gate it controls. However, the ground node R at the switch level is 0
While at the Boolean level ground node R # 1
And R # 3 is set to 1 or true. as a result,
A closed switch at the switch level causes the corresponding tree output T0 or T1 to go to 0, while a conditioned AND gate at the Boolean level causes the corresponding tree output T0 # 3 or T1 # 3 to go to 1. The same goes for the first pass Boolean tree 70
Also applies to outputs T0 # 1 and T1 # 1. Therefore, the buffer and precharge model 30 does not require a Boolean inverter. The full Boolean model is NAND
Complementary Boolean logic using AND gates can be similarly implemented.

E-4. Boolean display of the circuit The above model is the switch level logic tree 10 in FIG.
Applied to the resulting Boolean
The model is shown in FIG. Fault inserter 76 for inserting a fault into Mejiya-the net G0 ₂ is shown only one. Only one fault inserter is on for a single fault model, but
It should be appreciated that the net has a similar fault inserter 76. In the model of FIG. 1, OR gate 80 is used for upward dot coupling or fan-in (driving one input with multiple outputs), while OR gate 54 is used for downward dot coupling. in use. If the fault inserter 76 inserts 0 faults, then the second and third passes are no longer needed, so it is possible to connect the buffer and precharge, model 30, directly to the outputs T0 # 1 and T1 # 1 of the first pass Boolean tree. it can.

According to Theorem 1, a 0 fault at the input to the logic tree cannot cause a 1 fault at the output of the logic tree. As a result, the major nets of the faulty circuit are not both 1, and the 3-pass model is unnecessary. Similarly, if a 0 fault is so injected into the buffer and precharge model 30 by the fault inserter 32, only a one-pass Boolean logic tree 70 is needed. However, if the fault inserter inserts one fault, this fault inserter 32
Every other input of the logic tree connected to is 1 fault. As a result, a 3-pass model is required.

Since some AND and OR gates have one fixed input (logic 1), the model of FIG. 1 can be simplified slightly. However, these gates are left out to show the logical structure of the model. The Boolean model is shown here as a wiring diagram between various AND and OR gates. The model can also be tested with physical logic gates,
It is also possible to perform simulation with a computer by using a Boolean operation. The present invention extends to computer simulation. In the case of computer simulation, the attached drawing is regarded as a Boolean graphic representation. AND gates and OR gates indicate Boolean AND and OR operations, and cross-coupling indicates which calculation output is used as input for another Boolean calculation. In Boolean operations, 0 is a false value and 1 is a true value. Boolean Level Failure Simulation's Computer Program is the 17th Annual Meeting of the Design Automation Conference (ACM Order No. 477800) pages 374-380 held on June 23, 24 and 25, 1980 in Minneapolis, Minnesota. (17th Design A
utomation Conference Proceedings, Mineapolis, Minnes
ota, June23, 24, 25, 1980 (ACM Order No.477800) pp.
374-380) "High Speed Fault Simulation wi
th Vectors and Scalars) "by E. Ulrihi
ch) Explained by others.

F. Effect of the Invention According to the present invention, a circuit including a MOS switch can be easily and accurately simulated using a series of Boolean gates (AND, OR, etc.).

[Brief description of drawings]

FIG. 1 shows an example in which the switch level circuit display of FIG. 3 is replaced with a Boolean display according to the present invention, and FIG. 2 is a DC.
FIG. 3 is a diagram showing an outline of a VS circuit, FIG. 3 is a diagram showing an outline of a logic tree in a DCVS circuit and associated buffer and precharge circuits, FIG. 4 is a diagram showing an example of a DCVS logic tree, and FIG. 5 is a differential diagram. FIG. 6 is a schematic diagram of a pair, FIG. 6 is a diagram showing a buffer and precharge circuit of a Boolean model according to the present invention, FIG. 7 is a diagram showing a differential pair of the Boolean model according to the present invention, and FIG. FIG. 8 is a diagram showing the interconnection of the Boolean models of FIGS.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Berry Cummin Rosen Pour Botux 398, Stormville, New York, USA, Bruberi Lane (no address) (72) Inventor Gearbriel Mauricio Silverman United States 163 Orchyard Road, 1pt Abt, Briarcliff, New York

Claims (1)

[Claims] 1. A first switch (26) in which two or more logic trees each comprising a switch level circuit representation are arranged in parallel.
And a plurality of layers of a switch differential pair series arrangement including a second switch (28), each first switch having a first switch input (S) and a first switch output (D0), and each of the second switches. The switch has a second switch input (S) and a second switch input.
A switch output (D1), the first switch input and the second switch input of the same switch differential pair are connected to a common switch point (S), each common switch point being at least one lower layer switch It is connected to one output (D0, D1) or reference potential point (R) of the differential pair, and each switch output (D0, D1) is a switch differential pair common switch point (S) or switch tree output of the upper hierarchy. (T0, T1), each first switch and each second switch of each switch differential pair is a complementary first major net (G0
i) and the second major net (G1i) respectively, the major net being a temporary input (PI1
i, PI0i) or another switch tree tree output (T0, T1) connected to the switch level circuit display logic tree (1
0) into a Boolean logic tree, said switch differential pair (26,28) being replaced by a first AND gate pair (46,48) and said switch difference pair (26,28). When there is a dot bond between multiple layers of the moving pair (26, 28), the dot bond is replaced with an OR gate (80),
The first of the AND gates of the first AND gate pair (46, 48)
A common switch point (S) is connected to the logic inputs, and a second logic input of each AND gate of the first AND gate pair (46, 48) has first and second major nets (G0i) and A first Boolean display logic tree section (40,70) to which (G1i) is connected, and b. The switch differential pair (26,28) in the opposite direction to the first Boolean display logic tree section. , A second AND gate pair (50, 52), and the second AND gate pair (50, 5).
2) is replaced by a first OR gate (54) to which a pair of outputs are input, and each AN of the second AND gate pair (50, 52)
The first logic input of the D gate corresponds to the tree output pair of the logic tree (10) of the switch level circuit display (T0 # 2, T1 #
2) or another switch differential pair provided to replace the output of a first OR gate (54) provided by the replacement, and a second logic of each AND gate of the second AND gate pair (50, 52). A second Boolean logic tree section (42,72) to which inputs are connected first and second major nets (G0i) and (G1i), and c. Said switch differential pair (26,28) Are replaced by a third AND gate pair (56,58) and a second OR gate (60) in the same direction as the first Boolean logic tree section, and the switch differential pair (26,28). ), If there is a dot bond between multiple layers, the dot bond is OR
A gate (80), and the output of a second OR gate (60) is connected to the first logic input of each AND gate of the third AND gate pair (56, 58), First and second major nets (G0i) and (G1i) are connected to the second logic input of each AND gate of the gate pair (56, 58), and the first and second major gates (G1i) of the second OR gate (60) are connected. A third Boolean display logic tree section (44,74) to which a common switch point (S) is connected to the logic input, and a Boolean display logic tree consisting of Replacing the first and second sections (7
0,72) between two points (T0 # 1-T1 # 1, corresponding to the tree output pair (T0-T1) of the logic tree (10) of the switch circuit display.
T0 # 2-T1 # 2) and interconnect between the second and third sections (72, 74) at points corresponding to the reference potential points (R) of the respective sections. And applying the output of the first OR gate (54) to the second input of the second OR gate (60). How to convert to a logical tree.