JPH086988A - Cad system for manufacturing semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a CAD system for semiconductor device and a timing analysis method which surely eliminate false path by utilizing a static timing analysis means. CONSTITUTION:This CAD system for manufacturing semiconductor device is provided with a static timing analysis means A for outputting a critical path candidate and the combination column of the input signal corresponding to the candidate in the route from the input signal to an output signal by the connection information of the transistor of a sequential circuit or a combination circuit, a timing simulator B for performing a simulation by the combination column of the input signal and a comparison means C for comparing the critical path candidate outputted from the static timing analysis means and the result outputted from the timing simulator. In the display of the CAD system, the critical path candidate to be the output of the static timing analysis means A, the combination column of the input signal corresponding to this candidate and the decision result of the comparison of the both of them are accurately decided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing CA.
The present invention relates to a D device, and more particularly to a static timing analysis means for searching a critical path of a circuit from connection information of transistors.

[0002]

2. Description of the Related Art Today, the number of integrated transistors in semiconductor devices such as LSIs has increased dramatically, and system LSIs represented by microprocessors in particular have increased in circuit complexity. Further, in today's semiconductor devices, a CAD device for semiconductor device manufacturing is indispensable in order to improve the circuit performance and shorten the design period. One of them is the critical path of the circuit based on the circuit connection information of the transistor. PathMill; Epic De
A static timing analysis means such as sign Technology Inc.) has been proposed. This static timing analysis means is an example of combination of input signals (hereinafter,
It has become popular rapidly in recent years because it does not require a test vector) and its execution period is fast. As static timing analysis means, there have been proposed ones that perform analysis at various levels such as those that perform analysis at the gate level such as inverters and NAND, and those that perform analysis at the transistor level, and various path search algorithms are also proposed. Has been done.

Various algorithms of static timing analysis means for performing analysis at the transistor level have been proposed, and one example is shown below. The static timing analysis means searches for the path having the largest delay from the input signal to the output signal, based on the connection information of the transistors. The method pays attention to one input signal, first performs a path search assuming that the input signal changes from high to low, and then performs a path search assuming that it changes from low to high. It seeks the longest path. Then, the same operation is performed for each of the other input signals to find the critical path of the circuit. The path search method is performed by repeating the assumption and verification of the signal flow and following the signal transmission.

Here, the narrowing down of the signal direction of the transistor will be described. Although the MOS transistor is a 4-terminal element, the static timing analysis means considers it as a 3-terminal element excluding the substrate terminal. Here, the NMO shown in FIG.
In the S transistor, if the gate terminal G is given a logical value positive (power supply terminal), the drain terminal D is a logical value positive (power supply terminal) and the source terminal S is grounded, the current I is NM.
The current flows from the drain terminal D of the OS transistor to the source terminal S. This is defined as a low signal transmitted from the source terminal S to the drain terminal D as shown in FIG. Further, when the potential of the gate terminal G is unknown, it can be seen that if the drain terminal D has a positive logic value (power supply terminal), the gate terminal must have a positive logic value in order for current to flow through the NMOS transistor. This is defined as a high signal transmitted from the drain terminal to the gate terminal as shown in FIG.
The PMOS transistor can be similarly defined.

With the above definition, the voltage at each terminal of the transistor can be estimated. For example, if the MOS transistors are connected in series as shown in FIG.
When the gate terminal of the MOS transistor N1 is high, N
Only when the gate terminal of the MOS transistor N2 is high, a low signal is transmitted to the terminal OUT as shown by an arrow (↑). Similarly, as shown in FIG. 4, when the PMOS transistors are connected in series, the high signal is output only when the gate terminal of the PMOS transistor P1 is low and when the gate terminal of the PMOS transistor P2 is low. ) Is transmitted to the terminal OUT. This consideration is NAN
It is used to estimate the voltage of the input signal of the D gate and the NOR gate.

Next, an example of the conventional static timing analysis for analyzing the combinational circuit shown in FIG. 5 will be described. This combinational circuit uses input signals INA, INB, I
A NAND circuit, a NOR circuit, and inverters INV1 and INV2 are connected between the NC and the output signals OUT1 and OUT2, and these circuits are PMOS transistors 1 and
3, 4, 7, 9, 10 and NMOS transistor 2,
It is composed of 5, 6, 8, 11, and 12. First, the analysis is started when the input signal INB changes from high to low. At this time, the node X changes from low to high. At this time, the input signal INA must be high in order for signal propagation to occur, that is, for the node Y to change from high to low. Further, assuming that the output signal OUT2 is low, that is, the input signal INC is high, the output signal OUT1 changes from low to high.

In this way, an assumption is made as to whether a certain node is high or low due to the signal propagation, and the assumption is verified. The verification is repeated until an input signal other than the input signal of current interest, all output signals, or the ground terminal and the power supply terminal are encountered, and the assumption is supported if there is no contradiction. In this way, the path analysis is performed focusing on a certain input signal, and the longest path from the input signal to the output signal is searched for. The circuit delay at this time can be approximated by the sum of the products of the equivalent resistance of the transistor during pentode operation and the parasitic capacitance (sum of junction capacitance and gate capacitance) associated with the node. Similarly, input signal INB
Changes from low to high and the input signals INA and I
The same path search is performed for the NC, and the circuit delay is calculated. Table 1 shows the results arranged in order from the largest circuit delay.

[0008]

[Table 1]

In this way, the static timing analysis means outputs candidate routes of critical paths in the circuit in descending order of delay. H indicates High, L
Indicates Low (the same applies hereinafter). Actually, when the path search is performed, the longest route is searched while considering the RC delay product of each node, but in this case, the longest route is simply the case where the number of gates is large. However, in the conventional static timing analysis means, a candidate route of a circuit critical path and a test vector for confirming the delay at that time can only be formed by human hands. Using this test vector, timing simulation and SPICE (Simulation Program with Integra
ted Circuit Emphasis). That is,
Static timing analysis is performed on the circuit of FIG. 5 described above, and a test vector is generated based on the result.

Next, in the critical path candidates obtained by the static timing analysis means,
An example including a path that is impossible in circuit operation will be shown. The static timing analysis means analyzes the combinational circuit including the pass transistor shown in FIG. This combinational circuit includes input signals INA, INB, INC and an output signal OU.
NAND circuit, transmission gate 1, and T1 and OUT2
The inverter 1, the inverter 2, and the inverter INV are connected, and these circuits are connected to the PMOS transistor 1
3, 15, 17, 18, 21, 23 and NMOS transistors 14, 16, 19, 20, 22, 24. Analysis is performed when the input signal INB changes from low to high. Assuming that the input signal INC is high, the node P changes from high to low.
Further, the input signal INC passes through the inverter 1 and the node Q changes from low to high. At this time, the transmission gate 1 is turned on. Here, as shown in the figure, the direction in which the transmission gate 1 transmits a signal is from the node R to the output signal OUT2.

However, the static timing analysis means does not determine the signal propagation direction of the transmission gate 1 and outputs the path with the longest delay in connection of the circuit as a critical path candidate. Assuming that the node R changes from high to low after the transmission gate 1 is turned on, that signal is output via the inverter 2 and its output signal OU
Suppose T1 changes from low to high. At this time, the input signal INA becomes low. This is because, when verifying that the node R changes from high to low, only the signal (potential) before the change of the node R is focused and the hypothetical verification is performed. As described above, the above route is determined as a critical path candidate. The circuit delay at this time can also be approximated by the sum of the products of the equivalent resistance of the transistor during pentode operation and the parasitic capacitance (sum of junction capacitance and gate capacitance) associated with the node. Similarly, for other input signals, the path analysis is performed for the case of changing from low to high and the case of changing from high to low, and the results are summarized in Table 2.

[0012]

[Table 2]

As shown in Table 2, the result obtained by the static timing analysis may include a path (false path) which is not possible in circuit operation. In order to confirm whether this output result is a false path or an actually possible path, timing simulation may be performed by a test vector created by a human, or transient analysis of the circuit may be performed by SPICE. Next, an example in which a sequential circuit is analyzed by static timing analysis means will be shown.
FIG. 7 shows a D-type master-slave flip-flop (hereinafter,
It is a sequential circuit including a D-FF). D-FF in the figure
The circuit except for is the combinational circuit shown in FIG. 5, and the path search of this portion is performed in exactly the same manner as described above. The sequential circuit includes a NAND circuit, a NOR circuit, and inverters INV1 and INV between the input signals INA, INB and INC and the clock signal CLOCK and the output signals OUT1 and OUT2.
V2 and D-FF1 to 5 are connected, and these circuits are connected to PMOS transistors 1, 3, 4, 7, 9, 10.
And NMOS transistors 2, 5, 6, 8, 11, 12
It consists of

D-FFs 1 to 5 in the figure are composed of a circuit as shown in FIG. The D-FF is configured by wiring a NAND circuit and an inverter INV. Although the circuit operation of the D-FF will not be described in detail, the master flip-flop (hereinafter abbreviated as M-FF) and the slave flip-flop (hereinafter abbreviated as S-FF) shown in FIG. It is a flip-flop that moves in synchronization. This circuit has an input signal D, output signals Q, QN and a clock signal input. When the clock signal changes from high to low, the value of D immediately before that changes to the new Q value.
Is stored as the value of. The static timing analysis of the sequential circuit finds the maximum delay between D-FFs to satisfy the maximum clock frequency of the system. In the circuit of FIG. 7, analysis is performed assuming that the node CLKI (inverted signal of the clock signal) in the D-FF2 changes from low to high. When the node C in FIG. 8 is set low, the complementary signals are output to the nodes C and D, so that the node D is high. At this time, the node F changes from high to low,
Further, the node QN changes from low to high, and the node Q changes from high to low.

That is, the node Q2 in FIG. 7 changes from high to low. Here, the analysis is performed in the same manner as the previous conventional example. That is, an assumption is made as to whether a node is high or low due to signal propagation, and the assumption is verified. The verification is repeated until an input signal other than the input signal of current interest, all output signals, or the ground terminal and the power supply terminal are encountered, and the assumption is supported if there is no contradiction. In the case of a sequential circuit, when this verification is performed, the verification is aborted even when the clock signal and its invert signal reach the source terminal or the drain terminal of the transistor input to the gate terminal. In this way, static timing analysis can be performed in the sequential circuit as in the combinational circuit. This time,
In the sequential circuit as well as in the combinational circuit, the circuit delay can be calculated from the RC delay product of the on resistance of the transistor and the parasitic capacitance. A static timing analysis is performed on the circuit of FIG. 7 and the circuits arranged in descending order of circuit delay are shown in Table 3.

[0016]

[Table 3]

[0017]

However, in the conventional static timing analysis means, it was not possible to automatically generate a test vector for confirming a route of a critical path candidate in the circuit and a delay at that time. . Timing simulation and SPICE (circuit transient analysis) can be performed using this test vector, and timing verification with a clock signal can also be performed using a test vector in a sequential circuit. It was not possible to automatically confirm whether the result obtained by the means is a path that is not possible in the circuit operation (false path) or a path that is actually possible. Conventionally, when a human creates a test vector while looking at a circuit diagram on paper and compares it with a candidate route of a circuit critical path formed by the static timing analysis means, and discovers a false path from the candidates. Was excluding this. However, as the circuit becomes more complicated, it becomes difficult to find the false path manually. The present invention has been made under such circumstances, and an object of the present invention is to provide a CAD device for manufacturing a semiconductor device and a timing analysis method capable of effectively removing a false path by using static timing analysis means. .

[0018]

According to a CAD device for manufacturing a semiconductor device of the present invention, a candidate for a critical path and a corresponding input signal in a path from an input signal to an output signal according to connection information of transistors of a sequential circuit or a combinational circuit. Static timing analysis means for outputting a combination sequence of, a timing simulator for performing simulation by the combination sequence of the input signals, a candidate for a critical path output from the static timing analysis means and a result output from the timing simulator. And a comparison means for comparing This CAD device for semiconductor device manufacturing is provided with a display, on which the candidate of the critical path, the output of the timing simulator, and the determination result obtained by comparing the both are displayed together. You may

Further, in the method for manufacturing a semiconductor device using the timing analysis method of the present invention, the static timing analysis means uses the connection information of the transistors of the sequential circuit or the combinational circuit to determine the candidate of a critical path in the path from the input signal to the output signal. And a step of outputting a combination sequence of the input signals corresponding thereto, a step of simulating the combination sequence of the input signals, and a step of comparing the result of simulating the combination sequence of the input path and the candidate of the critical path. The first feature is that and are used. Further, the static timing analysis means outputs a combination path of a critical path candidate and a corresponding input signal in the path of the input signal from the input signal according to the connection information of the transistors of the sequential circuit or the combination circuit; A second feature is that a step of performing a simulation by a combination sequence and a step of extracting a false path that is impossible in circuit operation from a result of simulating a combination sequence of the critical path candidate and the input signal are used. . The timing analysis method is for manufacturing a semiconductor device having a display.
An AD device may be provided, and the false path may be displayed on this display, and its output waveform may be displayed on this display. Further, the circuit including the sequential circuit may be divided into a plurality of sections, and the static timing analysis may be performed for each section.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of designing an integrated circuit having a predetermined structure and function,
A mask forming step of forming various patterns such as a wiring pattern on a wafer forming a semiconductor substrate on which the integrated circuit is provided based on this design, a wafer forming step of forming the semiconductor substrate, and a diffusion region on the wafer, A wafer processing step of forming an oxide film, a thin film, etc., a step of dicing the wafer to form the semiconductor substrate, packaging the semiconductor substrate to form a semiconductor device, and a step of inspecting the semiconductor device. In the step of designing the integrated circuit, a false path of the sequential circuit or combinational circuit included in the integrated circuit is extracted and eliminated by using the semiconductor device manufacturing CAD device according to claim 1. From the static timing analysis result that does not include the false path, the integrated circuit having the predetermined structure and function can be obtained. It is characterized in that the total.

[0021]

The static timing analysis means of the semiconductor device manufacturing CAD device outputs a critical path candidate in the path of the input signal to the output signal according to the connection information of the transistors of the sequential circuit or the combinational circuit, and the corresponding input signal. Since the combination string of is output, the false path included in the circuit can be accurately removed by utilizing this. Further, the display of the CAD device for manufacturing a semiconductor device shows the combination of the critical path candidates output from the static timing analysis means and the corresponding input signal combination and the judgment result obtained by comparing the both, so that it is quick and accurate. A decision is made. Moreover, since the focal path is automatically extracted, the degree of automation of the design process in the manufacturing process of the semiconductor device is improved.

[0022]

The present invention will be described below with reference to examples. First, a first embodiment will be described with reference to FIGS.
FIG. 5 is a circuit diagram of a combinational circuit, and FIG. 9 is a waveform diagram of each node when timing simulation is performed.
As described in the above-mentioned conventional example, Table 1 shows the result of analysis of the circuit of FIG. 5 by the static timing analysis means. At this time, a test vector can be generated corresponding to a candidate of a critical path. . For example, the path of I in Table 1 is the input signal INB as described in the conventional example.
Changes from high to low, INA is high and INC is also high. Further, it is defined as high when the input signal is X (may be high or low). In this way, test vectors can be generated for all the paths in Table 1. Table 4 shows other input signals of the path I in Table 1.

Further, timing simulation is performed in the circuit of FIG. 5 using the test vector of path I in Table 4.
FIG. 9 shows the movement of each node at that time. Then, when the movement of each node of the path I shown in Table 1 obtained by the static timing analysis means is compared with the movement of each node in FIG. 9, it is understood that these two have exactly the same logic. . From this, it can be seen that the path I in Table 1, which is the result obtained by the static timing analysis means, is appropriate. The results of the above static timing analysis means and timing simulator are also shown in Table 4. Similarly, it is possible to execute the paths II and III in Table 1 and other paths. Next, FIG. 6 and FIG.
The second embodiment will be described with reference to FIG. FIG. 6 is a circuit diagram of a combinational circuit, and FIG. 10 is a waveform diagram of each node when timing simulation is performed. The circuit shown in FIG. 6 is analyzed by static timing analysis means,
The obtained results are shown in Table 2. As described above, the path I in Table 2 is a path that is not possible in terms of circuit operation (false path).
Is.

[0024]

[Table 4]

Also in this case, the test vector can be generated in the same manner as in Table 4, and the results are summarized in Table 5. Timing simulation of the circuit of FIG. 6 is performed using the test vector of path I in Table 5. The movement of each node at this time is shown in FIG. Comparing the movement of each node in the path I shown in Table 2 showing the result obtained by the static timing analysis means with the movement of each node in FIG. 10, it is apparent that the two movements are different. The above results are also shown in Table 5. From this, it can be seen that the path I in Table 2 obtained by the static timing analysis means is a false path. Similarly, it is possible to execute the paths II and III in Table 2 and other paths. Of course, also in the circuit of FIG. 6, a correct path in circuit operation can be obtained from the analysis result of the static timing analysis means. Therefore, it is possible to obtain a proper path by removing the false paths using the above method and again arranging the paths in descending order of circuit delay.

[0026]

[Table 5]

Next, a third embodiment will be described with reference to FIGS. 7, 8, 11, 12, and 13. 7 is a circuit diagram of the sequential circuit, and FIG. 8 is a D-F used in the sequential circuit of FIG.
FIG. 11 is a circuit diagram of F, and FIG. 11 is a waveform diagram of input / output signals of D-FF.
FIG. 12 is a waveform diagram of a test vector in the circuit of FIG.
FIG. 13 is a waveform diagram of each node when the timing simulation is performed. In this embodiment, a method for generating a test vector in a sequential circuit will be described. Figure 7
A static timing analysis is performed on the circuit shown in FIG. 3 and each node is arranged in Table 3 in the order of large circuit delay. Here, the output signal Q and the input signal D in the D-FF shown in FIG. 8 will be described as a function of time. Although many logic circuits include flip-flops, a signal having a constant cycle is often used as a clock signal common to them.
That is, the value of the output signal Q does not change for one cycle after the clock signal (CLOCK) changes from high to low.

Therefore, as shown in FIG. 11, the time (t) is divided into sections of finite width, each section is given an integer number, and the time t is represented by the number. When the time is divided and displayed in this way, the operation of the D-FF is as in the following expression (1). Q (t + 1) = D (t) (1) By expressing in this way, a test vector can be created. From the path I in Table 3, Q2 changes from high to low at time t + 1, so D2, that is, INB, is t.
It turns out that it is only necessary to change from high to low at the time of.
Here, Q1 is high at time t + 1, and Q3 is also t + 1.
D1 or INA is high at the time t, and D3 or INC is high at the time t as well. FIG. 12 shows this test vector. FIG. 13 shows the movement of each node when timing simulation is performed in the circuit of FIG. 7 using this test vector. When the movement of each node of path I in Table 3 showing the result obtained by the static timing analysis means is compared with the movement of each node in FIG. 13, it can be seen that the two have exactly the same logic. From this, it can be seen that the path I in Table 3 showing the result obtained by the static timing analysis means is appropriate. The above results are shown together in Table 6.

Similarly, other paths can be executed. As described above, by using the method of this embodiment, the test vector can be created even in the sequential circuit. Next, the timing analysis method of the present invention will be described with reference to the flowchart shown in FIG. As described above, the static timing analysis means performs the timing analysis by searching the path having the largest delay from the input signal to the output signal based on the connection information of the transistors. The method focuses on one input signal, first performs a path search assuming that the input signal changes from high to low, and then performs a path search assuming that the input signal changes from low to high, and searches for the longest possible path. It is a thing. Then, the same operation is performed for each of the other input signals to find the critical path of the circuit. The path search method is performed by repeating the assumption and verification of the signal flow and following the signal transmission.

[0030]

[Table 6]

The present invention is characterized in that the static timing analysis means outputs a test vector. In the timing analysis, a false path is determined from the circuit-critical path candidates output by the static timing analysis means and removed from the candidates. It is characterized by performing automatically. CAD device for semiconductor device manufacturing (1) Input the circuit description file and setting file,
(2) Timing analysis of a predetermined circuit is performed by the static timing analysis means, (3) a critical path candidate is output, and (4) a test vector for confirming the delay of this candidate is output. next,
(5) Timing simulation is performed using this test vector, and (6) the result is output. Then, (7) the candidate for the critical path is compared with the result of the timing simulation, and (8) the judgment result obtained by comparing both is output. If they do not match as a result of the determination, the compared critical path candidate is a false path and is excluded from the critical path candidates. Note that the present invention can be performed in the same manner for all semiconductor device manufacturing CAD devices that perform static timing analysis without depending on the algorithm of path search as shown in the conventional example. Removing it gives a reasonable path.

FIG. 15 shows a CA for manufacturing a semiconductor device according to the present invention.
FIG. 15 is a schematic system configuration diagram of the D device, which includes static timing analysis means A, timing simulator B, and output result comparison means C shown in FIG. 14. In this tool, a keyboard, a display, a memory, an MPU (microprocessor unit) and a mouse are connected to each other via a system bus including a data bus and a control bus. The keyboard is provided with function keys for changing, deleting, inserting, moving, etc. of the data displayed on the screen of the display, in addition to the ordinary keys such as ten keys and alphabet keys. By inputting this keyboard, the circuit description file and the setting file are input. The display displays each data input from the keyboard. The test vector output from the static timing analysis means and the state of each node of each circuit to be analyzed when timing simulation is performed are displayed as voltage waveforms. Further, as shown in Table 6 and the like, the comparison means C also writes the path analysis result output of the static timing analysis means and the timing simulation result output together, determines the comparison result of both, and displays it on the same screen. The memory stores various data input from the keyboard in addition to a program representing the processing performed by the MPU.
The MPU executes a predetermined process based on the program stored in the memory, temporarily stores each data input from the keyboard in the memory, and displays the data on the display. The mouse specifies the position on the screen of the display unit based on the manual operation.

Next, a method of manufacturing a semiconductor device using the CAD device for manufacturing a semiconductor device of the present invention will be described with reference to FIG. For a semiconductor device such as an integrated circuit, first, an integrated circuit having a predetermined structure and function is designed (design step a). Based on the design, a mask for forming various patterns such as a wiring pattern is formed on a wafer on which a semiconductor substrate on which an integrated circuit is formed is formed (mask forming step b). Further, a semiconductor wafer for forming a semiconductor substrate is formed (wafer manufacturing step c). Next, the semiconductor wafer is subjected to diffusion treatment, oxidation treatment, thin film formation, etc. (wafer treatment step d). Next, the wafer is diced to form a semiconductor substrate, which is then packaged (assembly step e). Next, the assembled semiconductor device is inspected (inspection step f). The semiconductor device is commercialized through such steps.

In the design process, a circuit / logic design and a layout design are performed. After these designs, the contents are analyzed and it is verified whether or not a predetermined specification is satisfied. If the design is flawed, it will be modified many times until the specified specifications are satisfied. Although there are various kinds of analysis means and analysis contents, the static timing analysis means according to the present invention is used to verify whether the circuit delay of the circuit to be analyzed satisfies a predetermined specification. The static timing analyzing means outputs candidate paths of critical paths in the circuit in the order of increasing delay. In the present invention, a false path which is impossible in the circuit operation is extracted from this output by using the static timing analyzing means. Therefore, the degree of automation in the design process is improved, and the design period of a complicated circuit such as a system LSI can be shortened.

[0035]

As described above, the present invention outputs a critical path candidate from the input signal to the output signal path according to the connection information of the transistors of the sequential circuit or the combinational circuit, and the corresponding input signal combination string. Since this is output, the false path included in the circuit can be automatically removed by using this. As a result, the critical path can be found quickly and accurately from the predetermined circuit. Further, since a combination of a critical path candidate output from the static timing analysis means and a corresponding input signal combination sequence and a determination result obtained by comparing the two are written together on the display of the semiconductor device manufacturing CAD device, quick determination is possible. it can. Further, the degree of automation in the design process of the semiconductor device is improved, and the design period of a complicated circuit such as a system LSI can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 5 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating an embodiment of the present invention.

FIG. 9 is a waveform diagram of each node when the timing simulation of the present invention is performed.

FIG. 10 is a waveform diagram of each node when the timing simulation of the present invention is performed.

FIG. 11 is a waveform diagram of input / output signals of the D-FF of the present invention.

12 is a waveform diagram of a test vector in the circuit of FIG.

FIG. 13 is a waveform diagram of each node when the timing simulation of the present invention is performed.

FIG. 14 is a flowchart showing a timing analysis method of the present invention.

FIG. 15 is a schematic configuration diagram of a CAD device for manufacturing a semiconductor device of the present invention.

FIG. 16 is a flowchart of manufacturing steps of the semiconductor device of the present invention.

[Explanation of symbols]

1, 3, 4, 7, 9, 10, 13, 15, 17, 18,
21, 23 PMOS transistors 2, 5, 6, 8, 11, 12, 14, 16, 19, 2
0, 22, 24, 25 NMOS transistors

Claims (7)

[Claims] 1. A static timing analysis means for outputting a combination of a critical path candidate and a corresponding input signal in the path of an input signal to an output signal according to connection information of a transistor of a sequential circuit or a combination circuit, and the input signal. And a comparison means for comparing a candidate of a critical path output from the static timing analysis means with a result output from the timing simulator. CAD equipment for semiconductor device manufacturing. 2. The CAD device for manufacturing a semiconductor device according to claim 1, further comprising a display, and the display includes a candidate for the critical path, an output of the timing simulator, and a determination result obtained by comparing the two. A CAD device for manufacturing a semiconductor device, wherein and are also displayed. 3. The static timing analysis means outputs a combination of a candidate of a critical path and a corresponding input signal in the path of the input signal to the output signal according to the connection information of the transistors of the sequential circuit or the combination circuit, The timing analysis method is characterized by using a step of performing a simulation with the combination sequence of the input signals, and a step of comparing the candidate of the critical path and a result of simulating the combination sequence of the input signals. Manufacturing method of semiconductor device. 4. A step of outputting, by static timing analysis means, a combination of a critical path candidate and a corresponding input signal in a path from an input signal to an output signal according to connection information of transistors of a sequential circuit or a combination circuit, It is characterized by using a step of simulating the combination sequence of the input signals, and a step of extracting a false path that is impossible in circuit operation from a result of simulating the combination sequence of the critical path candidate and the input signal. A method for manufacturing a semiconductor device using a timing analysis method. 5. The timing analysis method uses a CAD device for manufacturing a semiconductor device having a display, wherein the false path is displayed on this display, and its output waveform is displayed on this display. A method of manufacturing a semiconductor device using the timing analysis method according to item 4. 6. A semiconductor using the timing analysis method according to claim 3, wherein a circuit including a sequential circuit is divided into a plurality of sections, and static timing analysis is performed for each section. Device manufacturing method. 7. A step of designing an integrated circuit having a predetermined structure and function, and based on this design, for forming various patterns such as a wiring pattern on a wafer forming a semiconductor substrate on which the integrated circuit is provided. A mask forming step used for forming a semiconductor substrate, a wafer forming step for forming the semiconductor substrate, a wafer processing step for forming a diffusion region, an oxide film, and a thin film on the wafer, and dicing the wafer to form the semiconductor substrate. The semiconductor device manufacturing CAD according to claim 1 or 2, further comprising: a step of packaging the semiconductor device to form a semiconductor device; and a step of inspecting the semiconductor device, wherein the integrated circuit is designed. A device is used to extract and eliminate false paths of the sequential circuit or combinational circuit included in the integrated circuit, A method for manufacturing a semiconductor device, characterized in that an integrated circuit having the predetermined structure and function is designed based on a static timing analysis result which is not included.