JPH0869413A - Page history memory device - Google Patents

Abstract

PURPOSE: To speed up page history memory access by a highly parallel multiprocessor system. CONSTITUTION: The highly parallel multiprocessor system wherein an MMU 1 and plural CPUs 2 are connected to a bidirectional bus 100 is provided with a page history memory 3 in the MMU 1 and page history memory caches (RCM cache) 6 in the respective CPUs 2. When an EPU 4 accesses the MMU 1, the MCU 5 of its system updates the RCM cache of the same system. When the EPU 4 makes a request to refer to page history information, its MCU 5 looks up its RCM cache and the request is outputted from a bus access part 53. An MCU 5 of another system, when receiving the request by the bus access part 53, locks up the RCM cache 6 and sends it out to the bus 100. The MCU 5 at the request source returns the OR of read data of all the RCM caches to the EPU 4 at the request source.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a page history memory device in a highly parallel multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, in this type of information processing system, as described in Japanese Patent Application Laid-Open No. 02-150939, when the system is composed of a plurality of systems, each system including a memory access processing device is provided separately. A configuration in which the page history memory is distributed and owned is used.

FIG. 8 is a block diagram showing an example of such a conventional page history memory device. The first information processing apparatus includes an arithmetic processing unit (EPU) 4r and an EPU 4
It includes a memory access processing unit (MCU) 5r that receives and processes a memory access request to the main memory unit r, and a main memory unit (MMU) 1r. A page history memory (RCM) 3r is connected to the MCU 5r.

[0004] The information processing apparatus of the second system has exactly the same configuration. Corresponding components are denoted by the same reference numerals with the addition of the subscript 's'. Main memory 1
Both r and 1s can be accessed from both the first and second systems. In such a configuration, the EPU4r
From MMU1r or 1s to MMU1r or 1s, M
The CU 5r accepts this, and according to the request, the MMU 1
Access r or 1s.

The RCM 3r is a memory that holds access information corresponding to each page of the MMU 1r and 1s, that is, a reference bit indicating that the page has been referred to and an update bit indicating that the page has been updated in page units. . When the MCU 5r receives the access request of the MMU 1r or 1s, the RCM 3r of its own system is updated. Similarly, in the system on the MCU 5s side, the M
MCU5s for access request of MU1r or 1s
Processes this and updates the RCM 3s.

In this case, since the memory access processing device of the other system does not know the memory access by the memory access processing device of the own system, the content of the page history memory of the own system corresponds to the request of the arithmetic processing device of the own system. The contents of the page history memories of both systems are different from each other.

When the memory access processing unit receives a memory access request from the arithmetic processing unit in order to avoid such data inconsistency between the page history memories, the page history memory of the own system is updated and the other system is updated. The own system memory access processing device instructs the other system memory access device to update the page history memory of the other system. As described above, the matching process of the distributed page history memories in the information processing system is performed.

[0008]

In the page history memory device having the conventional configuration, in an information processing system having a small number of systems, the consistency can be guaranteed by the above-described method, but the number of systems in the system increases. When it becomes highly parallel,
In the match assurance by such a method, the number of updates of the page history memory due to the access of the memory of the other system increases, and the update of the page history memory of the own system becomes impossible, so that the access of the memory of the own system is delayed. As a result, there is a disadvantage that the processing performance is reduced.

In a highly parallel multiprocessor system, a system configuration in which a central processing unit including an arithmetic processing unit and a memory access processing unit is provided as one system, and a plurality of central processing units and a main storage unit are connected by a bus is common. . In this system, the main storage device is a shared memory, and memory access is possible from all systems.

In such a configuration, the page history memory can be owned singly in the system or can be distributed and owned by each central processing unit. In the former case, however, the central processing unit This causes contention for access to the page history memory. In the latter case, it is necessary to guarantee the data agreement of the page history memories that are distributed and owned.

[0011]

An apparatus according to the present invention has a main storage device and a plurality of systems of central processing units, and information of a virtual storage system in which the main storage device and the central sled unit are bus-connected. The page history memory device in the processing system holds a part of the information of the page history memory that manages the information indicating whether the data in the main storage device is referenced and the information indicating whether the data is rewritten in page units. A page history memory cache is provided for each central processing unit, and at the time of updating the page history information by memory access, updating of the data in the page history memory cache in the central processing unit that is the request source of the memory access is performed. And means for reading the data in the page history memory cache when requesting page history information reference. Means, means for sending the page history information reference request to the bus by the central processing unit, means for receiving the page history information reference request on the bus by the central processing unit, and all of the page history information reference requests on the bus A means for generating page history information from the read data of the page history memory cache is provided.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1A shows a system block diagram of a first embodiment of the present invention. The system of this embodiment is a virtual memory highly parallel multiprocessor system in which one main memory (hereinafter, referred to as MMU) and a plurality of central processing units (hereinafter, referred to as CPU) are bus-connected.

Referring to FIG. 1A, the present system comprises:
The MMU 1 and the three CPUs 2a, 2b, 2c are all connected to the bidirectional bus 100, and a page history memory (hereinafter referred to as RCM) 3 is installed inside the MMU 1. The RCM 3 holds page-by-page access history information on the MMU 1, and the access history information indicates a reference bit (hereinafter, R bit) indicating whether or not a page has been referenced, and whether the page has been updated ( C bits).

The CPU 2a, which is a first system, includes an arithmetic processing unit (hereinafter, referred to as EPU) 4a, a memory access processing unit (hereinafter, referred to as MCU) 5a for processing memory access from the EPU 4a, and the contents of the RCM 3. And a page history memory cache (hereinafter, RCM cache) 6a for holding a part thereof.

The CPUs 2b and 2c of the second and third systems have exactly the same configuration.
b 'and' c 'are added. Hereinafter, the CPU 2a,
When generically referring to 2b, 2c, etc., they are referred to as CPU2, etc.

The CPU 2a has an MCU 5a and an EPU 4a.
When an access request to the MMU 1 is received from the server, a function of updating the RCM cache 6a of the own system is provided. When the MCU 5a receives a page history information update request (RC set request) corresponding to a certain page from the EPU 4a, the RCM 3 and all RCMs in the system receive the request.
A function to update the relevant entry in the cache
When U5a receives a page history information reference request (RC read request) corresponding to a certain page from EPU4a, the U5a reads the corresponding entries of all RCM caches in the system, and returns the result to EPU4a of the request source;
It has a function of reading out the contents of the RCM 3 in the MMU 1 to the requesting EPU 4a.

FIG. 1B is a block diagram of the MCU 5. The configuration of the MCU 5 will be described below with reference to FIG.

The MCU 5 has an interface with the EPU 4 through a request receiving section 51 and a reply control section 52, and a bus access section 53 can input / output requests and data to / from the bidirectional bus 100 via the connection line 101. The input / output direction of the bidirectional bus 100 is controlled by the bus input / output control circuit 102.

Upon receiving the RC read request, the request receiving unit 51 indexes the RCM cache 6. According to the index result, the RCM cache output control unit 54 outputs the read data of the cache as it is in the case of a cache hit, and outputs R = 0 and C = 0 as the read data of the RCM cache 6 in the case of a cache miss. . The output of the RCM cache output control unit 54 is transmitted to the reply control unit 52 or the bus access unit 53.

When the request receiving unit 51 receives the RC read request, the bus access unit 53 receives the request from the request receiving unit 51 and
An RC read request is issued to the bidirectional bus 100 in order to collect the data in the CM cache. Further, the bus access unit 53 responds to this request by the CP of another system.
When U sends the RCM cache read data to the bus, it collects these and sends them to the reply control unit 52.

The bus access unit 53 receives data from the RCM cache output control unit 54 because the request receiving unit 51 receives an RC read data request of another system from the bus access unit 53 and reads the RCM cache 6. The read data of the RCM cache 6 is sent to the bidirectional bus 10 toward the requesting CPU.
Sent to 0. The reply control unit 52 holds the read data of the own system RCM cache, and when the read data is returned from the other system via the bus access unit 53, a logical sum of the returned data and the held data is taken and the read result is obtained. Will be returned to EPU4.

FIG. 2 is an example of a timing chart showing the operation of the MCUs 5a, 5b, 5c. In FIG. 2, (a) to (e) show operations in the MCU 5a,
(F) to (R) show the operation inside the MCU 5b, and (N) to
(W) shows the operation in the MCU 5c.

FIG. 3 is a detailed block diagram of the MCU 5 for explaining FIG. The operation of the MCUs 5a, 5b, 5c will be described in detail below with reference to FIGS. 2 and 3.

At a timing T0, a request reception register (RQRR) 11a in the CPU 2a is stored in its own EP.
When the RC read request from U4a is accepted, the own system RCM cache 6a is read. If the cache is a mishit, the data '00' becomes the RCM cache read register (RCR
R) 12a and the data '00' is held in the reply data register (RPDR) 13a at timing T2.

At timing T1, RQRR11
a to other system request creation register (ARQS) 14a
The other system RC read request is set to and sent to the bidirectional bus 100. At the next timing T2, the RC read request on the bidirectional bus 100 is
2c Other system request reception register (ARQR) 15
b, 15c, RQRR at timing T3
11b and 11c are set. RQRR11b, 11
R by the other system RC read request set to c
Each of the CM caches 6b and 6c is indexed.

If the cache hits in the CPU 2b and the read data is "10", the data "10" is set in the RCRR 12b at timing 4, and the other system reply transmission register (ARPS) is set at timing T5.
16b is set. If the cache hits in the CPU 2c and the read data is "11",
Data “11” is set and output to the RCRR 12c at the timing T4, and is set to the other-system reply transmission register (ARPS) 16c at the timing T5.

In the CPUs 2b and 2c, A is set at timing T5.
When data is set in the RPSs 16b and 16c, the bidirectional bus 100 is accessed. Now, when the CPU 2b acquires the bus, the data '10' of the ARPS 16b is sent out to the bus, collected at timing T6 by the other system reply reception register (ARPR) 17a of the requesting CPU 2a, and the data '00 of the RPDR 13a held from T2. And OR in the OR circuit 10a. At the next timing T7, the data result “10” of the logical operation is changed to the RPDR again.
It is held by 13a.

On the other hand, at timing T5, the bidirectional bus 100
The ARPS 16c of the CPU 2c, which has not been acquired, keeps holding the data '11' until it acquires the bidirectional bus 100. When the CPU 2c acquires the bidirectional bus 100 at the timing T6, the ARPR17 at the timing T7.
'11' is set in a and the data of RPDR12a '
The logical sum of 10 'and the OR circuit 10a is obtained. At timing T8, the logical sum result data '1 is stored in the RPDR 13a.
1 'is set.

As described above, at the time of the RC read request, the logical sum of the data of all the RCM caches is taken by the hardware, and this is the E of the request source.
The data is returned to the PU 4 and, by the firmware processing, the return data from the MCU 5 and the data read from the RCM are ORed to obtain the reference result of the page history information.

FIG. 4A shows a system block diagram of the second embodiment of the present invention. The system of this embodiment basically has the same configuration as that of the first embodiment, but the CPUs 2a, 2
b and 2c are connected by a wire or OR by a connecting line 200. Further, the MCU 5 can input / output to / from the connection line 200, and the output from the MCU 5 to the connection line 200 is controlled by the switch circuit 201.

Upon receiving the RC read request, the request receiving unit 51 indexes the RCM cache 6.
In the RCM cache output control unit 54, according to the index result,
If there is a cache hit, the read data from the cache is output as is, and if there is a cache miss, R =
0 and C = 0 are output as read data of the RCM cache 6. This read data is output to the switch circuit 201.

When the request receiving unit 51 receives the RC read request, the bus access unit 53 receives this request from the request receiving unit 51, and receives all RCMs.
Bidirectional bus 1 to retrieve the relevant data in the cache
A function of issuing an RC read request at 00 and a function of collecting an RC read request on the bidirectional bus 100 and transmitting the request to the request receiving unit 51 are provided. The reply control unit 52 receives the logical operation result of all the RCM cache read data on the connection line 200 and returns the result to the EPU 4 as a data result.

FIG. 5 is an example of a timing chart showing the operation of the MCUs 5a, 5b, 5c. In FIG. 5, (A) to (E) show operations in the MCU 5a (F).
~ (H) shows the operation in the MCU 5b, (I) ~ (K)
Shows the operation in the MCU 5c.

FIG. 6 is a detailed block diagram of the MCU 5 for explaining FIG. Hereinafter, the operations of the MCUs 5a, 5b, 5c will be described in detail with reference to FIGS.

At timing T0, the request reception register (RQRR) 11a in the CPU 2a
When the RC read request from U4a is accepted, the request bus transmission register (R
QBS) 18a, RC on bidirectional bus 100
A read request is sent.

At timing T2, all CPUs 2a, 2a
Request bus reception register (RQBR) in b and 2c
The RC read requests on the bidirectional bus 100 are received at the same time at 19a, 19b, and 19c.
Set in QRRs 11a, 11b, 11c. CPU2
In a, 2b, and 2c, the RCM cache 6
Index a, 6b, 6c.

If the index result of the cache 6a is a hit, the read data "10" becomes R at timing T4.
The CM cache read register (RCRR) 12a is set. If the index result of the cache 5b is a hit, the read data '10' is R at timing T4.
It is set in the CM cache read register (RCRR) 12b. If the index result of the cache 5c is a mishit, '00' is set in the RCM cache read register (RCRR) 12c at timing T4. In this way, when the read data is set in all CPUs at the timing T4, it is output to the switch circuits 201 all at once, and the logical sum operation "10" + "10" + "00" = "10" is performed on the connection line 200. Be seen. At timing T5, the calculation result is set in the reply data register (RPDR) 13a in the CPU 2a.

As described above, at the time of the RC read request, the logical sum of the data of all the RCM caches is taken by the hardware, and this is the E of the request source.
The data is returned to the PU 4 and, by the firmware processing, the return data from the MCU 5 and the data read from the RCM are ORed to obtain the reference result of the page history information.

FIG. 7 shows a circuit diagram of the switch circuits 201a, 201b, 201c. The operation will be described in more detail with reference to FIG.

The connection line 200 is pulled up to a logical value "1" via a resistor 203. Also, the connection line 20
To 0, switch circuits 201a, 201b, 201c are connected. The switch circuits 201a, 201b, 201c are open-drain circuits formed by N-type MOS transistors. The outputs from the MCUs 5a, b, c are input to the N-type MOS transistors in the switch circuits 201a, b, c, respectively.

The N-type MOS transistor is turned on when the input is "1", and turned off when the input is "0". Therefore, if all the inputs to the switch circuits 201a, 201b, 201c are "0", the state of the connecting line 200 is "0".
1 ”, and if there is at least one“ 1 ”input, connection line 20
The state of 0 becomes '0'. In this way, the connecting line 20
On 0, NOR logic of outputs from all MCUs can be taken.

In the MCUs 5a, 5b, 5c, the connection line 20
Inverters 202a, 202b, 20
By inserting 2c, OR of each RCM cache read data is obtained.

[0044]

As described above, in the page history memory device according to the present invention, in a highly parallel multiprocessor system having a bus coupling structure, all page history memory information is read out and ORed when referring to the page history memory. By providing a page history memory cache that guarantees the consistency in each central processing unit, there is an effect that the page history memory access is speeded up, paging overhead is eliminated, and system performance is improved.

[Brief description of drawings]

FIG. 1A is a block diagram showing a first embodiment of a page history memory device according to the present invention. FIG. 2B is a block diagram showing a memory access processing device for realizing the page history memory device of the first embodiment.

FIG. 2 is a timing chart illustrating an operation of the memory access processing device according to the first embodiment.

FIG. 3 is a detailed block diagram of a memory access processing device according to the first embodiment.

FIG. 4A is a block diagram showing a second embodiment of the page history memory device according to the present invention. (B)
FIG. 11 is a block diagram illustrating a memory access processing device for realizing the page history memory device according to the second embodiment.

FIG. 5 is a timing chart illustrating an operation of the memory access processing device according to the second embodiment.

FIG. 6 is a detailed block diagram of a memory access processing device according to a second embodiment.

FIG. 7 is a circuit diagram showing wired-OR connection in the second embodiment.

FIG. 8 is a block diagram showing an example of a conventional technique.

[Explanation of symbols]

 1 main memory 2 central processing unit 3 page history memory 4 arithmetic processing unit 5 memory access processing unit 6 RCM cache 51 request acceptance unit 52 reply control unit 53 bus access unit 54 RCM cache output control unit 100 bidirectional bus 101 connection line 102 bus Input / output control circuit 200 Connection line 201 Switch circuit.

Claims (3)

[Claims] 1. A page history memory device in a virtual memory type information processing system, comprising: a main memory device and a plurality of systems of central processing units, wherein the main memory device and the central sled device are bus-connected. The central processing unit includes a page history memory cache that holds a part of the information of the page history memory that manages information indicating whether the data in the main storage device is referenced and information indicating whether the data is rewritten in page units. Further, when updating the page history information by memory access, a means for updating the data of the page history memory cache in the central processing unit that is the requester of the memory access, and a page history information reference request Means for reading the data in the page history memory cache, and the central processing unit Means for sending the page history information reference request to the host, means for the central processing unit receiving the page history information reference request on the bus, and read data of all the page history memory caches at the time of the page history information reference request. Means for generating page history information from a page history memory device. 2. A means for generating the page history information, a means for the central processing unit to send read data of the page history memory cache to the bus, and the central processing device for the page history memory cache on the bus. 2. The page history memory device according to claim 1, comprising means for receiving read data, and means for taking the logical sum of all the page history memory cache read data received by the central processing unit from the bus. 3. A connection line for generating page history information, wherein the central processing unit connects all the central processing units by wired or, and the central processing unit transfers read data of the page history memory cache to the connection line. 2. The page history memory device according to claim 1, further comprising: means for sending to the central processing unit, and means for the central processing unit to receive wired or OR page history information from the connection line.