JPH0865664A - Decoding device for compressed image data - Google Patents

Abstract

PURPOSE: To deal with the decode and display of input encoded data equipped with different frame frequencies by defining a clock frequency, which can generate regular horizontal synchronizing signal (hSync) and vertical synchronizing signal (vSync), as a display system clock concerning modes for two kinds of frame frequencies. CONSTITUTION: A timing unit 18 for supplying a clock signal and various kinds of processing timing to respective blocks inside the decoder of a buffer memory 11 or the like generates a display frame frequency matched with the frame frequency of input image data by frequency-dividing one display clock signal at a frequency dividing ratio corresponding to the frame frequency of input image data. In this case, first of all, the clock frequency to generate the regular hSync and vSync is adopted as the display clock concerning the modes for two kinds of frame frequencies. Therefore, when the frame frequency designated by the input encoded data is included in those two kinds of modes, data are outputted at a regular frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compressed image data decoding apparatus which decodes image data whose data amount is compressed by compression encoding and outputs decoded data which is synchronized with a display frame frequency of the image data.

[0002]

2. Description of the Related Art MPEG (Moving
Picture Experts Group). This is based on motion-compensated inter-frame prediction and discrete cosine transform (DCT), and is a target for compression of existing NTSC and PAL television signals and computer images represented by CCIR 601 standard. And has high versatility. Therefore, several kinds of image parameters such as the number of pixels of the image, the number of display lines, and the frame frequency are prepared.

Specific image parameters are, for example, “Journal of the Television Society”, Vol. 46, No. 9, pp. 1149-1152 (199).
As described in 2), the frame frequency of interest in the present invention (expressed as an image rate in the document) is from 23.976 Hz to 60 Hz. Although the frame frequency takes discrete values, the frequency generally used in broadcasting at present is 24H.
z (movie film), 25 Hz (PAL), 29.97
4 (Hz (NTSC), 30Hz (HDTV down-conversion output, 3 to 2 pull-down output from 24Hz))
Is one.

When these moving images are coded and compressed, the image data such as the frame frequency of the original image is encoded in the coded data so that they can be displayed at the normal speed without distortion when decompressed. To insert. In order to make full use of the versatility described above, the decoding device is required to output at least an image in the same format as the input image using these parameters.

Here again, focusing on the frame frequency,
The output data from the decoding device must be synchronized with the timing signals used for display, such as the vertical sync signal (vSync) and the horizontal sync signal (hSync). Otherwise, the frequency shift between the two will result in missing or overlapping image frames. Alternatively, a frame synchronizer having a frame memory must be separately provided in order to make the input and output / display frequencies independent. The sync signal above is
There are cases where it is supplied from an external display system and cases where it is generated inside the decoding device. In either case, it is generated by dividing the basic display system clock.

Further, for the purpose of outputting the decoded image data in the form of an analog television signal,
When the decoding device has a color encoding function,
Color subcarrier frequency (NTSC) for modulation of color signals
In this case, 3.579542 MHz) is required. In a standard television signal, the color subcarrier and the horizontal synchronization signal (hSync) are phase-locked, and the interleaving relationship of the color subcarrier between lines is maintained, but at least the continuous color subcarrier If it is modulated with, it is possible to demodulate on the monitor side based on the phase of the color burst of each line.

Here, the decoding device corresponds to the mode of the frame frequency designated by the input encoded data (the expression "mode" is used because the variable range of the frame frequency is often finite and discrete). In order to generate the synchronizing signal for display, the number of display system clock generation means corresponding to the frequency is prepared and switched according to the mode of the input frame frequency. The division ratio for generating the vertical and horizontal sync signals is
Choose a clock frequency that is an integer over each frame frequency mode. It is possible.

[0008]

However, the above-mentioned method obviously increases the number of parts and raises the cost. In addition, since the frequency of the clock that is the reference of the display timing is switched, the stability of the display system in a transient state is generated when the input frame frequency changes intermittently (for example, switching of image channels). Is damaged. Furthermore, depending on the frame frequency mode, a clock that is not synchronized with the color subcarrier may be selected, so a circuit such as a time base collector for newly synchronizing the timing of decoded data with the color subcarrier must be added. I won't.

On the other hand, in the above method, generally, the clock frequency that can be shared by three or more kinds of frame frequency modes must be a high frequency. For example, for three modes of frame frequencies 25 Hz, 29.97 Hz, and 30 Hz, the frequency must be 15.73425 GHz in order to exactly obtain both hSync and vSync by clock division, which is not realistic. .

[0010]

According to the present invention, in a decoding apparatus for compressed coded data, a display system clock serving as a reference of a timing signal used for display is first described in terms of normal hSync and vSync for two kinds of frame frequency modes.
A clock frequency capable of generating is adopted as a display system clock. For the remaining frame frequency modes, the frame frequency is set to the desired value, that is, the value specified by the input encoded data, by adjusting the division ratio that determines the hSync cycle without changing the number of lines that make up the display screen. Try to keep it. In addition, hSy generated by adjusting the above division ratio
Discontinuous points of the nc cycle are placed in the vertical blanking interval of the image.

Further, in order to realize the built-in color encoder, a display system clock synchronized with the color subcarrier is adopted.

[0012]

First, the clock frequencies that can generate normal hSync and vSync for the two types of frame frequency modes are
Since it is used as the display system clock, when the frame frequency designated by the input encoded data is included in the above-mentioned two types of modes, it is output at the regular frequency.
Since the frame frequencies are the same in the cases other than the above two types of modes, no image dropouts and overlaps occur, and the numbers of lines are the same, so the interlaced relationship of the input image is preserved. Here, the hSync cycle differs from the normal one and changes in line units, so that skew occurs at the discontinuity point, but since it is arranged in the vertical retrace line period of the image, it has little effect on the monitor screen.

The display system clock synchronized with the color subcarriers is synchronized with the data even in the nonstandard frequency mode and generates continuous subcarriers, so that the color encoder can be easily realized.

[0014]

The details of the present invention will be described below with reference to the illustrated embodiments.

<First Embodiment> FIG. 1 is a block diagram showing the arrangement of a compressed image data decoding apparatus according to the first embodiment of the present invention. In the figure, 1 is a decoder LSI, and 2 is a memory which is controlled by the decoder LSI 1 and stores data. Further, in the decoder LSI 1, 11, 12
Is a buffer memory, 13 is a variable length decoding unit, 14 is an IDCT (Inverse Discrete Cosine Transform) unit, 15 is a motion compensation unit, 16 is a display unit, 17 is a memory controller, and 18 is a timing unit.

In the above configuration, the encoded data is input to the decoder LSI 1 which is a decoding device, and is converted in the buffer memory 11 from the data rate of the transmission system to the data rate inside the decoder. The timing unit 18 supplies the clock signal and each processing timing to each block in the decoder including the buffer memory 11. The internal structure of the timing unit 18 will be described later. The encoded data stored in the buffer memory 11 is written to the memory 2 via the data bus in response to a data request signal requested by the memory controller 17.

FIG. 3 is a block diagram showing the configuration of the memory controller 17. In the figure, the serialization circuit 17
1 and the parallelization circuit 172 perform bus width conversion between the data bus inside the decoder and the high-speed memory data bus.
The free memory capacity calculation circuit 173 calculates the amount of data in the memory 2 as described later. Blocks 174 to 178 (encoded data write address generation unit 17
4, encoded data read address generation unit 17
5, a motion compensation reference image data read address generation unit 176, a decoded image data write address generation unit 177, and a display image data read address generation unit 178) generate an address for accessing the memory 2 for each process described later. It is a unit. The coded data write address generation unit 174 and the coded data read address generation unit 175 are in charge of controlling the coded data.

Here, the data allocation in the memory 2 is as shown in FIG. 4, which means that the area in which the encoded data is stored is the remainder obtained by subtracting 3 frames of pixel data from the entire memory area. . In order to prevent overflow of data from the area for encoded data, the memory free space arithmetic circuit 173 of the memory controller 17 includes both the encoded data write address generation unit 174 and the encoded data read address generation unit 175. By calculating the difference between the two addresses from, the amount of data in the memory 2 is monitored, and then the data request signal is sent to the buffer memory 11.

The encoded data read from the memory 2 is sent to the buffer memory 12. Buffer memory 1
2 internally calculates the free space, and the memory controller 17
By sending a data request signal to, the data overflow is avoided. Variable length decoding unit 1
3 reads data from the buffer memory 12 and decodes a variable length code such as Huffman code. Decoding result is ID
The CT unit 14 receives the inverse discrete cosine transform processing to obtain pixel data.

The pixel data is sent to the motion compensation unit 15 and is decoded by referring to the reference image data in the frame memory allocated in the memory 2 and adding the difference value to the reference value. Here, the range of the pixel data read as the reference is changed by the motion vector to be decoded based on the motion vector data from the variable length decoding unit 13 first. The motion vector is the motion compensation reference image data read address generation unit 17 in the memory controller 17.
6 is supplied to the memory 2 to generate an address shifted in the horizontal / vertical direction by calculation with the memory address. The decoded image data is converted by the display unit 16 into data whose time axis is synchronized with a timing signal from the outside.

FIG. 5 is a block diagram showing the structure of the display unit 16. In the figure, 161 is a line memory (Y), 162 is an interpolation circuit, 163, 1
64 is a line memory (C), 165 is a serialization circuit, 16
6 is a timing controller, 167 is an OSD (on-screen data) generation circuit, and 168 is a multiplexer.

The image data from the memory 2 is input to the display unit 16 via the data bus, and the serializing circuit 16
5, the bit width conversion and the distribution processing to the luminance signal (Y) and the color difference signals (Cb, Cr) are performed. The image is read out in the display order, that is, in the line direction, and the line memory (Y) 161 and the line memory (C) 163, 1 are read.
It is written in 64 in the same order. The timing controller 166 controls the line memory based on the timing given by the timing unit 18.

In the image data read from the line memories 161, 163, 164, the luminance signal is directly sent to the multiplexer 168, and the color difference signal is 4: 2: 0 to 4: 2: 2 in the interpolation circuit 162. After being subjected to the interpolation processing to, it is sent to the multiplexer 168. OSD to the other input of multiplexer 168
On-screen data from the generation circuit 167 is sent,
The timing of the on-screen data to be superimposed and displayed on the screen is designated by the imposing signal. The content of the on-screen data may be written in the memory 2 directly from the host system, although it is not shown in the figure, even if it is based on the user data included in the input encoded data and decoded by the variable length decoding unit 13. It may be read out. The output of the multiplexer 168 becomes image data (Y, C) synchronized with the display timing, and is sent to the system in the subsequent stage as the output of the decoder LSI 1.
The above is the outline of the operation of the decoding device shown in FIG.

Next, the operation timing will be described.
FIG. 6 is an explanatory diagram showing the timing of allocating access to the memory 2 when the format of encoded data and the timing of display are both standard NTSC television signals. The horizontal axis shows time.

VSync and hSync are a vertical sync signal and a horizontal sync signal, respectively, and may be supplied with timing from outside the decoder LSI 1 or may be generated internally. At the timing unit 18,
It is generated by dividing the display clock pelCLK. vSync is a pulse that represents the beginning of one field on the display screen, has a spacing of 262.5 display lines, and is repeated at a cycle of ½ of 525 lines of one frame. hSync is a pulse representing a display line and has a period of 63.56 μs in NTSC.

In this embodiment, the frequency of pelCLK is set to 13.5.
MHz, hSync divides by 858, vSync divides it by 262.5, that is, 22522 of pelCLK.
It is a pulse divided by 5. Line number 0 for each line
From 1 to 524, 1 frame of display screen is
V (vertical) blanking period from the beginning 0 line to 22 lines, video period from 23 lines to 262 lines, 263
It is composed of a V blanking period from line 284 to a video period from line 285 to a line 524.

The V blanking period includes a vertical synchronizing signal portion representing a blanking period and a non-picture portion into which additional information such as a test signal and a time code can be inserted, and the video period is actually displayed on the monitor. This is the video part.

An enlarged representation of one line is the lower part of FIG. Here, in order to explain the timing of memory access, the operation clock of the memory 2 (memC
I will call it LK). In the present embodiment, memCLK is set to 29/6 times pelCLK (display system clock) in order to speed up the decoding process, and this is obtained by configuring pelCLK and a phase locked loop (PLL). Therefore, one line corresponds to 4147 cycles of memCLK. This 4147 clock cycle is made into a time slot and assigned to the memory access of each processing. First, a slot having 3 cycles of 1380 clocks is defined, and pixel-based data called a macroblock is decoded during this 1 cycle.

The definition of the macroblock is shown in FIG. One frame screen (720 x 480 pixels) is displayed vertically and horizontally with 4
A range of 16 pixels square divided into 5 and 30 is defined as one macroblock (MB), and a total of 1350 MB is the number in one frame. Regarding the color difference signal, the sample rate is half, and the macroblock of 8 pixels square is Cb,
Each Cr is in the same position as the luminance macroblock. Since the macroblock is a unit that defines the above-described motion vector, the reference screen is also read in macroblock units. The luminance macroblock is
It is further divided into 8 pixel square blocks, which are DCT
A unit that performs (discrete cosine transform) processing is called a DCT block.

FIG. 9 shows an example of mapping of macroblocks (MB0 to MB1349) for one frame in the memory 2. As shown in the figure, the macroblock (M
They are arranged in units of B) so that they can be easily accessed. 512 columns (8 × 8 × 4 × 2) × 1013 rows ((1
If the information amount is 8 bits per pixel at the address of 350/2) × 1.5), a capacity of about 4 megabits is required to configure one frame memory.

Returning to FIG. 6, the internal details of the 1380 clock of memCLK allocated to the processing of one macroblock will be described. Six kinds of slots are provided in the 1380 clock, and the memory access is allowed only for the time slot for the processing corresponding to each slot. The following is a list of each process: (a) process result (display image data) read, (b) reference (motion compensation reference image data) read, (c) bit buffer (coded data) read, (d) memory refresh, ( e) writing of bit buffer (encoded data), (f) writing of processing result (display image data), and the remaining period is (g) margin area.

Except for the above (d) and (g), which are not directly related to image processing, each memory access is performed by each address generation unit 174 to 178 in the memory controller 17 shown in FIG. The pattern given to the time slot in FIG. 6 corresponds to that of the address generating unit in FIG. The length of each of these time slots is determined by the time required for each process. (B) Reference (motion-compensation reference image data) is read with a relatively long slot in case of multiple reference screens. Have been assigned. In addition, (a) processing result (display image data) reading includes the above-described OSD processing.

Here, assuming that the processing of one macroblock is one
If the slot does not fit within the 380 clock slot, it can be dealt with by using the next slot. The number of slots given to the total number of macroblocks 1350 is 1458.
Since there are one, it is configured to withstand up to 108 overloads per frame.

Further, vSync which is a reference of the frame period
Is generated from the timing of the display system, the slot for (a) processing result (display image data) read is line number 23 to 262 and line number 2 which are video periods.
The reading process is performed only during the period of 85 to 524. In the V blanking period at the beginning of the frame, a large number of slots for (e) bit buffer (encoded data) writing are provided to centrally transfer the encoded data into the memory, and a blank portion of the slot Then, the header information such as various image parameters contained in the encoded data is analyzed.

The memory access control in macro block units has been described above. Further, a macroscopic view of this is shown in FIG. In the figure, vSync at the bottom is the same as that in FIG. 6, and represents the memory access timing in frame units according to the display timing. The encoded data is decoded according to the time on the horizontal axis, the processing result is written to the assigned memory, and the data is read in synchronization with the display timing. As described above, the coded data handled by the decoding device according to the present invention uses the motion-compensated interframe prediction to reduce the amount of information. Each frame (or field) is called differently depending on the type of prediction. Here, according to the MPEG, a reference is an I picture, a reference using only forward prediction from an I picture is a P picture, and
The ones using the forward and backward prediction from both the I and P pictures are called B pictures, respectively. The abbreviations in FIG. 7 are, for example, I-W for writing I-picture, P1
-W represents writing of the first P picture P1, and P0
ref-R represents reading of the 0th P picture P0 as a reference image. The pattern used in FIG. 7 corresponds to those in FIGS. 3 and 6.

In the example shown in FIG. 7, first, the I picture is decoded and written in the frame memory "1" (see FIG. 4). The 0th P picture P0 is stored in the frame memory “2” in the previous cycle, and P0 is read from the frame memory 2 at the same time when the I picture is written. The term “simultaneous” here is actually shown in FIG.
It means that the memory access is being performed based on the time slot shown in. P picture P read
0 is synchronized with vSync and is displayed following V blanking. Then, the decoding process of the first B picture B1 is performed. I-pictures and P-pictures are read from the frame memories “1” and “2” as references, respectively, and the data that has been calculated with the difference data is written into the frame memory “3” as B-picture B1. The written B picture B1 is read out with a delay of about 1 field and becomes display data. Similarly, B picture B2, P picture P1, B picture B3 are decoded and stored in each frame memory.
The picture and the B picture B3 are read in this order in accordance with the display timing.

A timing unit 18 supplies a timing / control signal which gives the timing of the above-mentioned microscopic and macroscopic memory access control. Figure 2
FIG. 2 is a block diagram showing a configuration of a timing unit 18, in which reference numeral 181 denotes an H timing generation circuit, 1
Reference numeral 82 is a V timing generation circuit, 183 is a logic gate circuit, and 184 is a PLL (phase locked loop) circuit.

The H timing generation circuit 181 driven by pelCLK and the V timing generation circuit 182 driven by the line cycle can be reset by hSync and vSync, respectively, and can be operated at the timing synchronized with them. The PLL 184 multiplies pelCLK to generate memCLK. In this embodiment, the frequency is 13.5M.
The frequency is multiplied by 29/6 to generate 65.25 MHz. The logic gate circuit 183 outputs various timing / control signals based on the output from each block and the mode information from the encoded data. A part of the output is fed back to the H timing generation circuit 181 and the V timing generation circuit 182, and the operation corresponding to each mode is performed.

FIG. 10 shows reference timing signals generated by the timing unit 18 for three modes in which the frame frequency of the input encoded data is 29.97 Hz, 30 Hz and 25 Hz. The clock in FIG. 10 is pelCLK having a frequency of 13.5 MHz. First, in the case of a standard NTSC signal with a frame frequency of 29.97 Hz, 85
Regular hSync in 8 clock cycles (cycle 63.56μ
s) can be generated, and one frame (4504
50 clocks) can be configured. In addition to the timing signal that defines the time slot, other control signals are generated based on the same timing.

Next, in the mode in which the frame frequency is 30 Hz, it is necessary to adjust the period of one frame to 450,000 clocks. In the present invention, this is realized by increasing or decreasing the cycle of a specific line without changing the number of display lines. In this embodiment, the line number 262 and the line number 52 corresponding to the last line of the field.
The frame period of a total of 450,000 clocks is obtained by reducing the two line periods of 4 to 633 clocks. The discontinuity of the line cycle appears as a skew on the monitor screen, but it is not noticeable because it is at the bottom of the screen. Further, since it can be expected that the influence will be converged within the subsequent V blanking period, the disturbance of the screen is unlikely to be remarkable.

Along with the adjustment of the line cycle, the time slot is also changed as shown in FIG. In the figure, pelCLK decreases by 225 clocks in two lines of line numbers 262 and 524, which means that memCLK is 108
This means that 7.5 clocks are reduced. Therefore, in the two lines of line numbers 262 and 524, the last one from the slots of three macroblocks is
Delete one. As a result, about 1/3 of the display will be deleted, but this is not affected because it is a line that causes skew. Further, as to the macroblock to be decoded in the deleted slot, the number of slots has a margin as described above, so that it is dealt with by shifting to the subsequent slot.

In the 30 Hz mode, the H of the frame frequency of 60 Hz is used as the signal format of the input data.
A signal obtained by down-converting a DTV signal is assumed, and a signal obtained by converting a motion picture film having a frequency of 24 Hz into 30 Hz by a 3 to 2 pull-down process is also accepted.

Finally, in the mode in which the frame frequency is 25 Hz, the PAL system (625/50) is used. As shown in FIG. 10, pelCLK has 864 clock cycles as one line, and 625 lines make one frame (54000).
0 clock) can be generated at the timing of the regular PAL signal. This is 13.5M for the frequency of pelCLK
Due to the choice of Hz. Regarding the allocation of time slots, the NTSC (29.97
(Hz), the description can be omitted here.

As described above, in this embodiment, a timing signal synchronized with one type of display system clock (pelCLK) is generated, and decoding of encoded data and display data is performed in accordance with a time slot assigned based on this timing signal. In a decoding device that outputs the following, the frame frequency of the input data is 29.97 Hz, 30 Hz (24 Hz), 25 Hz
One method of making both the frame frequency and the number of display lines coincide with each other in the input and output is shown for each of the three modes. If it is attempted to obtain an output without creating a skew in the 30 Hz mode, one frame period is 45045.
It is necessary to separately prepare and switch another display system clock that becomes 0 clock, that is, pelCLK having a frequency of 13.5135 MHz. This leads to an increase in peripheral circuits such as an oscillation circuit, resulting in an increase in cost, and switching of the frequency of the clock that serves as a reference for display timing, so that the input frame frequency changes intermittently (for example, image channel Switching) is disadvantageous in that the stability of the display system in a transient state is impaired.

<Second Embodiment> Next, a decoding apparatus for compressed image data according to a second embodiment of the present invention will be described with reference to FIG. In FIG. 12, the display system clock (pelCLK) is set to 13.5 MHz as in the first embodiment, and the frame frequency of input data is 29.97 Hz, 30 Hz (24 Hz), 2
The reference timing signal generated by the timing unit 18 is shown for the three modes of 5 Hz. The decoding device for compressed image data according to the present embodiment has the same configuration as that of FIG. 1 although not shown.

This embodiment differs from the first embodiment in that the number of clocks for one line is 85 in the 30 Hz mode.
7 points. Along with this, as a method of adjusting one frame period to 450,000 clocks, the line number 262 is changed to 894 clocks and the line number 524 is changed to 895 clocks. Since the difference in the changed line lengths is 37 clocks and 38 clocks, the difference is significantly smaller than the difference value of 225 clocks in the first embodiment. When converted into a ratio with the line period, the difference value is reduced from 26.2% to 4.4%, so that the effect of skew occurring on the monitor screen is significantly reduced, and the image quality is maintained while maintaining the effect of the first embodiment. Is improved.

<Third Embodiment> FIG. 13 is a block diagram showing the arrangement of a compressed image data decoding apparatus according to the third embodiment of the present invention. In FIG. 13, the same parts as those in FIG. The explanation is omitted to avoid duplication. In FIG. 13, 19 is an address counter and 20 is an RO.
M and 21 are color encoders, and 22 is a digital / analog converter (DAC).

The difference of this embodiment from the first embodiment is that a block for generating analog image data is added to the output of the decoder LSI1. The address counter 19 is a counter that counts a pelCLK (display system clock) having a frequency of 13.5 MHz, and gives an address as an output to the ROM 20 for generating a color subcarrier waveform. A subcarrier waveform of 858 samples per line is stored in the ROM 20, and the sine (s
in) and cosine (cos) waveform data are output.
The color encoder 21 receives the subcarrier waveform data, multiplies it with the color component data (Cb, Cr) from the display unit 16, and outputs the NTS.
Generate C and PAL subcarrier modulated outputs. This modulated output data is DA, together with the luminance signal data (Y) to which the synchronizing signal from the display unit 16 is added.
It is sent to a C (digital / analog converter) 22 and output to the outside of the decoder LSI 1 as an analog image signal. The timing unit 18 outputs the timing signal in the first or second embodiment,
Frame frequency of input data is 29.97Hz, 30H
z, 25 Hz, common to all three modes: 13.5
Image data can be output from the display unit 16 at a data rate of MHz.

Therefore, the frame frequency is 29.97H.
In the two modes of z and 25 Hz, standard NTSC and PAL system color television signals can be obtained as outputs, respectively, and even in the mode in which the frame frequency is 30 Hz, continuous color irrespective of the line period. Subcarrier and color component data can be multiplied at a data rate of 13.5 MHz, so it is a non-standard but burst-locked pseudo NTSC
It is possible to output a color signal. This pseudo NT
The SC color signal is the same as the output signal of a home VTR such as the VHS system, and the color signal can be demodulated on the monitor side without any problem.

If the frame frequency is 30 Hz, 1
If a similar color output is to be obtained by switching to pelCLK of 3.5135MHz, it is not possible to generate continuous subcarriers in synchronization with the data of 13.5135MHz. A rate converter (for example, a time base collector) is provided to match the carrier data rates, or output data jitter is generated due to data rate mismatches, which deteriorates the image quality of the entire screen, or discontinuous subcarriers. It is necessary to select either one of the following to allow the color disturbance at the discontinuous point by modulating with.

As described above, according to the third embodiment, one inexpensive display system clock is used and the frame frequency is 29.97 Hz, 30 Hz (24 Hz), 25 Hz.
In this case, good analog color image signals can be obtained corresponding to the three modes.

[0052]

As described above, according to the present invention, since one type of display system clock can be used for decoding and displaying input coded data having different frame frequencies, the number of parts can be reduced. The cost of the device is suppressed. Further, since the display system clock is synchronized with the color subcarrier, it is possible to generate continuous subcarriers in synchronization with the data even in the nonstandard frequency mode, and as a result, the color encoder can be easily realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a compressed image data decoding device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a timing unit in FIG.

3 is a block diagram showing a configuration of a memory controller in FIG.

FIG. 4 is an explanatory diagram showing data allocation inside a memory in each embodiment of the present invention.

5 is a block diagram showing a configuration of a display unit in FIG.

FIG. 6 is an NTSC in which both the format of encoded data and the timing of display are standard according to the first embodiment of the present invention.
It is explanatory drawing which shows the timing which allocates access to a memory in the case of a television signal.

FIG. 7 is an explanatory diagram macroscopically showing the timing of frame memory access according to the first embodiment of the present invention.

FIG. 8 is an explanatory diagram of macroblocks used in each embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a macroblock arrangement in a memory according to each embodiment of the present invention.

FIG. 10 is an explanatory diagram showing timings of synchronization signals in each frequency mode according to the first embodiment of the present invention.

FIG. 11 is an explanatory diagram showing the timing of frame memory access in a mode in which the frame frequency is 30 Hz according to the first embodiment of the present invention.

FIG. 12 is an explanatory diagram showing timings of synchronization signals in each frequency mode according to the second embodiment of the present invention.

FIG. 13 is a block diagram showing the configuration of a compressed image data decoding device according to a third embodiment of the present invention.

[Explanation of symbols]

1 Decoder LSI (Decoding Device) 2 Memory 11, 12 Buffer Memory 13 Variable Length Decoding Unit 14 IDCT (Inverse Discrete Cosine Transform) Unit 15 Motion Compensation Unit 16 Display Unit 17 Memory Controller 18 Timing Unit 19 Address Counter 20 ROM 21 Color Encoder 22 DAC (digital / analog converter) 161 Line memory (Y) 162 Interpolation circuit 163, 164 Line memory (C) 165 Serialization circuit 166 Timing controller 167 OSD (on-screen data) generation circuit 168 Multiplexer 171 Serialization circuit 172 Parallelization circuit 173 Free memory capacity calculation circuit 174 Encoded data write address generation unit 175 Encoded data read address generation unit 176 motion compensation reference image data read address generation unit 177 decoded image data write address generation unit 178 display image data read address generation unit 181 H timing generation circuit 182 V timing generation circuit 183 logic gate circuit 188 PLL (phase locked loop) circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H04N 5/06 Z 7/01 C (72) Inventor Hiroki Mizozoe 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Bunch Co., Ltd. Hitachi Media Imaging Media Laboratory

Claims (8)

[Claims] 1. An apparatus for decoding image data, the data amount of which is compressed by compression encoding, comprising a memory serving as a buffer for accumulating and decoding input image data, and writing data to the memory. And a memory controller for controlling data reading from the memory, a display unit for synchronizing the decoded image data with a display timing, and a timing unit for giving a timing at which the memory controller and the display unit operate. The timing unit divides one display clock signal by a division ratio according to the frame frequency of the input image data to generate a display frame frequency that matches the frame frequency of the input image data. , By this, the decoded data synchronized with the display frame frequency A decoding device for compressed image data, which outputs 2. The timing unit according to claim 1, wherein the timing unit divides one display clock signal by a division ratio according to a frame frequency of the input image data to match the frame frequency of the input image data. A decoding device for compressed image data, which has a mode in which the display frame frequency is generated, and the number of display lines per frame is constant regardless of the display frequency of the input image data. 3. The timing unit according to claim 2, wherein the timing unit divides one display clock signal by a frequency division ratio according to a frame frequency of the input image data to match the frame frequency of the input image data. Generated display frame frequency, the number of display lines per frame is constant regardless of the display frequency of the input image data, and the length of the display line is allocated by dividing the frame period approximately equally by the number of display lines. A decoding device for compressed image data, having a mode in which lines having different lengths for compensating for excess or deficiency with respect to a frame period are arranged in a vertical blanking period of a display screen. 4. The display according to claim 2, wherein the timing unit divides the display clock signal by a frequency division ratio according to the frame frequency of the input image data, so as to match the frame frequency of the input image data. A frame frequency is generated, the number of display lines per frame is constant regardless of the display frequency of the input image data, and the length of the display line uses two types in which the count number of the display clock signal is different by 1, A decoding device for compressed image data, characterized in that it has a mode in which a frame period is assigned by being equally divided by the number of display lines. 5. The timing unit according to claim 1, wherein the timing unit is a display clock signal.
Using 3.5 MHz, the frame frequency of the input image data is 29.97 Hz, 30 Hz or 24 Hz, 25 Hz
450 450, 45 depending on the three modes of
A decoding device for compressed image data, wherein a display frame frequency that matches a frame frequency of input image data is generated by dividing the frequency by 0000, 540000. 6. The timing unit according to claim 3, wherein the timing unit is a display clock signal.
Using 3.5 MHz, the frame frequency of the input image data is 29.97 Hz, 30 Hz or 24 Hz, 25 Hz
450 450, 45 depending on the three modes of
By dividing by 0000,540000, 29.9
Display frame frequencies of 7 Hz, 30 Hz, and 25 Hz are generated, and the number of display lines per frame is 525 lines, 525 lines, and 625 lines, respectively, according to each of the above modes. Depending on,
858 when forming a line with a uniform clock cycle,
A feature is that switching is performed between the case of forming a line of 57 clock cycles, of which a total of 75 clock cycles is added to two lines and allocated to the vertical blanking period of the display screen, and the case of forming a line with a uniform 864 clock cycle. Decoding device for compressed image data. 7. The display unit according to claim 4, wherein the timing unit is a display clock signal.
Using 3.5 MHz, the frame frequency of the input image data is 29.97 Hz, 30 Hz or 24 Hz, 25 Hz
450 450, 45 depending on the three modes of
By dividing by 0000,540000, 29.9
Display frame frequencies of 7 Hz, 30 Hz, and 25 Hz are generated, and the number of display lines per frame is 525 lines, 525 lines, and 625 lines, respectively, and the display line configuration depends on each of the modes. hand,
858 when forming a line with a uniform clock cycle,
A decoding device for compressed image data, which is switched between the case of forming 450 lines of 57 clock cycles and the line of 75 lines of 858 clock cycles and the case of forming lines with uniform 864 clock cycles. 8. The means according to claim 5, 6 or 7, for generating from said display clock signal 13.5 MHz a continuous and continuous color subcarrier.
And a color encoder for modulating a color component signal into a television signal using the color subcarrier.