JPH0864803A - Logical operation circuit without wiring - Google Patents

Abstract

PURPOSE: To eliminate wiring between transistors by arranging an element by permitting the center of spherical or cylindrical conductive material to accord with a lattice point on the prescribed row and transmitting electrons or particles in the conductive material by tunnel phenomenon. CONSTITUTION: A major part is composed of two input parts 1002 and 2003, which input electrons, an interaction area 2001, a branching area 40, an observation area 50 and an output area 60. Conductive material is arranged in each area, permitting the centers of the conductive material to accord, and a logical circuit 70, which is to be an OR gate, is provided. The logical circuit 70 permits electrons inputted to the input areas 2002 and 2003 to be outputted from the branching area 40, all electrons are to be inputted to the observation area 50, and the observation area 50 outputs electrons to the output area 60 when electrons are inputted. The conductive material is connected by one-electron tunnel phenomenon, and an electron to be the signal can be transmitted between the conductive material without arranging wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical operation circuit, and more particularly to a logical operation circuit which does not require wiring between transistors which is normally performed by arranging a plurality of conductive materials coupled by a one-electron tunnel phenomenon at predetermined positions. Regarding an arithmetic circuit.

[0002]

2. Description of the Related Art By the time the channel size of a MOS device reaches a quarter micron region, the conventional VLSI integration technology reaches the limit due to the quantum effect. This limitation will become a major problem in the near future, as many advances in integrated circuits have been based on the continuous advancement of miniaturization. In order to solve this problem, devices that positively utilize the quantum effect have been actively proposed. There are many types of devices utilizing the quantum effect, and one of them is a one-electron tunnel transistor utilizing the particle property of electrons.

The one-electron tunnel transistor is IEEE Transaction on Magnetics, Volume 23 (1987),
Page 1142-1145 (IEEE, Trans. Magnetics, MAG-23 (1987),
As shown in pp1142-1145), a microcapacitor whose capacitance is about femtofarad is its basic constituent element. In addition, the insulating film used for the microcapacitor is thinned to enable tunneling between conductive substances of electrons. In such a microcapacitor, when the temperature range of T <e2 / (2Ck) and the potential difference between the microcapacitors are within the range of -e / (2C) <V <e / (2C), between the conductive materials of electrons, The phenomenon that tunnels are banned is called Coulomb Brocade. Here, T is the temperature, V is the potential difference between the microcapacitors, e is the charge amount of one electron, C is the capacitance of the microcapacitor, and k is the Boltzmann constant. When the potential difference between the microcapacitors exceeds the Coulomb brocade condition, that is, when the Coulomb brocade is released, a one-electron tunnel occurs between the conductive materials. In the one-electron tunnel transistor,
The coulomb brocade state is interpreted as a switch-off state, and the coulomb brocade release state is a switch-on state. The one-electron tunnel transistor is a three-terminal switching element in which three microcapacitors are connected to control the on / off state and are assigned as three terminals of a gate, a source, and a drain, respectively.

According to the above conditions, if the capacitance of the microcapacitor is reduced by reducing the area of the capacitor, Coulomb blockade can be realized at a higher temperature and a higher inter-capacitor voltage. Using the current microfabrication technology, theoretically room temperature operation is also possible. Furthermore, the one-electron tunnel transistor has a large conductance ratio when turned on and off compared to an electron wave interference element which is the same quantum effect element, and the element characteristics are not greatly affected by minute changes in the structure. Therefore, the one-electron tunnel transistor is drawing attention as a main candidate for the next-generation ultrafine element.

In Japanese Patent Application No. 6-27710 and Toshiba's press release (Nikkan Kogyo Shimbun, April 8, 1994), a plurality of one-electron tunnel transistors are arranged on a two-dimensional plane to form a logic circuit. It is shown to be configured.

[0006]

When a logic circuit is formed by using switching elements having three terminals or more terminals, a plurality of three-terminal (or more terminals) switching elements are used as desired logic elements. Wire according to the structure. As a result, if the element is miniaturized, the wiring density becomes high, and there is a possibility that the wiring cannot be actually performed. That is, even if a fine element is used, the required wiring area hinders the integration of the chip. Furthermore, when the above-mentioned one-electron tunnel transistor is used as the limit of miniaturization of the element, there is a high possibility that the element will not operate normally due to the influence of the stray capacitance between the element and the wiring. Therefore, in the case of forming a logic circuit by utilizing the one-electron tunnel phenomenon, it is necessary to reduce the wiring as much as possible from the viewpoints of both the improvement of the degree of integration and the reliability of the element. For that purpose, it is necessary to select a logic circuit configuration method different from the conventional logic circuit based on a three-terminal switching element.

In order to be able to construct an arbitrary logic circuit with the new logic circuit construction method, it is necessary to construct an OR gate, a NOT gate, a FANOUT and a wire according to the construction method. Arbitrary logic can be combined using only NOT and OR operations. Furthermore, in order to synthesize a complex logic function, a gate that has the function of connecting one output of the gate to multiple inputs, that is, FANOUT is required. Further, in order to synchronize the input signal to the gate in the logic circuit, an element called a wire for adjusting the delay of the signal is required. The basic building blocks required to configure a logic circuit are the OR gate, NOT gate, and FAN.
It can be said to be OUT and wire. Therefore, if there is a non-wiring logic circuit construction method that can realize these basic constituent units, an arbitrary non-wiring logic circuit can be constructed.

On the other hand, in Japanese Patent Application No. 6-27710 and Toshiba's press release, the delay time is large due to the fact that the length of the signal and the transmission path of the signal are different because the elements are arranged in two dimensions. Since it is two-dimensional, it is difficult to achieve high integration as compared with three-dimensional one. Furthermore, in the two-dimensional case, the order parameter peculiar to the two-dimensional Coulomb system does not change, and the susceptibility, which is the second derivative of the energy with respect to the temperature, diverges, Kosterlits-Thoules
There is the problem that s transitions exist and impair the reliability of the circuit. Furthermore, in the case of Toshiba's two-dimensional circuit, the electron's own motion is carried out through a dipole, and a signal is transmitted by a so-called flip-flop at a certain localized position, so one electron transport phenomenon. Does not handle Further, since Japanese Patent Application No. 6-27710 is applied only to the regular honeycomb lattice, the margin of dimensions and the like must be extremely small.

An object of the present invention is to eliminate the above-mentioned restrictions, to allow a large margin such as the size of the honeycomb lattice, and
The purpose of the present invention is to provide a logic circuit that can be applied to transport phenomena of many electrons other than the one-electron tunnel phenomenon and classical particles other than electrons. Further, an object of the present invention is a circuit that can be applied to general transport phenomena including a three-dimensional one-electron tunnel phenomenon, and a logic circuit that can be applied to an arbitrary lattice without the framework of a regular lattice that is difficult to realize in actual trial production. To provide.

[0010]

[Means for Solving the Problems] The element is arranged and the conductive material is arranged such that the centers of the spherical or columnar conductive material coincide with predetermined lattice points. Two conductive materials within a certain distance are bound by particle scattering or one-electron tunneling phenomenon, and in other arrangements,
There is no bond between conductive materials due to the tunnel phenomenon. By the flight of the particles or the coupling by the one-electron tunnel, a signal, that is, the particle or one electron can propagate between the conductive substances without wiring.

Further, since the scattering, flight, or coupling of particles by one-electron tunneling phenomenon can be limited by the two-dimensional or three-dimensional arrangement of the conductive material, the particle or one-electron propagation can be changed by changing the arrangement. Can be controlled. Therefore, the particle or one-electron excess state in the conductive material is set to the logical "1", and the normal state is set to the logical "0".
By corresponding to, the propagation of particles or one electron can be associated with the process of logical operation. In other words, by applying a negative potential to a predetermined conductive substance for signal input, the introduced particles or electrons can finally reach the conductive substance for signal output by a logical operation.
1 "and the case where it cannot be reached correspond to the logical operation" 0 ".

From the above, the group of conductive substances arranged at a predetermined position operates as a logical operation circuit using one electron as a signal. The feature of this method is that
OR, which is the basic building block for constructing an arbitrary logic circuit
It is possible to generate gates, NOT gates, FANOUTs and wires with a population of conductive materials. Since the method of arranging the conductive material is determined for each of these basic building blocks, by expressing the desired logic using OR gates, NOT gates, FANOUTs, and wires, the conductive material for any logic circuit can be defined. The arrangement method is determined. further,
The problems peculiar to the two-dimensional Coulomb system and its constraints can be solved by expanding to the three-dimensional system.

[0013]

By arranging a plurality of conductive materials coupled by the one-electron tunnel phenomenon at predetermined two-dimensional or three-dimensional positions, it is possible to construct a logical operation circuit which does not require wiring between transistors, which is usually performed. This makes it possible to construct a highly reliable, ultra-high integration non-wiring logic circuit using the one-electron tunnel phenomenon. Further, according to the present invention, since an OR gate, a NOT gate, a FANOUT and a wire, which are basic units for the logic circuit configuration, can be generated, an arbitrary non-wiring logic circuit can be configured.

[0014]

1 shows an embodiment of a non-wiring logic circuit according to the present invention. An example of a circuit configuration using particles in the case where the quantum property is not a problem will be described below. In order to understand the operation of the logic circuit shown in FIG. 1, first, the physical phenomena in the case of using the flight of a single particle or a group of particles such as classical diffusion, ballistic, quantum transport, particle jump, etc. In the invention described, the elements of the circuit consist of an input area, an interaction area, a branch area, an observation area and an output area, which areas consist of a plurality of devices. FIG.
Then, 2002 and 2003 are input regions, 2001 (particularly 20) is an interaction region, 40 is a branch region, 50 is an observation region, and 60 is an output region. Here, black circles indicate some routes.

In the case where an electric potential capable of flying one classical particle (atom, electron) such as diffusion and ballistic is applied,
A single classical particle introduced into the input region for signal input flies toward the lower energy interaction region 20. On the contrary, when the applied potential is small and the energy increases due to the tunneling of one particle, the flight of the particle is prohibited. The physical phenomenon in which the flight of particles is controlled by the magnitude of the applied potential in this way is called flight control of particles. From the above, particle flight is
This is a physical phenomenon in which particles propagate in the direction of lower energy.

Against the background of this single atom flight phenomenon, what plays an important role in the present invention is the interaction between particles. When the applied potential condition is adjusted so that two particles enter the device within one region, the applied potential condition in which the energy is high is easily realized. However, in general, two particles cannot simultaneously enter within a certain (effective collision) distance due to the repulsive interaction between the particles. Therefore, the particles generally move in different flight directions in the 40 branch regions.

There can be any number of flight directions and flight paths at the bifurcation region. When the flight direction and flight path in the bifurcation area are all input paths to the observation area, that is, when all particles from the bifurcation area are in the observation area, as long as particles enter the input area, output Particles are always output to the area. Therefore, as shown in FIG. 2, assuming that particles are present at the terminals 2002 and 2003 in the input area as 1 and as 0 when no particles are present, the output area becomes 2002.
Particles are present except in the case where both No. and 2003 do not have particles. Therefore, the circuit element is an OR gate.

On the other hand, the NOT circuit element is a device and a device that prevent a particle entering the input area from entering the observation area when interacting with another particle in the interaction area and leaving the branch area. Adjust network placement,
Keep particles out of the output area. On the other hand, when particles do not enter the input area, there are particles in the observation area,
It suffices that the particles come out of the output area. Based on the flight of particles (or particles) shown here, OR gates, NOT gates, FANOUT, and wires can be constructed. It is generally known that if an OR gate, a NOT gate, a FANOUT, and a wire can be configured, theoretically any logic circuit can be assembled.

An example of the configuration of a general circuit of one-electron tunnel coupling will be described. Next, also in the case of the one-electron tunnel coupling, the logic circuit 70 shown in FIG. 1 operates as an OR gate as shown in FIG. Hereinafter, the configuration of the logic circuit 70 will be described in the case of the one-electron tunnel coupling. The one-electron tunnel device is placed at the device position. The correspondence will be described below. The logic circuit 70 arranges the conductive material such that the centers of the conductive materials coincide with 20, 40 and 50 of FIG. 1 for any element arrangement. The vertices on which the conductive material is placed depends on the desired logic. The two conductive materials are bonded by the one-electron tunnel phenomenon, and in the other arrangements, there is no bond between the conductive materials by the tunnel phenomenon. Due to the existence of the coupling by the one-electron tunnel, a signal, that is, one electron can propagate between the conductive materials 10 to 60 without wiring. (As long as the flight path of the particle can be set, this also applies to the flight mode of any particle.) Furthermore, the coupling due to the one-electron tunneling phenomenon is limited by the arrangement of the conductive material. Since the propagation of one electron can be controlled by changing its arrangement, the circuit 70 having a logical operation function can be constructed. The binding conditions for the two conductive materials determine the length between the configurations and the radius of the conductive material. When the one-electron tunneling phenomenon is used, if the radius of the conductive material is about 100 angstroms, the distance between the conductive materials is about 230 angstrom. When the classical diffusion of one atom is used and the radius of the conductive material is about 5 to 10 angstroms, the distance between the conductive materials is about 5 to 30 angstroms. The conductive materials 20, 40 and 50 arranged at predetermined positions have a special function and are provided with an input 10 for a logical operation and an output with a logical operation result 50. 6
There is 0. Other conductive materials 20, 40 and 5
0 is used to perform a logical operation.

In FIG. 1, there are two conductive materials to which inputs for logical operation are performed, and one conductive material to which the result of logical operation is output. That is, the logic circuit 70
Can be said to be a two-input, one-output logical operation gate.

Generally, the logic circuit 70 has multiple inputs and multiple outputs. In the present invention, the excess state of one particle or one electron in the conductive material corresponds to the logical "1", and the normal state corresponds to the logical "0". It is assumed that the state in which electrons are introduced into the conductive substance 10 at a certain time interval by applying a negative potential to the conductive substance 10 for inputting a predetermined signal is the state of “1” in the input. The time interval at which the electrons are introduced is determined by the magnitude of the applied potential. The introduced electrons cause the conductive material networks 20, 40 and 5
Whether or not the conductive substance 60 for propagating between 0s and finally reaching the signal output can be reached corresponds to 1 or 0 of the logical operation result.

FIG. 2 shows an output result 60 of the logic circuit 70 shown in FIG. 1 for a predetermined input condition 10. (Fig. 1
An embodiment of the OR gate according to the present invention is shown in FIG. Also,
FIG. 3 shows the logical operation of the NOT gate, and FIG. 4 shows its truth table. The OR gate shown in FIG. 1 outputs one operation result 60 to two inputs 10. 5 or 6
The details of the circuit operation when the conductive material shown in FIG. 2 performs the operation shown in FIG. 2 will be described with reference to FIGS. 10, 11 and 12. As shown in FIG. 10, the input signal 2002 is "
When the input signal 2003 is 1 ”and the input signal 2003 is“ 0 ”, the particles take the propagation path 2001 indicated by the thick line.
0 becomes "1".

Next, as shown in FIG. 11, the input signal 20
When 02 is “0” and the input signal 2003 is “1”, the particles take the propagation path 2001 indicated by the thick line. Therefore, the output signal 2000 becomes "1". Further, as shown in FIG. 12, the input signal 2002 is "1" and the input signal 2003 is "
In the case of 1 ″, the particle takes a propagation path 2001 indicated by a thick line. In 2005, 2002 and 2003 fall within the effective repulsive force range.
Particles entered from enter and collide with each other due to interaction. Therefore, when two particles come out of 2004, the route of 2005 or 2007 is taken, and the route of 2006 does not pass. As a result, it will take any arbitrary route of 2008. Therefore, the output signal 2000 becomes "1". The part of 2008 is 20
Either particle from the 05 and 2006 paths
It may be configured to have at least one path that passes to 0, and this is possible as shown in the later arrangement configuration.
Here, the input signal 2002 is “0”, and the input signal 2003
If is "0", no particle propagation occurs. Therefore, the output signal 2000 becomes "0". From the above, it can be seen that the arrangement shown in FIG. 1 becomes an OR gate.

FIG. 3 shows details of the circuit operation of an embodiment of the NOT gate according to the present invention. Further, FIG. 4 shows the logical operation of the NOT gate. The NOT gate shown in FIG. 3 outputs one operation result 60 to one input 10. However, unlike the OR gate, the constant input 2003 of the signal "1"
Is done. The reason why the arrangement of the conductive material shown in FIG. 3 gives the calculation shown in FIG. 4 will be described below with reference to FIGS. 14 and 15. As shown in FIG. 14, the input signal 2002 is "
In the case of 0 ″, the particle takes the propagation path 2100 indicated by the thick line by only the constant input 2003. Therefore, the output signal 20
00 becomes "1". Further, as shown in FIG. 15, when the input signal 2003 is “1”, the particle passes through the propagation path 2005 or 2007 indicated by the thick line, but does not pass through 2006. This is within the effective repulsive force 2004 to 2002 and 2
This is because the particles entered from 003 enter, collide with each other in 2004 by some kind of interaction, and when two particles exit from 2004, they cannot pass through the path 2006. As a result, route 2006 does not lead to route 2100, which must be traversed to pass 2000. Therefore, the output signal 2000 becomes "0". From the above, FIG.
It can be seen that the arrangement shown in is a NOT gate.

Further, referring to FIG. 13, in the present invention,
An example of FANOUT is shown. In 2008, the paths are set up with sufficient distance so that no interaction occurs between the paths that the particles can pass through. Input of logic operation of FANOUT is 1
It is sufficient if there are two output terminals whose output is 1 when, and output 0 when input is 0. When the input signal 2002 is “1”, particles are detected as two output signals 2200 and 2210 with a finite equal probability. In this logic circuit,
The particles continue to be introduced for a fixed time interval, which is much longer than the electron introduction time interval, so that the two output signals are both "1". Input signal 20
When 03 is "0", the two output signals are both "0". From the above, it can be seen that the arrangement shown in FIG. 13 realizes the function of FANOUT.

An embodiment of the wire according to the present invention will be described. It represents a wire that transports particles with zero delay. Since a wire with zero delay needs to transport electrons on a straight line, it is possible by placing a substance that sets the route so that the particle route is taken on a straight line and making the placement interval sufficiently small. A wire for transporting particles with a delay N is possible by displacing the corresponding path from a straight path. Here, the delay N indicates that when traveling the same distance in the lateral direction, there is a need for a path along which particles travel N time units. FIG. 13 shows a wire for transporting electrons with a delay of 3. As described above, signal delay can be realized by using various wires.

An example of the operation in the case of the cylindrical honeycomb structure will be described. The structure of the logic circuit of Japanese Patent Application No. 6-27710 is
It is as shown in FIG. Logic circuit 50 shown in FIG.
05 operates as a NOR gate. Hereinafter, the logic circuit 5
The configuration of 005 will be described. In the logic circuit 5005, a two-dimensional plane of a substrate on which elements are arranged is divided into a plurality of regular hexagons, and a predetermined vertex of each regular hexagon has a vertex and a center of a circle of a bottom surface of a cylindrical conductive material. Place the conductive material so that they match. The vertices on which the conductive material is placed depends on the desired logic. When two conductive materials are arranged on the same side of one regular hexagon, these two adjacent conductive materials are connected by a one-electron tunneling phenomenon with a minute gap, and other arrangements. In the case of, the coupling between the conductive materials due to the tunnel phenomenon does not occur. Due to the existence of the coupling by the one-electron tunnel, a signal, that is, one electron can propagate between the conductive substances without wiring.

FIG. 5 and FIG. 6 are bird's-eye views when a gate is formed by using conductive materials arranged on a two-dimensional plane. The following is an example of a processing technique for regularly arranging the substances shown in FIGS. 5 and 6. First, a silicon oxide film is deposited on a silicon substrate using CVD. After that, a round hole is made in the oxide film by a photoresist process. After that, tungsten silicide is selectively grown only inside the hole where the oxide film is removed. Finally, by removing the oxide film, the substances can be regularly arranged. In particular, when they are arranged by atoms or atomic clusters, they can be arranged by an electron scanning tunneling microscope or a field emission microscope. When a GaAs substrate is used, the same processing technique is used to selectively grow GaAs instead of tungsten silicide. This processing technique is a technique used when creating quantum dots.

An embodiment of the operation of the input / output circuit will be described. In the input / output circuit of FIG. 1, as a peripheral circuit which is an interface with an external signal of one electronic circuit, as shown in FIG. 50, a point defect trap and a lead wire are arranged in the input / output portion. It is known that trapping one electron in a trap site causes a change in resistance of a very thin wire by several orders of magnitude (K. Raals, Phys. Rev. Lett. 228 (1984)). Further, by increasing the number of trapping sites, the trapping efficiency of the one-electron trap can be almost perfected.

In order to increase the sensitivity of the wire, it is preferable that the thickness of the wire be such that Anderson localization occurs in which the electrons are localized in a one-dimensional system in which the potential received by the electrons is random. 1000nm ×
Although the thickness is about 1000 nm, the sensitivity can be increased by utilizing the characteristics of the semimetal by using the carbon nanostructure having the spiral structure. Reference numerals 5000 and 5009 in FIG. 50 are portions corresponding to a source and a drain for applying a voltage. Two wires 5001 for determining the input side address
And 5002 are applied to inject the electrons at the trap site of 5003 into the one-electron tunnel network. The result obtained thereby captures the electron at the trap site of 5006 as a variation of the wires of two wires 55008 and 5009 for determining the output side address.

In the case of three dimensions, the same determination can be made,
This state is shown in FIG. In FIG. 51, 5100 and 51
Reference numeral 09 is a portion corresponding to a source and a drain for applying a voltage. A voltage is applied to the two wires 5101 and 5102 for determining the address on the input side, and electrons at the trap site of 5103 are injected into the one-electron tunnel network. The result obtained thereby is captured as an electron at the trap site of 5106 as a variation of the wires of two wires 5108 and 5109 for determining the output side address.

In both the two-dimensional and three-dimensional cases, the address designating method can be determined by the well-known method of designating the address of the random access memory as shown in FIG. A voltage is applied to the two wires so that a large voltage is applied where they cross each other, and at that time, electrons are emitted from the trap position. Further, at the time of reading, in the wire lattice drawn on the mesh, the wire whose voltage is raised by the entry of electrons may be found by the column and row detectors. The wire may be extremely thin and one-dimensionally visible. The material may be a semiconductor quantum wire or a carbon nanotube other than metal.

Further, a voltage may be applied in the direction of 5004 in FIG. 50 so that the electric field is parallel to one side of the hexagon in the honeycomb structure. When a conducting material is placed at the T site position of the BCC structure, which will be described later, for the simplest handling, the voltage should be set so that the electric field is in the (111) direction of the BCC structure like 5104 in FIG. Good. This way
Since the T sites are on the (100) plane of the BCC structure, the voltage applied at each site is uniform. This makes the three-dimensional circuit more compact. Further, as in the embodiment, if the potential is set so that the electric field is applied in the direction of 506 in FIG. 16, it is easy to grasp the image of movement.

The operating conditions of a logic circuit in which spherical conductive materials are arranged in a three-dimensional space will be described below. In the non-wiring logic circuit of the present invention, the microcapacitor C is formed between two spherical conductive materials. If the radius of the sphere is a, the distance between the surfaces of the two spheres is d, and the dielectric constant at the distance is ε ₁ , the capacitance c of the microcapacitor with the surfaces of the two spheres facing each other as c is πε It is given by ₁ a · log (2 a / d). However, a >> d, and log is a natural logarithm. If nothing is inserted between the two conductive materials, ε ₁
Is the dielectric constant ε ₀ of the vacuum.

The coupling condition of the two conductive materials by the one-electron tunnel phenomenon determines the radius a and the distance d of the conductive materials. Radius a of conductive material is 100 angstrom
If the distance d between the surfaces of the two spheres is approximately (Å) and is 30 angstroms (Å), the femtofarad (condition that the above-mentioned one-electron tunnel occurs under the condition that the potential difference is approximately 0.1 V and the temperature is approximately 100 K ( c of about fF) is obtained, and at that time, the distance D (= 2a + d) between the centers of the two spheres is about 230 angstrom (Å).

In order to understand the operation of the logic circuit of the present invention, first, the physical phenomenon which is the background of the present invention will be described with reference to FIGS. 7, 8 and 9. As shown in FIG. 7, when a potential capable of one-electron tunneling is applied to a plurality of conductive material columns as shown in FIG. 50, the electrons 1402 introduced into the conductive material 103 for signal input are , Propagates toward the conductive material 505a having a lower energy level 1401, and further propagates to the conductive materials 505b, c, and d. This state is generally called a state where the coulomb brocade is released. In the case of FIG. 7, conductive materials 103 to 5
A sufficient potential is applied such that the direction of the potential gradient does not change even if one electron propagates to 05a. Conversely, FIG.
Since the applied potential is small, the electrons tunnel from the conductive material 103 to 505a, as shown in FIG.
When the energy of the conductive material 505a is higher than that of the conductive material 103, electron tunneling is prohibited. This state is called the Coulomb Brocade state. The physical phenomenon in which the tunneling of electrons is controlled by the magnitude of the applied potential is called a single-electron tunneling phenomenon. The threshold voltage Vt that defines the transition between the above two states is given by | Vt | = e / (2c) as described above.

From the above, the one-electron tunnel phenomenon can be said to be a physical phenomenon in which electrons propagate in the direction of lower energy. Against the background of this one-electron tunnel phenomenon,
The physical phenomenon shown in FIG. 9 plays an important role in the present invention. Consider the applied potential condition (| V |> | Vt |) where the Coulomb blockade is released. In this case, when two electrons enter from one conductive material 505a to one conductive material 505b, the applied potential condition in which the energy is high due to Coulomb interaction between the two electrons is realized as follows. It

When the potential difference between two adjacent conductive substances shown in FIG. 7 is ΔV, the energy increment δ ₁ due to one electron entering the conductive substance, and the Coulomb interaction acting between the two electrons. Energy increment δ
₂ is expressed by the following equations 1 and 2 in terms of voltage.

Δ ₁ = e / (2c) (δ ₁ <| ΔV |) (Equation 1) δ ₂ = e / (4πε ₂ a) (δ ₁ + δ ₂ > | ΔV |) (Equation 2) Here, ε ₂ is the dielectric constant of the conductive material. (Equation 1) is
As shown in FIG. 7, even if one electron moves to the adjacent conductive substance, the potential does not become higher than the potential of the conductive substance before the movement, and the direction of the potential gradient does not change. (Equation 2) is (Equation 1)
In addition to the energy increment shown by, as shown in FIG.
Energy increase due to Coulomb interaction by two electrons causes the energy increment to become larger than the potential difference between two adjacent conducting materials, indicating that two electrons cannot enter the same conducting material. . From (Equation 1) and (Equation 2), the conditions that ΔV must satisfy are as follows.
It is shown by (Equation 3). δ ₁ <| ΔV | <δ ₁ + δ ₂ (Equation 3) In the above, as shown in FIG. 7, the case where a plurality of conductive substances are arranged in a one-dimensional direction was considered. In a logic circuit, a plurality of conductive materials are arranged on a two-dimensional plane, and the direction cosine with respect to the voltage application direction is 1 / r.
Since adjacent conductive materials also exist in the direction of (r> 1), the potential difference between the two conductive materials in that case is
If the potential gradient is uniform in the voltage application direction, ΔV / r
Therefore, the condition of (Equation 1) is δ ₁ <| ΔV | / r (Equation 4). From the conditions of (Equation 4) and (Equation 2), the condition of (Equation 3) is changed as follows.

In order for ΔV to satisfy the condition of rδ ₁ <| ΔV | <δ ₁ + δ ₂ (Equation 5) (Equation 5), (r−
1) δ ₁ <δ ₂ is required. Therefore, using the equation that represents the capacitance c of the microcapacitor already obtained, (r-
1) δ ₁ <δ ₂ is expressed by the following equation. (ε ₂ / ε ₁ ) <log (2a / d) / (2 (r-1)) (Equation 6) (ε ₂ / ε ₁ ) is the ratio of the permittivity of the conductive material to the spacing. It is a value of about 1 to 10.

Furthermore, if the equation expressing the electrostatic capacitance c of the minute capacitor is used for the temperature condition T <e ² / (2ck) at which one electron can be tunneled, the following (Equation 7) is obtained. e ² / (kT)> 2πε ₁ a · log (2a / d) (Equation 7) When the radius a of the spherical conductive material is given, (Equation 6)
From (Equation 7), the following equation is obtained as a condition that the interval d satisfies. 2 (r-1) (ε ₂ / ε ₁ ) <log (2a / d) <e ² / (2πε ₁ akT) (Equation 8) Also, in order for d to satisfy the condition of (Equation 8), ,
The relationship between the upper and lower limits of (Equation 8) is 2 (r-1) (ε ₂ / ε ₁ )
It is necessary to satisfy <e ² / (2πε ₁ akT). From this condition, the upper limit of the operating temperature determined by the radius a of the sphere is expressed as follows. T <e ² / (4πε ₂ ak (r-1)) (Equation 9) FIG. 9 shows a conductive material arranged in a one-dimensional manner. When materials are arranged, electrons may try to enter one conductive material from different directions. In this case, due to the mechanism shown in FIG. 9, that is, Coulomb brocade and Coulomb interaction, two electrons cannot both enter the conductive material.

FIG. 4 shows an embodiment of a method for producing a three-dimensional circuit network.
9 shows. In FIG. 49, the black circles indicate the positions where conductive materials are placed, and the gray (hatched) circles indicate the positions where substances are placed when making a BCC (body-centered cubic lattice. White circles indicate the substrate (4900-4905).
Shows the position where the same insulator is placed. The following is an example of a processing technique for regularly arranging substances to form the logic circuit shown by the thick solid line shown in FIG.

First, a silicon oxide film is deposited on the 4905 silicon substrate by CVD. The deposited thickness is 49
All of 00 to 4905 are ¼ of the distance a between square lattice distances between BCC lattices. Regarding 4905, a conductive material different from the conductive material conductor placed in the black circles at the BCC lattice position may be placed and used for shielding between the T positions. If you don't, put nothing in 4905. Next, 4904 silicon oxide is film-deposited. At this time, 4 for the BCC lattice
The following operations are performed to place the conductive material in the positions indicated by black circles 904. After that, a round hole is formed in the oxide film at the position of a black circle by a photoresist process. After that, tungsten silicide is selectively grown only inside the hole where the oxide film is removed.

Finally, the substance can be regularly arranged by removing the oxide film. Where 4910
The insets from 4 to 4915 all show the positional relationship seen from above. 4903, 4902, 4901, and 4900
Also, place the conductive material in the black circle, the same material as the substrate in the white circle, and place a different material from the one placed in the black circle in the position of the gray circle as needed. In this way, the conductive material is placed at the positions of black circles by depositing, drilling, and selective growth from 4900 to 4905. Then, the NOT circuit shown in the lower part of FIG. 49 is formed by the thick line formed by connecting the black circles. Other circuits and connection of circuits are possible by arranging the conductive materials two-dimensionally at positions shifted by a / 4 as described above.

Instead of selective growth, atoms or atomic clusters can be directly arranged by moving and arranging them by an electron scanning tunneling microscope or a field emission microscope. As a result, the shape as shown in FIGS. 41, 42, and 43 can be formed from a thin silicon oxide film, and the conductive material can be arranged at the apex position.

When a GaAs substrate is used instead of silicon, the same processing technique is used to selectively grow GaAs instead of tungsten silicide. This processing technique is a technique used when creating quantum dots.

An embodiment of the three-dimensional circuit network will be described. FIG.
An embodiment of a three-dimensional non-wiring logic circuit according to the present invention is shown in FIG. The logic circuit shown by the thick solid line in FIG. 21 operates as an OR gate as shown in FIG. The configuration of the logic circuit will be described below.

An example of a three-dimensional arrangement capable of controlling the propagation of one electron will be shown. A general three-dimensional arrangement structure is also possible. It is shown that a three-dimensional circuit network can be easily manufactured because there is no need to worry about wiring. The number of terminals changes depending on the coordination number of the layout structure (the number of nearest layouts). For a face-centered cubic lattice, the coordination number is 12. Here, a case where a space is divided at a tetrahedral position (here, abbreviated as T position) called 12 (d) position obtained from a body-centered cubic lattice (black circle position in FIG. 1) is formed. deal with.

The closest distances between the T positions are all equal. With this arrangement, the density is extremely high, and since it is easy to make with the current processing technology, the lattice can be efficiently assembled. When there are two black circles in one body-centered cubic lattice, there are 12 T positions.
There are four closest T-configurations for each T-position.
Therefore, the atomic clusters 17 that form a polyhedron close to a sphere
70 is obtained. An example in which a conductive material such as 1771 and 1772 is prepared and placed at the T position is shown. here,
The sphere at 1770 represents an atom. This atom need not be a metal, as long as the cluster is metallic.

The vertex at which the conductive material is placed (50 in FIG. 16)
5) depends on the desired logic. When the two conductive materials are arranged in the closest position, these two conductive materials are bonded by the one-electron tunnel phenomenon, and in other arrangements, there is no bond between the conductive materials by the tunnel phenomenon. . Due to the existence of the bond by this one-electron tunnel,
A signal, that is, one electron can propagate between conductive substances without wiring.

Furthermore, the coupling due to the one-electron tunneling phenomenon is
Since the conductive material is limited by the way of arrangement, the propagation of one electron can be controlled by changing the arrangement, so that a circuit having a logical operation function (FIG. 21) can be constructed. The coupling condition of the two conductive materials determines the distance between the closest lattice points and the radius of the conductive material. If the radius of the conductive material is 100 angstroms,
The length between the closest lattice points is about 230 Å.

The conductive substance placed at a predetermined position includes
As shown in FIG. 27, as having a special function,
There are an input 104 for inputting a logical operation 104, an input for inputting a fixed signal, that is, a constant, and an output 109 for outputting a logical operation result 108. The conductive material 105 other than these is used for performing a logical operation.

In FIG. 21, there are two conductive materials 104 to which an input for logical operation is performed, and one conductive material 109 to which a logical operation result is output. That is, the logic circuit can be said to be a two-input one-output logic operation gate. Generally, the logic circuit has multiple inputs and one output. Further, the input of the constant 103 is not always necessary depending on the desired logical operation.

In the present invention, the one-electron excess state in the conductive material is a logical "1", and the normal state is a logical "0".
Correspond to. It is assumed that the state where electrons are introduced into the conductive substance 104 at a certain time interval by applying a negative potential to the conductive substance 104 for inputting a predetermined signal is the state of “1”. The time interval at which the electrons are introduced is determined by the magnitude of the applied potential. The introduced electrons are
Whether or not the conductive material 108 propagates between the conductive materials 105 and finally reaches the conductive material 108 for signal output corresponds to 1 or 0 of the logical operation result. FIG. 2 shows the logic circuit 1 shown in FIG.
An output result 108 for a predetermined input condition 103 of 01 is shown.

In order to understand the operation of the logic circuit shown in FIG. 21, first, the physical phenomenon which is the background of the present invention will be described with reference to FIGS. 7, 8 and 9. As shown in FIG. 7, when a potential capable of one-electron tunneling is applied, the electrons 1402 introduced into the signal input conductive material 103 are
Lower conductive material 105 with energy level 1401
(1402). This state is generally called a state in which Coulomb Brocade is released.

On the contrary, as shown in FIG. 8, when the applied potential is small and the energy of electrons is high due to tunneling of electrons, tunneling of electrons is prohibited. This state is called the Coulomb Brocade state. The physical phenomenon in which the tunneling of electrons is controlled by the magnitude of the applied potential in this way is called a single-electron tunneling phenomenon.

From the above, the one-electron tunnel phenomenon is a physical phenomenon in which electrons propagate in the direction of lower energy. Against the background of this one-electron tunnel phenomenon, what plays an important role in the present invention is the physical phenomenon shown in FIG. Consider the applied potential condition in which the Coulomb blockade is released. In this case, when two electrons enter one conductive material, the applied potential condition in which the energy is high is easily realized.

FIG. 9 is a diagram in which the conductive materials are arranged one-dimensionally. However, when the conductive materials are arranged two-dimensionally or three-dimensionally, electrons are changed from one direction to another conductive material. You may try to enter. In this case, due to the mechanism shown in FIG. 9, namely Coulomb Brocade, two electrons are
Both cannot enter the conductive material. (However, when electrons are used for compensating the potential of the surroundings, it is not always necessary that the maximum number is two.) Conduction arranged three-dimensionally with reference to FIGS. 18, 19 and 20. The manner in which one electron propagates between volatile substances will be described. The arrangement of conductive materials shown in FIGS. 18, 19 and 20 is the basis for any conductive material arrangement in the present invention. FIG.
As shown in FIG. 8, consider the case where electrons are injected into the conductive material 1700. (In this case, the electric field is applied in the (100) direction. That is, the conductive material 1701,
There is a conductive material 1702 and a conductive material 1703 (10
The energy of the (100) plane on the opposite side of the 0) plane is higher by the amount of the external potential. That is, 5 in FIG.
The potential is set so that the electric field is applied in the direction of 06. ) This corresponds to the input of signal 1 to the conductive material 1700. In this case, the electrons pass through the conductive material 1704 one by one and have a probability of 1/4.
It flows into the conductive material 1711. It then flows from 1711 and 1704 to 1706. Further, the flow of electrons to the conductive material 1703 is prohibited because the energy of the conductive material 1707 is higher than that of the conductive material 1702. In addition, electron tunneling is prohibited when the conducting material is not in the closest position.

Next, FIG. 19 shows how electrons are propagated when a signal “1” is input to the conductive material 170 when a conductive material is arranged as in FIG. Also in this case
When the same consideration as in No. 8 is performed, the signal “1” is output to the conductive substance 1705 and the conductive substance 1708.

When a conductive substance is arranged in FIG. 20 as in FIGS. 18 and 19, when a signal “1” is input to the conductive substance 170 and a signal “1” is input to the conductive substance 1700. The state of electron propagation is shown. In this case, since there is a flow of electrons from both the conductive substance 1700 and the conductive substance 170, the behavior of one electron is considered in the cases of FIGS. 18 and 19, while the behavior of two electrons is considered. There is a need. In this case, the inflow of electrons into the conductive material 1705 is prohibited due to the physical phenomenon shown in FIG. Therefore, the signal “1” is output to the conductive material 1707 via the conductive material 1708, and the signal “1” is output to the conductive material 1705.
0 "is output.

From the above, it can be seen that the arrangement of the conductive materials shown in FIGS. 18, 19 and 20 is a circuit for performing the logical operation of EOR. Based on the basic layout shown here,
You can configure OR gates, NOT gates, FANOUTs, and even wires. If OR gates, NOT gates, FANOUTs, and wires can be configured, theoretically any logic circuit can be assembled.

FIG. 21 shows an embodiment of the OR gate according to the present invention. Further, FIG. 22 shows the logical operation of the OR gate. The OR gate shown in FIG. 21 outputs one operation result 108 to two inputs 103. The reason why the arrangement of the conductive material shown in FIG. 21 gives the calculation shown in FIG.
This will be described with reference to FIGS. 27, 28 and 29. As shown in FIG. 27, when the input p of the signal 103 is “1” and one input signal q is “0”, the electrons take the propagation path indicated by the thick line. Therefore, the output signal 108 becomes "1".

Next, as shown in FIG. 28, the input signal 10
When the input p of 3 is "0" and one input signal q is "1", the electrons pass through the propagation path indicated by the thick line. Therefore, the output signal 108 becomes "1". Further, as shown in FIG.
The input p of the signal 103 is "1", and one input signal q is "
In the case of "1", the electrons follow the propagation path indicated by the thick line. Therefore, the output signal 108 becomes "1". Here, the input p of the input signal 103 is "0", and one input signal q is "0". In the case of, no electron propagation occurs, so the output signal 10
8 becomes "0". From the above, it can be seen that the arrangement shown in FIG. 21 becomes an OR gate.

FIG. 23 shows an embodiment of the NOT gate according to the present invention. Further, FIG. 24 shows the logical operation of the NOT gate. The NOT gate shown in FIG. 23 has one input 103
In response, one calculation result 108 is output. However, OR
Unlike the gate, the constant input 106 of the signal "1" is performed. The reason why the arrangement of the conductive material shown in FIG. 23 gives the calculation shown in FIG. 24 will be described below with reference to FIGS. 31 and 32. As shown in FIG. 31, when the input signal 103 is “0”, the electrons take the propagation path indicated by the thick line only by the constant input 106. Therefore, the output signal 108 becomes "1". Further, as shown in FIG. 32, the input signal 103 is "
In the case of "1", the electron takes the propagation path 2001 indicated by the thick line. Therefore, the output signal 108 becomes "0". From the above, it is understood that the arrangement shown in FIG.

It can be understood that the logic circuit shown in FIG. 33 serves as a NOR gate because it is composed of an OR gate 2701 and a NOT gate 2702.

FIG. 25 shows the FA of the three-dimensional circuit according to the present invention.
An example of NOUT will be shown. Further, FIG. 26 shows a logical operation of FANOUT. When the input signal 103 is “1”, the electrons are detected as two output signals 108 with a probability of ½. In this logic circuit, the electrons continue to be introduced for a fixed time interval, and this time interval is set to be much longer than the time interval for the introduction of electrons, so that the two output signals are both "
When the input signal 103 is "0", the two output signals are both "0". From the above, it can be seen that the arrangement shown in Fig. 25 realizes the function of FANOUT.

Next, an embodiment of the wire according to the present invention will be described with reference to FIG. A wire that transports electrons with zero delay can be represented by a straight line. A zero lag wire is required to transport electrons in a straight line, so exceptionally conductive material can be achieved with the arrangement of 3005, which is placed through the center of 3001, 3002, 3003, 3004. Figure 30
The dashed lines passing through 3002, 3001 and 3004 at ## EQU3 ## represent wires for transporting electrons with a delay of 2. Here, the delay 1 indicates that, when traveling the same distance in the lateral direction, it is necessary for the electron to travel one distance closer to the closest position of the T position than in the case of FIG. As described above, control of signal delay can be realized by using various wires.

In Japanese Patent Application No. 6-27710, the lattice is assembled in each of the regular six shapes, but the conditions can be more relaxed. FIG.
As shown in, the OR (3501) and NOT (3502) gates can be built on a random lattice keeping almost the same distance. In FIG. 35, the white ellipses are 3511 and 351.
It is shown that the electrons at the positions 2, or 3513 and 3514 are scattered. In the case of the NOT gate, when the input P is 1, electrons cannot pass to 3503 due to the interaction, and the output becomes 0.

FIG. 36 shows a mechanism of increasing the capacitance by blocking and affecting surrounding electrons when the electrons move. The shielding effect increases the dielectric constant, making it difficult for single-electron tunnels to occur, but the effect of making tunnel movements that occur at one location less likely to occur at other locations, or vice versa. There is. When another electron moves in the same direction as the tunnel movement direction as shown in FIG. 36, it facilitates tunnel movement at another position in this direction at another place. When another electron moves in the direction perpendicular to the tunnel movement direction as shown in FIG. 36, it makes it difficult for the tunnel movement to occur in another place. Therefore, if the circuit network according to the present invention is sandwiched between ferroelectric layers, interference between layers can be suppressed, and the circuit network can be stacked in multiple layers.

Further, it is possible to intentionally cause interference between layers and exchange data between layers. A semiconductor having a low impurity concentration may be used in place of the ferroelectric substance, and hopping of electrons may be used to provide a shielding effect.
As shown in FIG. 37, at the T position, electrons are caused to move at the position of 500, which corresponds to the body-centered cubic lattice, by the atom or only in it, and the effect of polarization is caused, or the atom is oscillated, so that the atom moves only in a certain direction. Increasing the amplitude of vibration can also provide a shielding effect. By adding such an additional function, it becomes possible to adjust the frequency of transfer of electrons between conductive materials and the time required for transfer. By allowing these polarizations to occur uniformly, the performance of the entire network can be changed or improved.

In addition, by adjusting the polarization shown in FIG. 36 or 37 to occur in a fairly limited region, the frequency of electron transfer between certain portions of the conductive material and the time required for the transfer can be adjusted. Will be possible. As a result, it is possible to improve the performance of the network by changing the departure, flight or arrival time of the electron conductive material and adjusting the timing.

As shown in FIG. 35, not only hexagons but also 3
The present invention is also effective for a random lattice including corners, 4 corners, 5 corners, 7 corners, 8 corners, 9 corners, and the like. On the tube, on the tube,
The circuit can be configured by a tubular shape or a spiral shape as shown in FIGS. 41 and 42, or a sponge-like three-dimensional body formed only by the negative curved surface shown in FIG. If a conductive material is placed at the apex of each polygon, the NOR and OR gates can be assembled.

Although the classical operating principle has been dealt with above, four outputs correspond to two inputs A and B in the logic using the collision of brown particles as shown in FIG. Also in the present invention, as shown by 45, it is possible to make four inputs correspond to two inputs A and B by changing the way of understanding the logic. Therefore, the three-dimensional quantum tunnel can handle the logic utilizing the collision of Brown particles in the non-wiring logic network. Circuits that follow quantum logic can also be created by further highlighting the quantum mechanical aspects of the three-dimensional electron tunneling effect.
Whether or not it is at one position can be stochastically determined by quantum mechanics. Further, as shown in FIGS. 46, 47 and 48, the circuit can be constructed based on an interaction mechanism corresponding to FIGS. 18, 19 and 20.

[0074]

According to the present invention, it is possible to provide a logical operation circuit that does not require wiring between transistors, which is normally performed, by disposing a plurality of conductive materials coupled by the one-electron tunnel phenomenon at predetermined positions. . The effects of no wiring are as follows: 1) Reduce the wiring capacitance that becomes stray capacitance with respect to the tunnel junction capacitance, and enhance the stability and reliability of the one-electron tunnel phenomenon. 2) Reduce the wiring area required for wiring. However, the promotion of the integration of logic circuits using the one-electron tunnel phenomenon is mentioned.

Further, in the present invention, since the OR gate, NOT gate, FANOUT and wire, which are the basic units for the construction of the logic circuit, can be generated, an arbitrary non-wiring logic circuit can be constructed. In particular, when a circuit is constructed in two dimensions, the delay time becomes large due to the difference in the length of the signal transmission path, and the disadvantage that high integration is difficult due to two dimensions compared to the case of three dimensions is avoided. it can.

Furthermore, in the case of two dimensions, there is no change in the order parameter peculiar to the two-dimensional Coulomb system, and there is a Kosterlits-Thouless transition in which the susceptibility which is the second derivative of energy with respect to temperature diverges. The problem of impairing the reliability of the circuit can also be avoided. Further, in the conventional technique, the margin of the dimension and the like due to the processing had to be extremely small, but the present invention enables the margin of the dimension and the like to be large.

[Brief description of drawings]

FIG. 1 is an example of an OR gate configured according to the present invention.

FIG. 2 is an example of a logical operation using an OR gate.

FIG. 3 is an example of a NOT gate constructed in accordance with the present invention.

FIG. 4 is an example of a logical operation using a NOT gate.

FIG. 5 is a plan view of a circuit network.

FIG. 6 is a bird's eye view of a circuit network.

FIG. 7 is an explanatory diagram 1 of a physical background for realizing the logical operation circuit of the present invention.

FIG. 8 is an explanatory diagram 2 of a physical background for realizing the logical operation circuit of the present invention.

FIG. 9 is an explanatory diagram 3 of a physical background for realizing the logical operation circuit of the present invention.

FIG. 10 is an explanatory diagram 1 of signal propagation in an OR gate configured according to the present invention.

FIG. 11 is an explanatory diagram 2 of signal propagation in the OR gate configured according to the present invention.

FIG. 12 is an explanatory diagram 3 of signal propagation in an OR gate configured according to the present invention.

FIG. 13 is an embodiment of FANOUT constructed according to the present invention.

FIG. 14 is an explanatory diagram 1 of signal propagation in a NOT gate configured according to the present invention.

FIG. 15 is an explanatory diagram 2 of signal propagation in the NOT gate configured according to the present invention.

FIG. 16 is an explanatory diagram of a three-dimensional circuit network constructed according to the present invention.

FIG. 17 is a sphere-like polyhedron constructed according to the present invention.

FIG. 18 is an explanatory diagram 1 of a physical background for realizing the logical operation three-dimensional circuit of the present invention.

FIG. 19 is an explanatory diagram 2 of a physical background in which the logical operation three-dimensional circuit of the present invention is realized.

FIG. 20 is an explanatory diagram 3 of a physical background in which the logical operation three-dimensional circuit of the present invention is realized.

FIG. 21 is an example of a three-dimensional OR gate configured according to the present invention.

FIG. 22 is an example of a three-dimensional OR logical operation constructed according to the present invention.

FIG. 23 is an example of a three-dimensional NOT gate constructed according to the present invention.

FIG. 24 is an example of a three-dimensional NOT logical operation constructed according to the present invention.

FIG. 25 is an example of a three-dimensional FANOUT gate configured according to the present invention.

FIG. 26 is an example of a three-dimensional FANOUT logical operation constructed according to the present invention.

FIG. 27 is an explanatory diagram 1 of signal propagation in a three-dimensional OR gate configured according to the present invention.

FIG. 28 is an explanatory diagram 2 of signal propagation in the three-dimensional OR gate configured according to the present invention.

FIG. 29 is an explanatory diagram 3 of signal propagation in a three-dimensional OR gate configured according to the present invention.

FIG. 30 is an explanatory diagram of signal propagation in a three-dimensional wire configured according to the present invention.

FIG. 31 is an explanatory diagram 1 of signal propagation in the three-dimensional NOT gate configured according to the present invention.

FIG. 32 is an explanatory diagram 2 of signal propagation in the three-dimensional NOT gate configured according to the present invention.

FIG. 33 is a first example of signal propagation in a three-dimensional NOR gate configured according to the present invention.

FIG. 34 is a second example of signal propagation in a three-dimensional NOR gate configured according to the present invention.

FIG. 35 is a second embodiment of the OR gate and the NOT gate in the two-dimensional random lattice constructed according to the present invention.

FIG. 36 is an explanatory diagram 1 of the use of the shielding effect constructed according to the present invention.

FIG. 37 is an explanatory diagram 2 of the use of the shielding effect constructed according to the present invention.

FIG. 38 is a structural example of a circuit network configured according to the present invention.

FIG. 39 is a structural example of a spherical circuit network configured according to the present invention.

FIG. 40 is a structural example of a tubular network constructed according to the present invention.

FIG. 41 is a configuration example 1 of a torus circuit network configured according to the present invention.

FIG. 42 is a second embodiment of the configuration of the torus circuit network constructed according to the present invention.

FIG. 43 is a structural example of a sponge-like network having negative curvature constructed according to the present invention.

FIG. 44 is a collision-type logic for a billiard ball that can be constructed in accordance with the present invention.

FIG. 45 is an example of a billiard ball network that can be constructed in accordance with the present invention.

FIG. 46 is an explanatory diagram 1 of a state of interaction of the circuit network configured according to the present invention.

[Fig. 47] Fig. 47 is an explanatory diagram 2 of a state of interaction of a circuit network configured according to the present invention.

FIG. 48 is an explanatory diagram 3 of a state of interaction of a circuit network configured according to the present invention.

FIG. 49 is a schematic diagram of a manufacturing process of a circuit network configured according to the present invention.

FIG. 50 is an input / output interface diagram of the two-dimensional circuit network.

FIG. 51 is an input / output interface diagram of the three-dimensional circuit network.

FIG. 52 is a schematic diagram of an input / output circuit.

[Explanation of symbols]

70: Logic gate, 505: Lattice used to divide all planes for placing conductive material, 103: Input signal, 20: Conductive material for introducing input signal to logic gate, 1770: Polyhedron Forming conductive material, 30: conductive material for introducing constant signal into logic gate, 200
3: constant signal, 50: conductive substance for outputting logical operation result, 60: output signal.

Claims (13)

[Claims] 1. A logical operation circuit for performing a logical operation on a predetermined input, wherein a two-dimensional plane or a three-dimensional plane for arranging elements is divided by a random or regular lattice, and each lattice point is cylindrical or The conductive substance is arranged so that the centers of the conductive substance forming the polyhedron close to the sphere coincide with each other, and the one-electron excess state in the conductive substance is logically "1".
In addition, the state where there is no excess electrons is made to correspond to a logical "0", and the case where an electron introduced into a predetermined conductive substance for signal input can reach the conductive substance for signal output is calculated as "logical operation".
1 ", a non-wiring logic operation circuit characterized by performing a logic operation in correspondence with" 0 "of a logic operation when it cannot be reached. 2. In a logic operation circuit for performing a logic operation on a predetermined input, a conductive material having a polyhedron shape similar to a cylinder or a sphere is arranged on a two-dimensional plane or a three-dimensional plane for arranging elements, and the conduction is performed. Place a sexual substance. The two conductive materials are within the effective scattering distance, and the conductive materials are bonded by the one-electron tunneling phenomenon. The one-electron excess state in 1 corresponds to the logic "1", and the state without excess electrons corresponds to the logic "0", and the electrons introduced into the predetermined conductive material for signal input are conducted for signal output. A non-wiring logical operation circuit characterized in that a logical operation is performed by making a logical operation "1" when it can reach a functional substance and a logical operation "0" when it cannot be reached. 3. A logic operation circuit for performing a logic operation on a predetermined input, wherein a conductive material forming a polyhedron which is a cylinder or a sphere is arranged on a two-dimensional plane or a three-dimensional plane for arranging elements, and conduction is performed. Place a sexual substance. Two conductive materials within a certain distance are connected by a one-electron tunneling phenomenon, and it is arranged so as not to bond between conductive materials over a certain distance, and within the effective scattering distance. The operating condition of the circuit is set so that two or more electrons do not enter, and the one-electron excess state in the conductive substance is logical
1 ”corresponds to the state of no excess electrons to“ 0 ”of the logic, and the case where the electrons introduced into the predetermined conductive material for signal input can reach the conductive material for signal output A non-wiring logical operation circuit characterized by performing a logical operation by correlating "1" and "0" when it cannot be reached with a logical operation "0". 4. A logic operation circuit for performing a logic operation with respect to a predetermined input, wherein a conductive material forming a polyhedron having a shape of a cylinder or a sphere is arranged on a two-dimensional plane or a three-dimensional plane for arranging elements and conducts. Place a sexual substance. Two conductive materials within a certain distance are connected by a one-electron tunneling phenomenon, and it is arranged so as not to bond between conductive materials over a certain distance, and within the effective scattering distance. The operating condition of the circuit is set so that two or more electrons do not enter, and the one-electron excess state in the conductive substance is logical
1 ”corresponds to the state of no excess electrons to“ 0 ”of the logic, and the case where the electrons introduced into the predetermined conductive material for signal input can reach the conductive material for signal output A non-wiring logical operation circuit characterized by performing a logical operation by correlating "1" and "0" when it cannot be reached with a logical operation "0". 5. A logical operation circuit for performing a logical operation on a predetermined input, wherein a two-dimensional plane or a three-dimensional plane for arranging elements is divided so that the grid point distances are equal, and each grid point is divided. , The conductive material is arranged so that the centers of the conductive material forming a columnar shape or a polyhedron close to a sphere coincide with each other, and the one-electron excess state in the conductive material is logically determined.
1 ”corresponds to the state of no excess electrons to“ 0 ”of the logic, and the case where the electrons introduced into the predetermined conductive material for signal input can reach the conductive material for signal output A non-wiring logical operation circuit characterized by performing a logical operation by correlating "1" and "0" when it cannot be reached with a logical operation "0". 6. A logical operation circuit for performing a logical operation on a predetermined input, wherein a two-dimensional plane or a three-dimensional plane for arranging elements is divided at regular grid points, and each grid point has a cylindrical shape or The conductive substances are arranged so that the centers of the conductive substances forming a polyhedron close to the sphere coincide with each other, and the one-electron excess state in the conductive substance is the logical "1", and the state without excess electrons is the logical " Corresponding to "0", a logical operation is "1" when an electron introduced into a predetermined signal input conductive material can reach the signal output conductive material, and a logical operation "0" when it cannot be reached. "A non-wiring logic operation circuit characterized by performing a logic operation in accordance with". 7. The conductive substance arranged so that the apex and the center thereof are coincident with each other are coupled by a tunnel phenomenon between the conductive substances arranged at the closest distance, and in the case of other arrangements, the conductivity is reduced. 2. The non-wiring logic operation circuit according to claim 1, having a size such that coupling due to a tunnel phenomenon between substances is eliminated. 8. The logic circuit is operated under an operating condition in which electrons inputted into the signal input conductive material cannot enter into the same conductive material more than once. The non-wiring logic operation circuit according to claim 1. 9. A logic circuit is operated under an operating condition in which electrons input to the conductive material for signal input cannot enter more than one in the same conductive material. When an electron moves between the two, it causes the movement of the electron only in the atom or in it, and has the effect of polarization, or vibrates the atom, and increases the amplitude of the vibration in a certain direction. The effect of electron transfer that occurred at one position makes it difficult to cause electron transfer at other positions, and conversely makes it easy to cause
2. The non-wiring logic operation circuit according to claim 1, wherein the performance of a part or the whole circuit is controlled by changing the departure, flight or arrival time of the electron conductive material and adjusting the timing. 10. A logic circuit is operated under an operating condition in which electrons input to the signal input conductive material cannot enter into the same conductive material more than once. If sandwiched between dielectric layers, the interference between layers can be suppressed, and the network can be stacked in multiple layers. The communication of the communication is possible.
The described non-wiring logical operation circuit. 11. A scattering direction of two or more electrons under an operating condition in which electrons input to the signal input conductive material cannot enter the same conductive material. 2. The non-wiring logic operation circuit according to claim 1, wherein a billiard ball type logic circuit is operated by determining the logic of an electron input by. 12. A scattering direction of two or more electrons under an operating condition in which electrons input to the signal input conductive material cannot enter the same conductive material. 2. The non-wiring logic operation circuit according to claim 1, wherein the logic circuit is operated by probabilistically determining the logic of the electron input by the quantum mechanics. 13. When a circuit network is stretched on the flat surface or curved surface,
2. The non-wiring logic according to claim 1, wherein a hexagon is used as a base, and by inserting 2, 3, 4, 5, 7, 8, and 9 polygons, the distances between the conductive materials are substantially evenly arranged. Arithmetic circuit.