JPH0864796A - Manufacture of solid-state image sensing device - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a solid-state image sensing device equipped with a CMD lessened in dispersion of an output current or a dark current. CONSTITUTION: An N-type channel layer 2 is formed on a<-> -type semiconductor substrate 1, and a thermal oxide film 3 is formed thereon. Then, a positive-type resist pattern 11 similar to a gate electrode in effective shape is formed, phosphorus ions are implanted for the formation of N-type diffusion regions 4 to serve as a source and a drain respectively, and the substrate 1 is annealed after the resist pattern 11 is removed. A gate oxide film is formed after the thermal oxide film 3 is removed, a polysilicon is deposited, lessened in resistance by a diffusion of N-type impurities, and formed into a gate electrode by photolithography and etching. Then, an oxide film is formed on all the sur-ace, then a source electrode is provided, and thus a CMD is finished.

Description

Detailed Description of the Invention

[0001]

This invention relates to a charge modulation device (Char
ge Modulation Device: abbreviated as CMD hereinafter) as a light receiving element.

[0002]

2. Description of the Related Art Conventionally, various solid-state image pickup devices having a light receiving element having a MIS type light receiving / accumulating portion have been proposed. For example, Japanese Patent Application Laid-Open No. 61-84059 discloses a solid-state imaging device using a CMD having a MIS type light receiving / accumulating portion and having an internal amplification function as a light receiving element.

Next, a solid-state image pickup device using a conventional CMD type CMD light receiving element will be described. FIG. 19 is a cross-sectional view showing the configuration of one pixel portion of a solid-state imaging device using a known CMD previously proposed by the applicant of the present application as a light receiving element. In FIG. 19, 101 is a P ⁻ type semiconductor substrate, and 102
Is an N ⁻ type channel layer formed of an N ⁻ type epitaxial layer grown on the semiconductor substrate 101 by an epitaxial method or the like. 103 is a gate oxide film having a thickness of 200 to 500 Å formed on the surface of the N ⁻ type channel layer 102. Reference numeral 104 denotes a gate electrode formed on the gate oxide film 103, which is made of, for example, polysilicon or the like and has a film thickness of about 1000 Å or less. Ten
Reference numeral 5 is a silicon oxide film formed on the gate electrode 104. Reference numerals 106 and 107 respectively denote an N ⁺ type source diffusion layer and an N ⁺ type drain diffusion layer, and a silicon oxide film 105 is formed on the entire surface.
The gate electrode 104 is formed in a self-aligned manner. Reference numeral 108 denotes a source electrode formed on the N ⁺ type source diffusion layer 106.

Next, the operation of the CMD light receiving element thus constructed will be briefly described. In FIG. 19, incident light 109 incident from above the gate electrode 104 causes N ⁻
Signal charge is generated in type channel layer 102, the signal charges (holes) directly below the gate electrode 104 N ^- -type channel layer 10
Deposit on the surface of 2. The N ⁺ type source diffusion layer 106 and the N ⁺ type drain diffusion layer 10 flowing in the N ⁻ type channel layer 102 are generated by the electric field generated by the accumulation of the signal charges.
It is designed to modulate the electron current between 7 and.

Further, the conventional CMD having the above-mentioned structure
In the light receiving element, as shown in FIG. 20, in order to simplify the wiring, the gate electrodes 201 for two pixels are connected by the coupling portion 202 and are integrally formed. In this case, a channel stopper region must be formed in order to electrically separate the photoelectric conversion units of the two pixels. Therefore, the gate electrode 201
A region 204 indicated by a dotted line is formed by ion-implanting an N-type impurity into a region 203 indicated by a solid line of the coupling part 202 of FIG.
Is the channel stopper region. The end portion 204a of the channel stopper region 204 also defines the end portion on the drain side that determines the effective gate length of the CMD light receiving element. In FIG. 20, 205 is an N ⁺ type source diffusion layer and 206 is an N ⁺ type drain diffusion layer.

[0006]

By the way, the conventional CM
In the D light receiving element, the N ⁺ type source / drain diffusion layer is formed in a self-aligned manner with the gate electrode by ion implantation or the like. The difference will depend on the difference in the remaining etching thickness of the gate oxide film. In fact, since the etching rate of the gate electrode has a non-uniform distribution in the wafer surface, the remaining thickness of the gate oxide film has a non-uniform distribution. This causes variations in the diffusion depth of the N ⁺ type source / drain diffusion layers, which causes variations in the electric field near the gate end, resulting in variations in the output current and the dark current. These variations cause fixed pattern noise (FPN) and image quality roughness.

When the channel stopper region is formed by ion implantation in a process different from the ion implantation for forming the N ⁺ type source / drain diffusion layer as described above, the N type on the drain side constituting the channel stopper region is formed. The effective gate length of the CMD, which is defined by the lateral expansion of the diffusion layer, tends to be different between adjacent pixels due to the positional shift in the photolithography process. This difference in the effective gate length causes a problem that it becomes an FPN and deteriorates the image quality.

The present invention has been made in order to solve the above problems in the conventional solid-state image pickup device using a CMD as a light receiving element, and does not cause deterioration of FPN and image quality due to variations in output current and dark current. CM that did
An object of the present invention is to provide a method for manufacturing a solid-state imaging device using D as a light receiving element.

[0009]

In order to solve the above problems, the invention according to claim 1 forms a source region and a drain region on the surface of a high resistance semiconductor substrate, and at the same time, the source region and the drain region. A gate electrode is arranged between the two via an insulating film, and a source / drain current modulated in parallel with the surface of the substrate flows.
In a method of manufacturing a solid-state imaging device using MD as a light receiving element, before forming a gate electrode of CMD, an oxide film by thermal oxidation is formed in a gate electrode region that contributes to a charge modulation operation of CMD, and then a gate electrode is formed. A resist pattern having a similar shape at least on its drain side is formed, and N-type impurities are ion-implanted using the resist pattern as a mask to form at least a channel stopper region for electrically separating the N-type drain diffusion layer and each light receiving element. It has a process.

As described above, after forming the thermal oxide film before forming the gate electrode, N-type impurities are ion-implanted to form a channel stopper region including at least an N-type drain diffusion layer and an N-type diffusion layer. As a result, the thermal oxide film having a uniform thickness makes the diffusion depth and the lateral spread of the N-type drain diffusion layer and the channel stopper region uniform, resulting in a small variation in the electric field near the gate end. It is possible to obtain a CMD in which variations in output current and dark current are small.

Further, since N-type impurities are ion-implanted using a resist pattern formed in the gate electrode region contributing to the charge modulation operation and having a shape similar to that of the gate electrode at least on the drain side as a mask, CMD of the CMD can be formed only in that step. The edge of the drain side region that determines the effective gate length is defined, and therefore the generation of FPN due to the positional shift in the photolithography process can be prevented.

According to a second aspect of the present invention, a source region and a drain region are formed on the surface of the high resistance semiconductor substrate, and a gate electrode is arranged between the source region and the drain region with an insulating film interposed therebetween. In a method of manufacturing a solid-state imaging device using as a light receiving element a charge modulation element configured so that a source / drain current modulated in parallel with the surface of a substrate flows, before forming a CMD gate electrode, N
A film serving as a solid-phase diffusion source of the type impurities is deposited, and in addition to the gate electrode region that contributes to the charge modulation operation of the charge modulation element, the gate electrode and at least the drain side thereof are formed in a similar shape to part of the solid-phase diffusion source film It comprises a step of removing and forming, and then annealing to form at least a channel stopper region for electrically separating the N-type drain diffusion layer and each light receiving element.

As described above, before forming the gate electrode, the solid phase diffusion source film is formed and annealed to form the channel stopper region including at least the N-type drain diffusion layer and the N-type diffusion layer. Therefore, the diffusion depth and the lateral spread of the N-type drain diffusion layer and the channel stopper region become uniform, and as a result, the variation of the electric field in the vicinity of the gate edge is reduced, and the variation of the output current and the dark current is small. To be

Further, since impurities are diffused from the solid-phase diffusion source film formed in a region other than the gate electrode region which contributes to the charge modulation operation and which has a similar shape to the gate electrode and at least the drain side, the CMD effect can be obtained only by the process. The edge of the drain side region that determines the effective gate length is defined, and therefore the generation of FPN due to the positional shift in the photolithography process can be prevented.

[0015]

EXAMPLES Next, examples will be described. 1 to 6
[FIG. 8] is a diagram showing a manufacturing process for explaining the first embodiment of the method for manufacturing a solid-state imaging device according to the invention described in claim 1. First, as shown in FIG. 1, on a P ⁻ type semiconductor substrate 1,
An N ⁻ type channel layer 2 is formed by using an epitaxial method or the like, and the N ⁻ type channel layer 2 is formed on the N ⁻ type channel layer 2 in an oxidizing atmosphere.
Thermal oxidation is performed at 900 ° C. to form an oxide film 3 of about 500 Å. Next, as shown in FIG. 1 and FIG. 2 showing the upper surface of FIG. 1, two annular positive resist patterns 11 having a thickness of about 1 μm shown as two pixels are formed on the oxide film 3 by photolithography. This annular resist pattern 11
Is similar to the effective gate shape of the gate electrode 12 to be formed later, and has an outer diameter larger by 0.1 μm and an inner diameter smaller by 0.1 μm than the gate electrode in order to match the output with the conventional one. Next, phosphorus was added at an acceleration voltage of 80 keV to 3 × 10 ¹³ cm 3.
^-Ions are implanted at a concentration of ^-2 to become the source and drain N
The type diffusion layer region 4 is formed. Then resist pattern 11
After being removed by ashing or the like, it is annealed at 900 ° C in a non-oxidizing atmosphere.

Next, as shown in FIG. 3, the oxide film 3 is subjected to HF.
And the like, and then oxidized at 1000 ° C. in an oxidizing atmosphere to form a gate oxide film 5 with a thickness of about 400 Å.
Then, polysilicon to be the gate electrode 12 is deposited to a desired thickness of about 800 Å by the LPCVD method or the like, and N-type impurities such as phosphorus are diffused to reduce the resistance, and photolithography is performed. And the gate electrode 12 is formed by etching. This gate electrode 12 is, as shown in FIG. 4 showing the upper surface of FIG. 3, a gate electrode 1 for two pixels.
2, 12 are in a state of being integrally connected at the connecting portion 12a.

Next, as shown in FIG. 5, oxidation is performed at 900 ° C. for 20 minutes in an oxidizing atmosphere to form an oxide film 6 on the entire surface, and subsequently a source contact hole 7 is formed by photolithography and etching. . Then, arsenic is ion-implanted at an acceleration voltage of 100 keV and a concentration of 2 × 10 ¹⁵ cm ^-2 to form an N ⁺ -type region 8 for good contact, and subsequently at 950 ° C. in a non-oxidizing atmosphere. Anneal for 40 minutes.

Next, as shown in FIG. 6, an electrode film is deposited by a sputtering method or the like, and a source electrode 9 is formed by photolithography and etching, thereby completing a solid-state image pickup device using a CMD as a light receiving element. .

In this embodiment, the gate electrode region that contributes to the charge modulation operation of the CMD is covered with a resist pattern and phosphorus is ion-implanted to form the N-type diffusion layer 4 serving as the source / drain. , CM only in this process
The effective gate length of D is defined, and the channel stopper region can be formed. The oxide film that serves as a mask when phosphorus is ion-implanted has a uniform thickness because it is formed by thermal oxidation. Therefore, the diffusion depth of phosphorus is also uniform, and as a result, variations in the electric field near the gate edge are small. Become. As a result, variations in the output current and the dark current are reduced, and the roughness of the image quality is reduced.

Next, a second embodiment of the invention according to claim 1 will be described with reference to the manufacturing process diagrams shown in FIGS. First, as shown in FIG. 7, an N ⁻ type channel layer 22 is formed on a P ⁻ type semiconductor substrate 21 by an epitaxial method or the like, and the N ⁻ type channel layer 22 is formed.
Thermal oxidation is performed on the ⁻ type channel layer 22 at 900 ° C. in an oxidizing atmosphere to form an oxide film 23 of about 500 Å. next,
As shown in FIGS. 7 and 8 showing the upper surface of FIG. 7, two disk-shaped negative resist patterns 31 having a thickness of about 1 μm shown as two pixels are formed on the oxide film 23 by photolithography. The disk-shaped resist pattern 31 is similar to the effective gate shape of the gate electrode 32 to be formed later on the drain side, and has an outer diameter larger than the gate electrode by 0.1 μm. Next, 2x phosphorus at an acceleration voltage of 80 keV
Ions are implanted at a concentration of 10 ¹³ cm ^-2 to form an N-type diffusion layer region 24 on the drain side. Then, after removing the resist pattern 31 by ashing or the like, 90
Anneal at 0 ° C.

Next, as shown in FIG. 9, the oxide film 23 is subjected to HF.
And the like, and thereafter is oxidized at 1000 ° C. in an oxidizing atmosphere to form a gate oxide film 25 with a thickness of about 400 Å.
Then, polysilicon to be the gate electrode 32 is deposited by LPCVD or the like to a desired film thickness so as to have a finished size of about 1600 Å, and N-type impurities such as phosphorus are diffused to reduce the resistance. Gate electrode 32 is formed by photolithography using a positive resist pattern
To form. This gate electrode 32 is a diagram showing the upper surface of FIG.
As shown in 10, the gate electrodes 32 for two pixels are connected to each other.
It is integrally connected at 32a.

Next, as shown in FIG. 11, a resist pattern 33 which opens only the source region of the CMD is formed, and arsenic is ion-implanted at an acceleration voltage of 130 keV and a concentration of 2 × 10 ¹⁵ cm ^-2 to form a source. The side N ⁺ type diffusion region 26 is formed, the resist pattern 33 is removed, and then annealing is performed at 950 ° C. for 30 minutes in a non-oxidizing atmosphere.

Next, as shown in FIG. 12, heat treatment is performed at 900 ° C. for 30 minutes in an oxidizing atmosphere to form an oxide film on the entire surface.
After forming 27, a source contact hole is formed by photolithography and etching, an electrode film is deposited by a sputtering method or the like, and a source electrode 28 is formed by photolithography and etching.
Complete the MD.

In this embodiment, the gate electrode region that contributes to the charge modulation operation of the CMD is ion-implanted with phosphorus so as to cover the resist pattern, and the N-type diffusion layer to be the drain is formed.
Since 24 is formed, the effective gate length of the CMD is defined and the channel stopper region can be formed only in this step. In addition, the oxide film that serves as a mask when phosphorus is ion-implanted is formed by thermal oxidation and has a uniform film thickness. Therefore, the diffusion depth of phosphorus is also uniform, and as a result, variations in the electric field in the vicinity of the gate edge are suppressed. Get smaller. This reduces variations in output current and dark current,
The roughness of the image quality is reduced.

Further, in this embodiment, the N-type diffusion layer region on the drain side is formed by using the negative type resist pattern, and the N ⁺ type diffusion layer on the source side is formed by using the positive type resist pattern. It is formed along. In general, an exposure apparatus used for photolithography has non-uniformity in illuminance distribution, but as described above, the non-uniformity in illuminance distribution is canceled by using a negative resist pattern and a positive resist pattern together. . Therefore,
In this embodiment, the effective gate length determined between the source and the drain is constant regardless of the illuminance distribution in photolithography, and fixed pattern noise can be reduced.

Next, the embodiment of the invention described in claim 2 is shown in FIG.
~ It demonstrates based on the manufacturing process drawing shown in FIG. First, Fig. 13
As shown in FIG. 5, an N ⁻ type channel layer 42 is formed on the P ⁻ type semiconductor substrate 41 by an epitaxial method or the like, and an oxide film containing an N type impurity such as phosphorus is formed on the N ⁻ type channel layer 42. A
A solid phase diffusion source film 43 of N-type impurities is formed by depositing the film with a film thickness of about 2000 Å by the PCVD method or the like. Next, as shown in FIG. 13 and FIG. 14 showing the upper surface thereof, a resist pattern 51 having two notched annular portions shown as two pixels is formed on the solid-phase diffusion source film 43 by photolithography. The notched annular portion of the resist pattern 51 is similar to the effective gate shape of the gate electrode 46 to be formed later, and has an outer diameter larger by 0.1 μm and an inner diameter smaller by 0.1 μm than the gate electrode.

Next, as shown in FIG. 15, the resist pattern shape is transferred to the solid phase diffusion source film 43 by etching using the resist pattern 51 as a mask. Next, after removing the resist pattern 51 by ashing or the like, the resist pattern 51 is annealed at 900 ° C. in a non-oxidizing atmosphere to diffuse the N-type impurities into the N ⁻ -type channel layer 42, and the N ⁺ -type diffusion layer serving as the source and drain A region 44 is formed.

Next, as shown in FIG. 16, the solid phase diffusion source film 43
Is removed by HF etc., then 1000 ℃ in an oxidizing atmosphere.
Then, the gate oxide film 45 is formed to a thickness of about 400 Å. Then, a polysilicon film to be the gate electrode 46 is deposited to a desired film thickness by LPCVD or the like to a desired thickness of about 800 Å, and N-type impurities such as phosphorus are diffused to reduce the resistance, and photolithography is performed. And the gate electrode 46 is formed by etching. This gate electrode 46 is
As shown in FIG. 17 showing the upper surface of FIG. 16, the gate electrodes 46, 46 for two pixels are integrally connected by the connecting portion 46a.

Then, as shown in FIG. 18, heat treatment is performed at 900 ° C. for 30 minutes in an oxidizing atmosphere to form an oxide film on the entire surface.
After forming 47, a source contact hole is formed by photolithography and etching, an electrode film is deposited by a sputtering method or the like, and a source electrode 48 is formed by photolithography and etching.
Complete the MD.

In this embodiment, in addition to the gate electrode region that contributes to the charge modulation operation of CMD, the N-type impurity is diffused by the solid-phase diffusion source film to form the N-type diffusion layer region serving as the source / drain. Since this is done, the effective gate length of the CMD can be defined and the channel stopper region can be formed only in this step. Further, since the N-type impurities are directly diffused from the solid-phase diffusion source film without passing through the oxide film or the like, the diffusion depth of the N-type impurities becomes uniform, and as a result, the variation of the electric field near the gate end is reduced. As a result, variations in the output current and the dark current are reduced, and the roughness of the image quality is reduced.

[0031]

As described above on the basis of the embodiments,
According to each of the first and second aspects of the invention, the N-type diffusion layer region is formed by ion implantation or diffusion from the solid phase diffusion source film in addition to the effective charge modulation region regardless of the gate electrode of the CMD. Since it is formed, the effective gate length of the CMD can be defined and the channel stopper region can be formed only in this step, and as a result, the generation of FPN due to the positional deviation in the photolithography step can be prevented. You can Further, before the gate electrode is formed, an N-type diffusion layer is formed by ion implantation using a thermal oxide film having a uniform thickness as a mask or by direct diffusion from a solid phase diffusion source film without an oxide film or the like. Therefore, the diffusion depth of the N-type diffusion layer is uniform, the variation of the electric field near the gate end is reduced, and the variations of the output current and the dark current are reduced.
A solid-state imaging device using D can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a first embodiment of the invention according to claim 1;

FIG. 2 is a schematic top view seen from above in FIG.

FIG. 3 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 1.

FIG. 4 is a schematic top view seen from above in FIG.

FIG. 5 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 3;

FIG. 6 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 5;

FIG. 7 is a diagram showing a manufacturing process of the second embodiment of the invention according to claim 1;

FIG. 8 is a schematic top view seen from above in FIG.

9 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 8. FIG.

FIG. 10 is a schematic top view seen from above in FIG. 9.

FIG. 11 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 9.

FIG. 12 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 11.

FIG. 13 is a diagram showing a manufacturing process according to the embodiment of the invention as set forth in claim 2;

14 is a schematic top view seen from above in FIG. 13.

FIG. 15 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 13.

16 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 15.

17 is a schematic top view seen from above in FIG. 16.

18 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 16.

FIG. 19 is a cross-sectional view showing a configuration of one pixel portion of a solid-state imaging device using a conventional CMD as a light receiving element.

FIG. 20 is a schematic top view showing a gate electrode structure of a conventional CMD light receiving element.

[Explanation of symbols]

1 P ⁻ type semiconductor substrate 2 N ⁻ type channel layer 3 oxide film 4 N type diffusion layer region 5 gate oxide film 6 oxide film 7 source contact hole 8 N ⁺ type region 9 source electrode 11 positive resist pattern 12 gate electrode 21 P ^- type semiconductor substrate 22 N ^- -type channel layer 23 oxide film 24 drain side N-type diffusion layer region 25 a gate oxide film 26 source-side N ⁺ -type region 27 oxide film 28 source electrode 31 negative resist pattern 32 gate electrode 33 resist pattern 41 P ⁻ type semiconductor substrate 42 N ⁻ type channel layer 43 Solid phase diffusion source film 44 N type diffusion layer region 45 Gate oxide film 46 Gate electrode 47 Oxide film 48 Source electrode 51 Resist pattern

Claims (2)

[Claims] 1. A source region and a drain region are formed on the surface of a high resistance semiconductor substrate, and a gate electrode is disposed between the source region and the drain region with an insulating film interposed therebetween, and is modulated in parallel with the substrate surface. In a method of manufacturing a solid-state imaging device using a charge modulation element configured so that a source / drain current flows as a light receiving element, after forming an oxide film by thermal oxidation before forming a gate electrode of the charge modulation element, A resist pattern having a similar shape to the gate electrode and at least its drain side is formed in the gate electrode region that contributes to the charge modulation operation of the charge modulation element, and N-type impurities are ion-implanted using the resist pattern as a mask,
A method of manufacturing a solid-state imaging device, comprising a step of forming at least a channel stopper region for electrically separating an N-type drain diffusion layer and each light receiving element. 2. A source region and a drain region are formed on a surface of a high resistance semiconductor substrate, and a gate electrode is disposed between the source region and the drain region with an insulating film interposed therebetween, and is modulated in parallel with the substrate surface. In a method of manufacturing a solid-state imaging device using a charge modulation element configured so that a source / drain current flows as a light receiving element, a solid-state diffusion source of N-type impurities is formed before forming a gate electrode of the charge modulation element. A film is deposited, and the solid-phase diffusion source film is formed by removing a part of the solid-phase diffusion source film in a similar shape to the gate electrode and at least the drain side thereof in addition to the gate electrode region that contributes to the charge modulation operation of the charge modulation device, and then annealed And at least forming a channel stopper region for electrically separating the N-type drain diffusion layer and each light receiving element from each other.