JPH0863993A - Memory device - Google Patents

Abstract

PURPOSE: To prevent increasing the size of a memory IC package by converting digital address information and digital information into analog data, supplying them with each one pin, converting them to digital data inside, and accessing a memory array. CONSTITUTION: Digital address information from access devices 1a-1n is supplied to a memory 5 with corresponding one pin through D/A converters 2a-2n. And memory array banks 110a-110k are accessed preventing competition for the same memory bank in a mediation section 100 and address selectors 7a-7n through A/D converters 6a-6n of the inside of the memory 5. Data information is supplied to the memory 5 with one pin in the same way, read-out information is outputted with one pin through internal D/A converters 150aa-150nn. By using this constitution, address information and data information are supplied with one pin independently of the number of stored words of a memory and data length per one word, increasing the size of an IC package is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory in which digital data can be stored and read and written by supplying address information and control information.

[0002]

2. Description of the Related Art FIGS. 3 and 4 show N (= log2W) address signal lines and B data signals when the number of words stored in a memory array is W words and the data length per word is B bits. FIG. 3 is a block diagram of a conventional memory access in which a plurality of devices for accessing a line and a memory that requires n control lines are connected by these signal lines.

In FIG. 3, an access bus 510 forming an address signal line, a data bus 520 forming a data signal line, and a control bus 530 forming a control signal line are shown as the access device 1.
a, 1b ..., 1n are shared. Therefore, when a plurality of access devices 1a, 1b, ..., 1n access the memory 500 at the same time, a collision of the buses occurs. To avoid this simultaneous memory access,
There is an arbitration device 540 having a function of monitoring the control bus 530 and, when detecting a simultaneous memory access, giving access use priority to the bus and permitting the memory access.

In FIG. 4, two access devices 1a and 1b are provided.
It is possible to access the memory simultaneously by each port of the dual port memory. However, for the same address, the access control arbitration 620 in the dual port memory 600 drives the access lines 532a and 532b indicating which access device is given priority. This causes one access device to perform a memory access, while the other must wait.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Many address pins and data pins that supply digital address information and digital data information must be prepared according to the number of words stored in the memory and the data length per word. There is a drawback that the IC package size increases. It is an object of the present invention to provide an address and data information supply method for solving these drawbacks.

[0006]

SUMMARY OF THE INVENTION According to the present invention, digital address information and digital data information are converted into analog values, and the address information and the data information are supplied to the memory by one pin, respectively. Convert these analog value address and data information to digital value and return
These pieces of information enable access to the memory array.

[0007]

As a result, the number of pins for supplying the address information and the data information to the memory is only one each regardless of the number of words stored in the memory and the data length per word, and the size of the IC package is not increased. Also, it becomes possible to easily connect a large number of memory access devices.

[0008]

FIG. 1 shows an embodiment of the present invention.

In the figure, 1a, 1b, ..., 1n
Is an access device, 2a, 2b, ..., 2n is a digital address information access device 1a, 1b ,.
The digital / analog converters 3a, 3b, ...
Input data digital / analog converters 4a, 4b, ..., 4n for converting output digital data of a, 1b, ..., 1n into analog values are access devices 1a, 1
b, ..., 1n show output data-analog / digital converters for converting the data received by analog into digital data, and these devices access the memory of the present invention described below.

A memory 5 according to the present invention has the following structure. 6a, 6b, ..., 6n are the address information of the analog value supplied from the outside, 21a, 2
Address analog / digital converters for converting 1b, ..., 21n into digital values, 7a, 7b ,.
k is the address / analog / digital converter 6a, 6b,
..., the address information 6aa which is the output of 6n,
Address selectors for passing only one of 6bb, ..., 6nn, 110a, 110b ,.
Are address information 11a, 11b, ...
, 11n or 6aa, 6bb, ..., 6nn high order l bits make the memory array a bank memory array in which K = 2 l-th banked bank memory array, 140a,
140n are analog value data information 51a, 51b, ..., 51n supplied to the memory 5.
The input data / analog / digital converters 150a, 150b, ...
Bank memory arrays 110a, 110b, ..., 1
An output data / digital / analog converter for converting the digital data output from 10n to an analog value, 12
0a, 120b, ..., 120k are input data / analog / digital conversion units 140a, 140b ,.
This is the input data selector that passes only one of the data from 140k, and this output is the bank memory array 110.
a, 110b, ..., 110k are connected to the data input / output ports. 130a, 130b, ..., 13
0k is a bank memory array 110a, 110b, ...
The output data selection unit for passing only one of the output data from the 110k, the output data is output to the digital / analog conversion unit 150a, 150b, ..., 15
It is connected to the 0n input section. Reference numeral 100 designates address information 6aa, 6bb, ..., 6n supplied to realize avoidance of access to the same bank memory array.
The upper l bits of n are monitored, and if there is the same bit pattern, it is determined that access to the same bank memory array has occurred, and which of the address information 6aa, 6bb, ...・ ・ ・ ・ ・ ・ 7
k) Arbitration control information 10 indicating whether to preferentially pass
0a is generated and supplied to the address / data selection control unit and bank selection control unit described below. Also, the input data / analog / digital conversion units 140a, 140b, ..., 1
40n and output data / digital / analog converter 150
a, 150b, ..., 150n operation control signal 100
produces b. 8 is address information 6aa, 6bb, ...
.., 7k, input data selection units 120a, 120b, ..., 120k, and output data selection units 130a, 130b, ..・ 、 130k
Pass bit patterns 8a, 8b, ..., 8k indicating which address information or data information is to be passed with respect to
Is output. 9 is address information 6aa, 6bb, ...
The bank memory arrays 110a, 110b, ..., 1 according to the upper 1 bit of 6nn and the arbitration control signal 100a.
The operation control signals 9a, 9b, ..., 9k to 10k are generated. 160 is an access device 1a, 1b, ...
In response to the 1n access control signal 52, this information is supplied to the arbitration unit 100 and each unit in the memory 5 is controlled.
Further, if arbitration occurs during memory access, the access device is notified of the information to that effect through the control signal 52.

The operation of the memory of the present invention will be described below with reference to FIG. In FIG. 2, the access devices are 1a, 1b, 1
c, 1d, and the number of banks of the memory 5 is 4 11
The case of 0a, 110b, 110c, and 110d is shown. Address information 11a, 11 from the access devices 1a, 1b, 1c, 1d as bit patterns at the same time
b, 11c and 11d are 00a ₁ a ₂ ..., an, 1 respectively
0b ₁ b ₂ ... bn, 11c ₁ c ₂ ... cn, 11d ₁
When the data is output as d ₂ ... dn, the bit pattern of the upper 2 bits l is "11", so 11c ₁ c ₂ ... c
n and 11d ₁ d ₂ ... dn with bank memory array 11
Simultaneous access to 0d is detected, and arbitration occurs in both.

Address information 11a, 11b, 11c, output simultaneously from the access devices 1a, 1b, 1c, 1d,
11d is an address / analog / digital converter 2a,
2b, 2c, and 2d are analog address information 21
It is supplied to the memory 5 as a, 21b, 21c and 21d. These pieces of information are again converted into digital value address information 6aa, 6bb, 6cc, 6dd by the address / analog / digital converters 6a, 6b, 6c, 6d, and the bit pattern 1 of the address information 6cc and 6dd.
The access arbitration is performed by 1c ₁ c ₂ ... cn and 11d ₁ d ₂ ... dn, and priority is given to the bit pattern 11c ₁ c ₂ ... cn of the address information 6cc and the address selector 7d is set. Pass the bank memory array 110d first
Bit pattern c ₁ c ₂ ... As address information 7dd
・ Supply cn. Bit information 00a ₁ a ₂ ... An of one address information 6aa, address information 6bb
Of the bit patterns 10b ₁ b ₂ ... Bn pass unconditionally through the address selection units 7a and 7c, and are transferred to the bank memory arrays 110a and 110c, respectively.
bit pattern as cc a ₁ a ₂ ... An, b ₁ b ₂
... bn is supplied. The address information 6dd, which has lost the priority of the path in the address selecting unit 7d, passes through the address selecting unit 7d for the memory access immediately after the end of the access by the address information 6cc, and the bit pattern d ₁ d ₂ ... dn is bank memory array 1
Supply to 10d. The operation up to this point is shown in FIG.
It corresponds to (b), (c), and (f).

Data information 12a, 12b, 12c, 12
d is the address data 51a, 51b, 51c, 51 of the analog value by the input data digital / analog converters 3a, 3b, 3c, 3d at the time of writing to the memory 5.
It is converted into d and supplied to the memory 5. These pieces of information are input data / analog / digital converters 140a, 14
0b, 140c, 140d convert the data information into digital values again, and the input data selection units 120a, 120
b, 120c, 120d. When reading from the memory 5, the output data selection units 130a, 130b, 1
The data information from 30c and 130d is output as data / digital / analog converters 150a, 150b, 150c,
Address information 51a, 51 of analog value at 150d
b, 51c, 51d, and further converted into digital value data information 12a, 12b, 12c, 12d by the output data / analog / digital converters 4a, 4b, 4c, 4d.

In reading / writing data from / to the address information, as in the case of the address information, the input data selecting section 120d is used for writing and 13 is used for reading.
At 0d, the arbitration of the acquisition of the priority of the path occurs, and the data information c ₁ c ₂ ... cn for the access of the address information 11c ₁ c ₂ ... Further, c ₁ c ₂ ... cn appear in the data information 51d as an analog value. Following this information, the data information D ₁ D ₂ ... Dn for the access of the address information 11d ₁ d ₂ ... dn appears on each signal line. The operation up to this point is as shown in (d), (e), and FIG.
This corresponds to (f).

[0015]

Even if the number of words stored in the memory and the bit length per word are increased, only one pin is required to supply the address information and the data information. The size can be reduced and the mounting area of the IC package on the printed board and the area occupied by the pattern for supplying the address and data information can be significantly reduced, which facilitates high-density mounting.

Further, a plurality of access devices can be easily connected to the memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the flow of addresses and data when there are four access devices in FIG.

FIG. 3 is a system block diagram of a conventional example.

FIG. 4 is a system block diagram of a conventional example.

[Explanation of symbols]

21a, 21b, ..., 21n Address information of analog value 6a, 6b, ..., 6n Address / analog / digital converter 6aa, 6bb, ..., 6nn Address information of digital value 140a, 140b, ... ., 140n input data
Analog / digital converter 150a, 150b, ..., 150n Output data
Digital / analog converter 51a, 51b, ..., 51n Analog value data information 140aa, 140bb, ..., 140nn Digital value input data information 150aa, 150bb, ..., 150nn Digital value output data information 110a , 110b, ..., 110k Bank memory array 7a, 7b, ..., 7k Address selection unit 7aa, 7bb, ..., 7cc Address information 110aa, 110bb ,. Data information 8 Address / data selection control unit 9 Bank memory control unit 100 Arbitration unit 52a, 52b ..., 52n Arbitration occurrence flag 120a, 120b, ..., 120k Input data selection unit 130a, 130b, ..., 130k Output data selection section 160 Memory 5 Internal control unit 1a, 1b, ... 1n Access device 11a, 11b, ... 11n Address information 2a, 2b, ... 2n Address digital / analog conversion device 3a, 3b, ... 3n Input data digital / Analog converter 4a, 4b, ... 4n Output data / Analog / digital converter 12a, 12b, ..., 12n Data information 8a, 8b, ... 8k 110 bit pattern

Claims (2)

[Claims] 1. A memory device characterized in that address information is inputted as an analog value, internally converted into digital address information, and data is accessed to a memory array. 2. Inputting / outputting data information as an analog value, internally converting to digital information when input and writing to a memory array, and outputting to converting digital data from the memory array to an analog value and reading. Memory device characterized by.