JPH0863127A - Picture display device - Google Patents

Abstract

PURPOSE: To reduce display irregularity by detecting a time in which a potential of a row electrode is made the reference potential, applying a correction selecting potential to a row electrode during a time proportional to the time, after that applying a non-correction selecting potential to it, and reversing polarity of a driving signal of liquid crystal by frame synchronism. CONSTITUTION: A correction selecting potential V1 A of 1 is applied to a row electrode in a selection period, a potential of a signal at the row electrode is raised from a non-selecting potential V5 of non-selection period 1 to the reference potential V1 S indicated by symbol Y1 , then a time (t) reaching to the reference potential is detected, and a correction selecting potential V1 A is applied to the row electrode during a time (ft) proportional to the time. A non-correction selecting potential V1 is applied in a selection period 3 after a time (f+1)t, when non-selection, a non-selection potential V5 of a non-selection period is applied. In the next frame, a non-selection potential of a signal of the row electrode is V2 , a correction selecting potential is V6 , a non- correction selecting potential is V6 , the signal reaches the reference potential V6 <5> at Y6 , and polarity of a signal of the row electrode is reversed. When selecting response of the row electrode is slow, a detecting time is made long, and reduction of driving effective voltage is corrected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simple matrix type image display device used in a computer word processor or the like.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram of a pixel of a simple matrix type image display device, which is (I, J) to (I + 1, J +).
4) of 1) is shown. Liquid crystal of pixel of (I.J.) 1
83 is sandwiched between a row electrode 181 and a column electrode 182 which are orthogonal to each other. A plurality of transparent row electrodes parallel to the row electrode 181 are formed on one glass substrate, and a plurality of transparent column electrodes parallel to the column electrode 182 are formed on the opposing glass substrate. The liquid crystal sealed between both substrates is subjected to voltage control for each pixel by electrodes crossing rows and columns to display an image. R (I), R (I +
1) is the signal of the row electrodes of the I row and (I + 1) row, S (J),
S (J + 1) is a signal of the column electrodes of the J and (J + 1) columns.

FIG. 16 is a screen view of a liquid crystal display body for explaining display unevenness. 191 and 192 are row-side drive circuits that send potential signals for selecting and deselecting pixels for each row to the row electrodes of the liquid crystal display, and 193 and 194 are columns that send image signals for lighting and non-lighting to the column electrodes. Drive circuit on the side.

On the first line of the screen, all black portions (non-lighting) horizontal stripes, on the second line, 2/3 on the left side is black portion, 1/3 on the right side is white portion (lighting) horizontal stripe, and on the third line. The left 1/3 has a black stripe, the right 2/3 has a white stripe, and the 4th row has a white stripe. The 5th, 6th, 7th, and 8th rows show the 1st, 2nd, 3rd, and 4th rows. It is repeated every 4 lines of 4 lines.

In lines 1, 2, 3, and 5, 195, 196, 197,
The black part at the position indicated by 201 is darker as the black part in the horizontal stripe is shorter and the white part is longer, and 195 and 201 have the same darkness.
196 and 197 are dark black in that order. The white areas at 198, 199, and 200 in the 2nd, 3rd, and 4th rows are brighter in the white areas in the horizontal stripes, and the longer the black area, the brighter the white area becomes.
Bright white in the order 9 and 198. There is "display unevenness" in which the density and brightness change depending on the amount of black and white in the line.

FIG. 17 is a drive signal diagram of the liquid crystal, and shows a signal of the row electrode and a potential diagram of lighting / non-lighting of the column electrode. The signal of the row electrode indicates the third row, and the non-selection potential V ₂ indicated by 211 is inverted to become the non-selection potential V ₅ indicated by 213,
After the selection period of the first and second rows, the selection potential V ₁ is set in the selection period of the third row indicated by 214, and the non-selection potential V indicated by 213 while the selected row sequentially moves from the fourth row to the last row. It will be ₅ .
In the next frame where the polarity is reversed due to the AC drive of the liquid crystal
There is a non-selection period of the non-selection potential V ₂ indicated by 211 corresponding to 213 and a selection period of the selection potential V ₆ indicated by 212 corresponding to 214.

Reference numerals 216 and 218 denote the non-lighting potential V ₄ and the lighting potential V ₆ of the column electrodes, respectively. In the next frame in which the polarities are reversed, 215 corresponds to 216 and 215 corresponds to the non-lighting potentials V ₃ and 218. Is the lighting potential V ₁ . V _k −V _{k + 1} = V (k
= 1, 2, 4, 5) and the same voltage.

FIGS. 18 and 19 are liquid crystal drive signal diagrams for explaining display unevenness. FIG. 18 is a drive signal diagram applied to the liquid crystal at position 198 in FIG. 16, and FIG. 19 is a liquid crystal at position 200 in FIG. It is a drive signal diagram added to the. The drive signal of this liquid crystal is selected in Fig. 17
The non-selected / lit / non-lit potentials are V ₁ , V ₅ , and
When a V _6, V ₄ (the potential of the row electrode - the column electrode potential)
And becomes the inversion signal of the signal of (the potential of the row electrode−the potential of the column electrode) when the respective potentials are V ₆ , V ₂ , V ₁ , and V ₃ in the next frame in which the polarities are inverted. ing.

A waveform 221 that rises to the inter-electrode voltage of the liquid crystal and a waveform 223 that falls to the non-selection period shown in 222 of FIG.
Is steeper than the waveform 231 that rises to the inter-electrode voltage of the liquid crystal and the waveform 233 that falls to the non-selection period in the selection period indicated by 232 in FIG. 19, and during the period when a high voltage of (selection potential-image signal potential) is taken, 18 is longer than FIG. 19 and the drive effective voltage is high. So
The lit white color of the LCD at position 198 is brighter than that of the liquid crystal at position 200.

This occurs because the capacitance differs depending on the orientation state due to the dielectric anisotropy of the liquid crystal. The white part has a larger capacity than the black part, and the larger the amount of white in one line, the larger the capacity. This is because the response time of the drive signal including the output resistance of the row selection signal including the electrode resistance and the capacitance product of the liquid crystal of the row becomes long, and the rising and falling response waveforms bend.

The reference numeral 224 in FIG. 18 and the reference numeral 234 in FIG.
Lighting potential), 225 and 235 are (non-selection potential-non-lighting potential)
, And the voltage between electrodes of the liquid crystal at this time is V
Is equal to

The reason why the black portion in the horizontal stripe is short and the white portion is long is that black is dark and white is less bright because the response of the drive signal at the time of selection is slow and the drive effective voltage is lowered. Is shorter and the black portion is longer, white is brighter and black is less dense because the response of the drive signal at the time of selection is fast and the drive effective voltage is high.

In recent years, liquid crystal display devices having a larger area and a higher definition use a super twist type liquid crystal display system having a steep transmittance-voltage curve. As the number of row electrodes increases, the selection period becomes shorter, and the drive effective voltage for distinguishing between lighting and non-lighting becomes closer. The display unevenness that changes the response waveform of the selection signal and changes the drive effective voltage to change the density and brightness depending on the amount of black and white in the above line is an underlined sentence or horizontal line, or a figure with a frame , It has come to be recognized as a defect on screens such as graphs.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and display unevenness can be obtained by using an improved driving method which has not been known so far. It is intended to newly provide a reduced image display device.

[0015]

The present invention has been made to solve the above-mentioned problems, and a liquid crystal is provided between a substrate having a plurality of row electrodes and a counter substrate having a plurality of column electrodes. A potential signal for sandwiching and selecting / non-selecting pixels for each row is sent to the row electrodes, and a lighting / non-lighting image signal is sent to the column electrodes.
In an image display device in which the polarity of the drive signal applied to the liquid crystal is inverted in a frame cycle to perform AC driving, the selection potential of the row electrode includes a correction selection potential and a non-correction selection potential, and the correction selection potential is a non-selection potential The voltage between them is set higher,
A selection potential is applied to the selected row electrode, the time from when the signal of the row electrode reaches the reference potential from the beginning of the selection period is detected, the time proportional to the time, and the correction selection potential is set as the selection potential, Hereinafter, the present invention provides an image display device characterized in that the liquid crystal is driven by using the non-correction selection potential as the selection potential.

[0016]

In the present invention, the time required for the selection signal applied to the row electrode to reach the reference potential from the beginning of the selection period is detected, and the correction selection potential is sent to the row electrode as the selection potential for a time proportional to the time. After that time, the non-correction selection potential is sent as the selection potential from the end of the selection period. Since the correction selection potential is applied according to the response time until the selection signal reaches the set reference potential, fluctuations in the drive effective voltage of the liquid crystal due to changes in the response waveform of the selection signal are corrected individually for each row, reducing display unevenness. To be done.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a drive signal diagram of a liquid crystal of an image display device of the present invention, showing a signal of a row electrode and a lighting / non-lighting potential of a column electrode related to the liquid crystal. The signal of the row electrode changes from the non-selection potential V _{5 in} the non-selection period of 1 to the correction selection potential V ₁ ^{A in the} selection period and changes with the response waveform of 2 to increase the potential. The time t from the beginning of the selection period until reaching the set reference voltage V ₁ ^S indicated by Y ₁ is detected, and the corrected selection potential V ₁ ^A is continuously applied to the row electrode for the time ft proportional to the time. The non-correction selection potential V ₁ is applied during the selection period 3 after the time of (f + 1) t, and when it is deselected, the potential changes due to the response waveform of 4 and the potential becomes low. It will be ₅ .

In the next frame, the non-selection potential of the signal of the row electrode is V ₂ , the correction selection potential is V ₆ ^A , the non-correction selection potential is V ₆ , and the reference potential V ₆ ^S is reached by Y ₆ , and 6, 7 , 8, 9 and 10 change the signal of the row electrode from 1, 2, 3, 4 of the previous frame.
Corresponding to the change of 5, the polarity is inverted. That is, V ₁ ^A −V
^{_{1 = - (V 6 A -V}} 6), V 1 A -V 1 S = - (V 6 A -
^{_{V 6 S), V 1 -V}} 5 = - a (V ₆ -V _2).

For the signals of the row electrodes 1 to 5, the lighting / non-lighting potentials of the column electrodes are V ₆ and V ₄ , respectively, and in the next frame in which the polarities are inverted, the signals of the row electrodes 6 to 10 are processed. The potentials of lighting and non-lighting of the column electrodes are V ₁ and V ₃ , respectively, and the value of V _K −V _{K + 1} is the same voltage for K = 1, 2, 4, and 5.

The slower the response of selection applied to the row electrode, the longer the detection time t, and the voltage between the non-selection potential and the non-correction selection potential is larger than the non-correction selection potential. In addition, the reduction of the effective drive voltage is corrected.

FIG. 2 is a power supply circuit diagram for producing a liquid crystal drive potential of the image display device of the present invention. A PNP transistor is formed by dividing the voltage between the power supply potential V _CC and V _ZZ with a resistor R ₈ and a variable resistor R _9.
It is input to the base of 11 and the collector is connected to the V _ZZ potential and the emitter is connected to the V _CC potential through the series connection of the two resistors R ₇ and R ₇ . The power supply potential V _CC and the emitter potential V _{EE of the} transistor 11 are bisected by two resistors R ₇ and R ₇ , and the voltage follower 12 creates an intermediate potential V _MM .
By changing the variable resistor R ₉ (V _CC −V _EE ), (V _CC −V
_MM ) voltage is adjusted.

Series resistances R ₃ and R are provided between the power supply potentials V _CC and V _{MM.
It is} divided by ₁ , R ₁ and R ₂ , and the potential of each point is voltage follower.
And output through 18, 19, 20 become non-corrected selection potential in lighting potential or polarity inversion frame V _1, the non-selection potential V _2,
The non-lighting potential V ₃ is created. The correction selection potential V ₁ ^A paired with the non-correction selection potential V ₁ outputs the potential at the voltage dividing point corresponding to V ₁ between V _CC and V _MM by the voltage follower 17, and the output and V
_The voltage between _{CC is divided} by a variable resistor R ₅ and a resistor R ₄ , and is made through a voltage follower 15. The reference voltage V ₁ ^S is defined by the voltage follower 16 by dividing the output potential corresponding to V _{1 of the} voltage follower 17 and V _CC by the variable resistors R ₆ and R ₄ .

An inverting amplifier 25 in which the potentials of V ₁ ^A , V ₁ ^S , V ₁ , V ₂ and V ₃ are both R for the input resistance and the feedback resistance,
24, 23, 22, 21 and inverted with respect to V _MM to be a correction selection potential V ₆ ^A , a reference potential V ₆ ^S , a non-correction selection potential or V ₆ which becomes a lighting potential in a polarity inversion frame, A non-selection potential V ₅ and a non-lighting potential V ₄ paired with the lighting potential V _6.
Is making.

The power supply voltage of the logic circuit portion of the drive circuit for driving the row electrodes and the column electrodes of the liquid crystal display is V _DD -V _SS (= 5
V), when the power supply voltage of the output circuit portion and V _DD -V _BB,
The power source potentials are V _CC ≧ V _DD ≧ V ₁ ^A ≧ V ₁ ^S ≧ V ₁ > V ₂
> V ₃ > V _MM > V ₄ > V ₅ > V ₆ ≧ V ₆ ^S ≧ V ₆ ^A ≧ V _BB ≧
It is set by V _EE > V _ZZ .

The positive power supply potentials of the operational amplifiers 12, 15, 16, 17, 18, 19, 20 are V _CC and the negative power supply potential is V _LL, and the positive power supply potentials of the operational amplifiers 21, 22, 23, 24, 25 are set. Is V _PP and the negative power supply potential is V _EE . V _CC > V _PP > V _MM > V _LL > V
There is a potential relationship of _EE . This is because the voltage of V _CC -V _ZZ is as large as 40 V and V _cc -V _EE becomes close to this value depending on the adjustment, so that the power supply voltage of the operational amplifier is not increased. Of course, if the power source voltage of V _CC -V _ZZ is selected within the rated range of the operational amplifier, the power source potentials of the 12, 15 to 25 operational amplifiers can be set to V _CC and V _EE .

A PNP transistor 13 is formed by dividing the voltage between the power supply potentials V _CC and V _EE with a resistor R ₁₀ and a zener diode V _ZL.
, The collector is connected to the power supply potential V _ZZ through the resistor R ₁₂ , the emitter is connected to V _CC through the load resistor R ₁₁ , and the potential V _LL is output from the emitter of the transistor 13. V _LL becomes higher than V _EE by the voltage of the Zener diode V _ZL and the base-emitter voltage V _{BE of the} transistor 13.

The voltage between the power supply potentials V _CC and V _EE is divided by the Zener diode V _ZP and the resistor R ₁₀ and input to the base of the NPN transistor 14, and the collector is fed through the resistor R ₁₃ to V _CC ,
The emitter is connected to V _EE through the load resistor R ₁₁ , and the emitter of the transistor 14 outputs the potential of V _PP . V _PP has a potential lower than V _CC by the voltage of the zener diode V _ZP and the base-emitter voltage V _{BE of the} transistor 14.

The capacitors C ₁ , C ₂ , C ₃ , C ₄ , C ₅ are for stabilizing the potential at the connection point. Lighting potential of V ₁ and V ₆ , V
_{While the} stabilizing capacitors C ₁ and C ₂ are connected to the non-lighting potentials of ₃ and V _{4 and} the non-selection potentials of V ₂ and V ₅ , the correction selection potentials V ₁ ^A and V ₆ ^A and the reference potential V _The reason why ₁ ^S and V ₆ ^S have no capacitance is that the row electrodes to be selected are usually one row and almost all rows have a non-selection potential.

The adjustment of the correction selection potential applied to the row electrode of the liquid crystal display is performed with respect to the set reference potential V ₁ ^S so that the display unevenness on the screen having horizontal stripes as shown in FIG. 16 is reduced. The selection potential V ₁ ^A is adjusted or the reference potential V ₁ ^S is adjusted with respect to the set correction selection potential V ₁ ^A.

When setting the reference potential, V ₁ ^S can be set to the same potential as V _1, and therefore V ₆ ^S can be set to the same potential as V ₆ . When setting the correction selection potential, the reference potential V ₁ ^S to be adjusted is V ₁ at one end of R ₄ of the connection shown in which the potential between V _CC and V ₁ is _divided by the resistor R ₄ and the variable resistor R _{6. It} may be changed from _CC to the connection of the output V ₁ ^A of the voltage follower 15 and may be defined between V ₁ ^A and V ₁ , and V _CC or V ₁ ^A and any potential of V ₂ , V ₃ and V _MM You may make it adjust by dividing the voltage between them.

For the correction selection potential V ₁ ^A and the reference potential V ₁ ^S , the potential equivalent to V ₂ is input to the non-inverting input terminal of the operational amplifier, the input resistance is provided between the inverting input terminal and the potential corresponding to V ₃ , and the output of the operational amplifier and the inverting input. An inverting amplifier having a feedback resistor connected between terminals is used to adjust and determine the ratio of the feedback resistor and the input resistor, and the power supply potentials V _CC and V _MM are divided by resistors R ₃ , R ₁ , R ₁ and R _2. The portion of R ₃ which is present may be a Zener diode.

Correction selection potentials V ₁ ^A , V ₆ ^A , reference potential V ₁ ^S ,
V ₆ ^S, uncorrected selection potential or lighting potentials V _1, V _6, the non-selection potential V _2, V _5, the potential of the non-lighting voltage V _3, V ₄ is changed supply voltage (V _CC -V _EE) It is configured to work in conjunction with a variable resistor R ₉ that adjusts the display state of white / black patterns and characters on the screen of the liquid crystal display.

The voltage follower 19 for outputting the non-selection potentials V ₂ and V ₅ of the row electrodes and the inverting amplifier 22 have the same configuration as the inputs to the operational amplifiers 19 and 22 and the outputs 19 and 22, respectively, and further each of them has a separate configuration. Circuits on the left side of the drive circuit on the row side in FIG.
May be separately supplied to the circuit 192 on the right side.

FIG. 3 is a circuit configuration diagram used in the operational amplifier of the liquid crystal drive potential power supply circuit of FIG. (A) is a voltage follower, and (b) is an inverting amplifier, which is a configuration of operational amplifiers connected in parallel so that a large operating current that can be supplied to the load can be obtained without increasing the quiescent current so much.

In the voltage follower (a), of the voltage followers 27 and 26 having the common input V _I , 26 is the auxiliary side, and is connected to the output of 27 through the output resistance r and becomes V _O. Even if the characteristics are not adjusted by adjusting the offset voltage of the operational amplifiers 27 and 26, the output resistance r of the operational amplifier on the auxiliary side
Therefore, the error of the offset voltage is absorbed to improve the circuit performance. Increase of quiescent current is (error of offset voltage) / r
Therefore, the output resistance r can be selected in the range of 1 to 10Ω. For example r
Is selected to be 5Ω, and if the offset voltage error is 5 mV, the quiescent current increases by 1 mA.

In the inverting amplifier of (b), the input resistor R and the feedback resistor R are similarly connected between the inverting input terminal and the input V _I− , and the output, and the input V _{I +} to the non-inverting input terminal is commonly used. Of the inverting amplifiers 29 and 28 that operate, 28 is the auxiliary side, and is connected to the output of 29 through the output resistance r to become V _O.

FIG. 4 shows a control circuit for correcting the selection potential of the row electrode, which supplies the non-correction selection potential subsequent to the correction selection potential as the selection potential of the row electrode of the image display device of the present invention.
5, 6 and 7 are circuit diagrams of a D-type flip-flop, a divider and an up / down counter used in the control circuit of FIG. 4, respectively. 50 and 56 are D-type flip-flops shown in FIG. 5, 51 is a divider shown in FIG. 6, 57 and 58,
59 and 60 are up / down counters shown in FIG.

When the potential of the row electrode is switched from the non-selected potential to the selected potential, the reset signal R _O becomes 1 (V _DD ), and
The data input D to the D-type flip-flop 50 is set to 0 (V _SS ) by the output of the RS flip-flops 45 and 46, and the inversion signal of R _O by the inverter 47 becomes 0, and the D-type flip-flop 50 and the up / down counter. The reset input R ^{* of} 57, 58, 59, 60 is set to 0, and the outputs Q, Q ₁ , Q _2, ... Q _n , Q _A of 50, 57, 58, 59, 60 are set to 0.

The output Q of the divider 51 using the output Q of the D-type flip-flop 50 as the reset input R ^* is 0, and the output of the inverter 52 is 1. However, since the output Q of 50 is 0, the switch 55 is turned off and the inverter is turned off. When the output of 53 is 1, the switch 54 is turned on, and the in-phase signal of the clock CL that has passed the clock CL through the inverters 48 and 49 is input to the clock input CK ₁ of the up / down counter 57. Inverted signal CL ^* by the inverter 48 of clock CL is input as clock C
Data input D of the D flip-flop 56, which is designated as K
The reset input R ^* contains the output Q of the D-type flip-flop 50.

The output Q of the D flip-flop 50 is further connected to the B inputs of the up / down counters 57, 58, 59, 60. When the output Q of 50 is 0, the output Q of the D-type flip-flop 56 connected to the C inputs of the up / down counters 57, 58, and 59 is also 0, and both the B input and the C input for mode switching of the up / down counter. It is 0.

Up / down counter is 0, 1 of B input
(C input is also 1), it becomes the up counter / down counter mode, and at the time of switching, the clock input CK ₁ of the first stage is set to 1 and the C input is set to 0 and the B input is set to 1 to set the clock of each stage. Input CK ₁ , CK ₂ ...
CK _n and CK _A are set to 1 to correct the internal state of the counter, and both the C input and the B input are set to 1 or the B input is set to 0 to serve as a down counter or an up counter. The state of the counter output before correction before the mode switching time is temporarily changed to the state of the counter output after correction after the mode switching.

Reset signal R_O When is 1, B input, C input
Both powers are set to 0, up / down counters 57, 5
8, 59, 60 are up counters. C input of 60 is V
_DDIs always 1, and downcount from upcounter
Output Q when the mode is switched to_A Hold the state of
I am trying. Output Q of 60_A And the inverter 61
Input the inverted signal to the 63, 62 level conversion circuit,
V_DD-V_SSFrom the potential of V _DD-V_BBConverted to a potential signal
Flip and V_DD-V_BB(Or V_CC-V_EE) Power supply potential
Further invert by operating inverters 64, 65 and Q_A Inversion of
Signal A and inverted signal A of A^* And Q_A Is 0 when A
Is 1 (V_DD(Or V_CC)), A^* Is 0 (V_BB(Or
V_EE)).

Signals A and A ^* are sent to analog switches 32 and 38.
31 and 37 are controlled to select the correction selection potentials V ₁ ^A and V ₆ ^A or the non-correction selection potentials V ₁ and V ₆ as the selection potential V ₁ ^R of the row electrode and the selection potential V ₆ ^R with the polarity inverted. Reset signal R _O is 1
Then, the signals A and A ^* are 1 and 0, respectively, and the correction selection potentials V ₁ ^A and V ₆ ^A are output as the selection potentials V ₁ ^R and V ₆ ^R of the row electrodes through the output resistance R _e. The electrodes are at the non-selection potential V ₅ or V ₂ before the reset signal R _O becomes 1,
As the reset signal R _O becomes 1 and the selection potential is applied, the selection potential having the polarity to which the selection potential is applied is initially the non-selection potential V ₅ or V ₂ and the correction selection potential V ₁ ^A.
Alternatively, it becomes a potential divided between V ₆ ^A and V ₆ .

That is, the average resistance of the row electrode of the liquid crystal display is R _L , the resistance when the transistor of the drive circuit on the row side is on is R _T , and the correction selection potential V _X ^A (X = 1, 6) is The output resistance including the resistance when the analog switch is turned on is R
Let _e be the non-selection potential V before the row is in the selected state.
_{Since N} (N = 5, 2) is the potential of the capacitance of the liquid crystal between the plurality of column electrodes intersecting the row electrodes, the selection potential V _X ^R (X = 1) in the polarity to which the selection potential is applied. , 6) is in the initial ^{_{(V X A -V N) (}} R L + R T) / (R L + R T + R
_e ) + V _N , and the selection potential V _Y ^R (Y = 6, 1) in the polarity in which the selection potential is not applied becomes the potential near V _Y ^A.

The reason why the potential of the row electrode changes from the non-selection potential in the initial state of the selection state in FIG. 1 is that the signal of the row electrode of the liquid crystal is shown. In FIG. 4, the selection potential V _X ^R is non-selective. The potential obtained by dividing the selection potential V _N and the correction selection potential V _X ^A is that the selection potential V _X ^R is the correction selection potential V from the row electrode of the liquid crystal.
_This is because it is close to the power supply potential of _X ^A.

When the polarity inversion signal P _Z is 1 (V _CC ), the liquid crystal lighting potential, non-lighting potential and non-selection potential are V ₁ and V ₁ , respectively.
V ₃ and V ₂ , and the selection potential is V ₆ ^R. In the initial state of the selection state, the selection potential V ₆ ^R is higher than the reference potential V ₆ ^S , the output of the comparator 39 is close to the positive power supply potential V _PP , and a current flows to the base of the NPN transistor 41 through the Zener diode 40 and the base resistor R _24. Flow to turn on the power supply potential V
_A current is caused to flow through the resistor R ₂₆ connected between _CC and the collector to drop the voltage, and the collector potential of the NPN transistor 41 becomes substantially negative power source potential V _EE .

[0047] between the power supply potential V _DD -V _SS, connect the PNP transistor 43 and the resistor R _28, the circuit connecting a resistor R ₂₇ to the base power supply potential V _CC -V _EE between signal V _DD -V of _SS
It is a conversion circuit which is a signal between. The polarity inversion signal P _Z is 1
Then, when the switch 42 is on, the transistor 41 causes a current to flow through the base resistor R _{27 to} the base of the PNP transistor 43 to turn it on, and the collector potential becomes V _DD ,
With the output T of the inverter 44 at 0 (V _SS ), Noah 45,
One input of the RS flip-flop composed of 46 is set to 0.

When the polarity inversion signal P _Z is 0 (V _EE ), the liquid crystal lighting potential, non-lighting potential, and non-selection potential are V ₆ and V ₆ , respectively.
V ₄ and V ₅ , and the selection potential is V ₁ ^R. In the initial state of the selection state, the selection potential V ₁ ^R is lower than the reference potential V ₁ ^S , the output of the comparator 33 is close to the positive power supply potential V _CC , and the PNP is generated by the Zener diode 34, the resistor R ₂₁ and the resistor R ₂₂ .
The base potential of the transistor 35 is set to V _CC to turn off the transistor, and the resistor R ₂₃ connected to the collector causes the collector to have a potential in the negative power supply potential V _EE direction.
If the switch 36 is off, the collector potential at this time is V _EE
Is.

When the polarity inversion signal P _Z is 0, P _Z ^* is 1
(V _CC ) turns on the switch 36, and the PNP transistor
The resistor R ₂₃ is connected in series to the base resistor R _{27 of} 43, and PN
Turn on the P-transistor 43 and set the collector potential to V _DD
And the output T of the inverter 44 is set to zero. That is, in the initial state of the selection state in which the reset signal R _O is 1, the detection signal T indicating the comparison between the selection potential V _X ^R applied to the row electrode and the reference potential V _X ^S is 0.
Is.

The selection signal according row electrodes to the liquid crystal shown in FIG. 1, the reference potential V _X ^S in response to determining that the time t to reach the (X = 1,6), selected in FIG potential The time t until V _X ^R reaches the reference potential V _X ^S is detected. Corresponding to the fact that the selection potential V _X ^R is closer to the power supply potential of the corrected selection potential V _X ^A than the row electrode of the liquid crystal, V _X ^S of FIG.
When the _X ^S and ^{_{V X 1S, V X S =}} (V X A -V X 1S) (R L +
Will be set to the R _T) / (reference potential _{R L + R T + R e} ) + V X 1S.

When the reset signal R _O becomes 0 (V _SS ),
The inverter 47 sets the reset input R ^* of the D-type flip-flop 50 and the up / down counters 57, 58, 59, 60 to 1 to bring it into operation. Since the detection output T indicating that the selection potential V _X ^R (X = 1, 6) has reached the reference potential V _X ^S is 0 after the reset is released, the D type of the RS flip-flop composed of the NORs 45 and 46. The data input to the flip-flop 50 remains 0, and the in-phase signal passing through the inverters 48 and 49 is used as the clock input CK.
The output Q of 1 transmits the signal of the data input D in synchronization with the rise of the clock CL from 0 to 1, but the output Q also remains 0.

[0052] Therefore a reset input R ^* also 0 of divider 51, D-type flip-flop 56 that the output Q of the D-type flip-flop 50 and the reset input R ^*, is also 0 and the output Q, the up-down counter 57 , 58, 59,
The B input of 60 and the C inputs of 57, 58 and 59 are also 0. The up / down counters 57, 58, 59, 60 enter the clock input CK ₁ of the first stage counter through the switch 54 which is turned on with the value 1 of the output Q obtained by inverting the output Q 0 of the D-type flip-flop 50 by the inverter 53. 1 of clock CL
Counts up in synchronization with the fall from 0 to 0.

There is a selection period for one row of the liquid crystal display within the time of one cycle of the n-th counter when the up-counter of the n-th stage from the first stage to the n-th stage is operated by the up-counter. The output Q _A of the down counter 60 remains 0, and the signals A and A ^* are 1 and 0, respectively. Compensation selection potentials V ₁ ^A and V ₆ ^A inputted to the comparators 33 and 39 from the analog switches 32 and 38 which are turned on by the signal A 1 are selection potentials V ₁ ^R and V ₆ ^R , and one of them is a liquid crystal display. It has been added to the row electrodes of the body.

When the polarity inversion signal P _Z is 1 and the selection potential V ₆ ^R applied to the row electrode of the liquid crystal display reaches the reference potential V ₆ ^S and becomes lower, the output of the comparator 39 becomes a negative power supply potential. Zener diode 40 and resistor R near V _EE
The base potential of the NPN transistor 41 is set to V _EE by ₂₄ and the resistor R ₂₅ to turn off the transistor. switch
Since the switch 42 is turned on and the switch 36 is turned off, a resistor R ₂₇ is connected in series to a resistor R ₂₆ that guides the potential V _CC (≧ V _DD ), thereby biasing the PNP transistor 43 between the base and emitter in the reverse direction. The transistor 43 turns off. The collector potential becomes V _SS at the resistor R ₂₈ , and the detection signal T is output at 1 from the inverter 44.

When the polarity inversion signal P _Z ^* is 1 and the selection potential V ₁ ^R applied to the row electrode of the liquid crystal display reaches the reference potential V ₁ ^S and becomes higher, the output of the comparator 33 becomes negative. When the power supply potential V _LL is approached, a current flows through the Zener diode 34 and the base resistor R _{21 to} the base of the PNP transistor 35 to turn it on. The current between the emitter and collector of the transistor 35, which is approximately V _CC -V across the resistor R _23.
The voltage of _EE is applied and the collector potential becomes almost V _CC .
Since the switch 36 is on and the switch 42 is off, the resistor R ₂₇ is connected to the collector of the transistor 35, and the base and emitter of the PNP transistor 43 are reversely biased to turn off the transistor 43 and the resistor R _{27. At 28} , the collector potential is set to V _SS, and the detection signal T output from the inverter 44 is 1.

Since the input T to the NOR gates 45 and 46 is 1 and R _O is 0, the output to the data input D of the D flip-flop of the RS flip-flop becomes 1, and this state shifts to the selection of the next row. When this happens, the reset signal R _O continues until it becomes 1. When the clock CL that is the clock input CK of the D-type flip-flop 50 rises from 0 to 1, the signal of the data input D is transmitted to the output Q and the reset input R ^* of the divider 51 and the D-type flip-flop 56 is changed. 1 and the B input of the up / down counters 57, 58, 59, 60 is set to 1.

Since the output Q of the D-type flip-flop 50 is 1, the switch 55 is turned on, the output Q of the divider 51 is inverted by the inverter 52, and a signal is output to the clock input CK ₁ of the up / down counter 57. To do. With the output 0 of the inverter 53, the switch 54 is turned off. When the clock CL is 1, the reset of the divider 51 is released, and the signal of the double cycle of the clock CL switched as the clock input CK ₁ of the first stage up / down counter 57 at that time is 1, and the up / down counter 57 C of 58, 59
Output Q of D-type flip-flop 56 that outputs a signal to the input
Is 0.

When the clock input CK ₁ of the first stage of the up / down counter is 1, the C input is 0 and the B input is 1, the clock inputs CK ₁ , CK ₂ ... CK _n , C of each stage.
K _A becomes 1, and the inside of the counter is in a correction state for switching from the up counter to the down counter. Next, when the clock CL falls from 1 to 0,
The clock input CK of the D-type flip-flop 56 receives the inverted signal CL ^{* of the} clock CL by the inverter 48, so that the signal of the data input D is transmitted to the output Q to become 1 and the C input of the up / down counter becomes 1 And

Since both the C input and the B input of the up / down counters 57, 58, 59, 60 are 1, the up / down counter is in the down counter mode, and the double cycle clock signal is input to the first stage counter clock input. CK ₁
The divider 51, which outputs as a clock, uses the in-phase signal passing through the inverters 48 and 49 as the clock CL as the clock input CK, and outputs a clock signal having a double cycle in synchronization with the fall of the clock CL from 1 to 0. . The up / down counters 57, 58, 59, 60 count down in synchronization with the rise of the signal which becomes the clock CK ₁ of the first stage counter from 0 to 1. Immediately after switching the mode of this up / down counter, the clock CK ₁ of the first stage counter
When 0 is 0, each output Q ₁ , Q ₂ ... Q _n , Q _A of the counter which is a down counter is an up counter before mode switching and correction of the internal state of the counter. Outputs Q ₁ , Q ₂ ... Q _n , Q
Same as _A.

As the clock CL advances, the outputs Q ₁ , Q _2, ... Q _n , Q _{A of} the up / down counter pass 0, 0, ... 0, 0 at the beginning of the selection period, 1, 1 ,. 1
When down-counting is performed, the signals A and A ^* become 0 and 1, respectively, and the analog switches 32 and 38 are turned off, the analog switches 31 and 37 are turned on, and the uncorrected selection potentials are set as the selection potentials V ₁ ^R and V ₆ ^R. One of V ₁ and V ₆ is selected, one of them is applied to the row electrode of the liquid crystal display, and the state is maintained until the selection of the next row is started.

[0061] selection period early, the reset signal R _O after the initial setting of the control circuit is 1, the reset signal R _O point starts to operate becomes 0 t _O, selection potential of the row electrodes of the liquid crystal display body V _The correction selection potential V _X ^A is added as _X ^R (X = 1, 6), the up-down counter continues to count up, reaches the reference potential V _X ^S , sets the detection signal T to 1, and switches the mode of the up-down counter. T ₁ when the B input for is set to ₁ , t ₂ when the corrected internal down-counting of the up-down counter starts, and the up-down counter continues to down-count and the count content has passed all 0s and all 1s. until just before the time point t ₃ when made, the correction selection potential V _X ^a are added as a selection potential V _X ^R the row electrodes of the liquid crystal display body.

During the selection period from the time t ₃ when the content of the counter becomes all 1, the selection potential V _X ^R of the row electrode of the liquid crystal display is added in place of the non-correction selection potential V _X.
The control circuit of FIG. 4 uses the clock CL from t ₀ to t _1.
Since the time is counted up in units of one cycle and the time is counted down in units of two cycles of the clock CL between t ₂ and t ₃ , (t ₃ −t ₂ ) = 2 (t ₁
−t ₀ ), and the proportional coefficient f shown in FIG. 1 is 2.

That is, when a row on the liquid crystal display is selected,
The time (t ₁ −t ₀ ) from the initial t _{0 of the} selection period of the row to the time point t ₁ at which the signal reaches the reference potential is measured and detected by the up counter, and f is proportional to the time.
(T ₁ -t ₀₎ of the time, the correction selected from switched t ₂ down counter for measuring a clock previous f times the period until the contents of the counter becomes all zero potential V _X ^A _(X =
1, 6) as the selection potential V _X ^R, and thereafter, the liquid crystal is driven with the non-correction selection potential V _X as the selection potential V _X ^R from t ₃ when the counter contents are all 1 to the time when the selection period ends. There is.

In FIG. 4, the comparators 33 and 39, which compare the corrected selection potential with the reference potential, divide the power supply voltage into V _CC -V _LL and V _pp -V _EE , respectively, but V _CC -V
_If you use a comparator that operates on the power supply potential of _EE , you can use only one comparator, 33 to 36, 39 to 42, and resistors R _{21 to} R.
₂₆ is omitted, the polarity inversion signal P _Z is 1 (V _CC ) and V ₆ ^S , P _Z is 0 (V _EE ) and V is the non-inverting input of the comparator.
The ₁ ^R connected, V ₆ in the polarity inversion signal P _Z is 1 to the inverting input of the comparator ^R, connecting the V ₁ ^S at P _Z is 0, by connecting one end of a resistor R ₂₇ to the output of the comparator , The input to the base of the PNP transistor 43 through the resistor R _27, the detection circuit portion of the selection potential applied to the row electrode can be simplified.

The D-type flip-flop shown in FIG. 5 is in a quiescent state when the reset input R ^* is 0 (V _SS ), the outputs of the NANDs 73 and 76 are 1 (V _DD ), and the output Q from the inverter 78 is set.
To 0. When the reset input R ^* is 1, the operation is enabled.
Clock input CK is 0, clock input C of its inverted signal
When K ^* is 1, the clock-controlled inverters 72 and 77 are turned on, 74 and 75 are turned off, and the data input D is applied to the inverter 7
1. Write through the clock-controlled inverter 72 to make the signal M in-phase with D, and input the clock-controlled inverter 74 for holding data and the input of the clock-controlled inverter 75 for writing to the signal S through the NAND 73 to invert M Inverter 78 waits as a signal and outputs in-phase signal with signal S held by NAND 76 and clock control type inverter 77.
Output as Q.

When the clock input CK is 1 and CK ^* is 0, the clock control type inverters 72 and 77 are off, and 74 and 75 are on, and the clock control type inverter 74 further inverts the input of the inverted signal of M in the standby state. The clock control type inverter 75 inverts the input of the inverted signal of M in the standby state and writes it to make the signal S in phase with the signal M and operate the inverters. Through the output Q, an in-phase signal of S, that is, M is output. Clock CK is 0 and signal M is the same as data D,
When CK is 1 and the signal S is the same as the signal M, the data D is transmitted to the output Q having the same phase as S.

The divider shown in FIG. 6 has a reset input R ^* of 0.
In the stationary state, the outputs of NANDs 82 and 85 are set to 1, and the inverter 87 outputs Q = 0. At this time, when the clock input is CK = 0 and CK ^* = 1, the clock control type inverter 81 is off, 83 is on and holds M = 0, the clock control type inverter 84 is on, 86 is off and S = 0. Become. When the reset input R ^* is 1, the operation is enabled. It is held at M = 0 when the clock input is CK = 0 and CK ^* = 1, and remains written at S = 0 and Q = 0. When the clock input is CK = 1 and CK ^* = 0, the clock control type inverter 81 is turned on, 83 is turned off, the inverted signal of S is written in M to set M = 1, the clock control type inverter 84 is turned off, and 86 is turned on. Then, S = 0 is held, and the output Q = 0.

Subsequently, clock inputs CK = 0 and CK ^* = 1
Then, the clock-controlled inverter 81 turns off, 83 turns on and holds M = 1, and the clock-controlled inverter
84 is turned on and 86 is turned off, the in-phase signal of M is written in S, S = 1 is set, and output Q = 1 is set. When the clock further advances and CK = 1 and CK ^* = 0, an inverted signal of S is written in M to set M = 0, S = 1 is held and Q = 1, and C
When K = 0 and CK ^* = 1, M = 0 is held and the in-phase signal of M is written in S to set S = 0 and the output Q = 0. The clock input signal CK is CK = 0, 1, 0, 1,
Operates with a two-cycle CK ^{* of} 0 to output Q of the divider
Operates for one cycle of Q = 0, 1, 0.

In the up / down counter of FIG. 7, when the input B for mode switching is 0, the inverting input B ^* is set to 1, the clock control type inverter 99 is turned off, and 97 is turned on to become an up counter. At this time, the circuit composed of 91 to 97 is the same as the circuit composed of 81 to 87 of FIG. 6, and every time the input signal CK of the clock operates for one cycle and becomes 0, the output Q changes and counts up. .

When the input B for mode switching is 1, B ^* = 0 and C = 1, the clock control type inverter 99 is turned on,
97 turns off and becomes a down counter. Signal M and input C
Is passed through an AND 98 and inverted by a clock control type inverter 99 to obtain an output Q. Every time the input signal CK of the clock operates for one cycle and becomes 1, the output Q changes and down counts.

When the up counter is switched to the down counter, the output Q changes from the in-phase signal of S to the inverted signal M of M.
^* Will be output, but at the time of switching CK = 0, C
If K ^* = 1, clock controlled inverters 93, 94
Is on, 91 and 96 are off, and M is in-phase signal with S
However, the inverted signal is output from Q.

When the mode switching input B is changed from 0 to 1,
When the input C is delayed from B and changed from 0 to 1, there is a correction period of C = 0 at the time of mode switching, and the output Q is set to 1 in a pulse shape through the AND 98 and the clock control type inverter 99, and the up / down counter of the next stage. Clock input of C
It is assumed that K = 1 and CK ^* = 0. At this time, if the clock input of the first stage up / down counter is set to CK = 1 and CK ^* = 0, the clock control type inverters 91 and 96 are turned on, 93 and 94.
Turns off and waits for M as an inverted signal of S. Input C
After the correction becomes 1, the inverted signal of M, that is, the in-phase signal of S before correction is output to the output Q through the AND 98 and the clock control type inverter 99, and the up counter shifts to the down counter. are doing.

FIG. 8 is a signal waveform diagram showing the operation of the control circuit of FIG. 4, showing the case where the number of stages of the up / down counter n = 6 and the proportional coefficient f = 1 shown in the figure. When the reset signal R _O is 1, the up / down counter outputs Q ₁ , Q
₂ , ... Q ₆ and Q _A are initialized to all 0s, and one row of the liquid crystal display is in the selected state, and the selection potential V _X ^R (X =
The correction selection potential V _X ^A is applied as 1, 6). When the reset signal R _O is 0, it continues counting up from the time t _O ,
When the selection potential V _X ^R crosses the reference potential V _X ^S , the detection signal T
Is changed from 0 to 1 and time is detected in the state of the counter at the time point t ₁ when the clock CL rises to 1.

At time t ₁ , the up / down counter is switched from the up counter to the down counter, and t
Move to ₁ ', enter the correction period inside the counter. Clock signal CL which is the clock input of the _first stage up / down counter, output signals Q ₁ , Q ₂ which are the clock inputs of the 2nd stage, 3rd stage ...
...... Q ₅ and output signal Q ₆ which is the clock input of the up / down counter for outputting the signal Q _A for producing the signals A and A ^* for controlling the switching between the correction selection potential V _X ^A and the non-correction selection potential V _X Are all 1, and subsequently, at the time t ₂ when the clock CL becomes 0, the output of the counter is the same as that at the time t ₁ .

[0075] continue to down-count from the time t _2, the time up to the time t ₃ when the output of the up-down counter is all one past the all 0, is the same as the time from the time t ₀ to t _1, initial The corrected selection potential V _X ^A is applied as the selection potential V _X ^R until time t ₃ . At time t ₃ , the selection potential V
_X ^R is replaced with the non-correction selection potential V _X and is applied to the row electrode until the selection period shifts to the next row. When the reset signal R ₀ is 1 when the next row is in the selected state, the outputs Q ₁ , Q ₂ , ... Q ₆ , Q _A of the up / down counters have returned to the initial state of all 0s.

In the correction period shown in FIGS. 4 and 8 where f = 2 and f = 1, respectively, the clock cycle is f ₀ (real number) times as many times as the down count, and the proportional coefficient shown in FIG. f can be f ₀ . In this case also, time t ₁ '
When changing the clock frequency with, the clock input of the first stage of the up / down counter is set to 1 so that the clock advances from the same value.

FIG. 9 is a row-side drive circuit diagram used in the image display device of the present invention, and is a circuit diagram of a drive integrated circuit for sending a signal to the m-th row of the row electrodes of the liquid crystal display body having M rows. . Figure
10 (a) and 10 (b) are circuit diagrams of AND and NAND used in the drive circuit diagram of FIG. 9, respectively. 107 and 108 are ANDs shown in (a), and 105 and 106 are NANDs shown in (b). Is.

Reference numeral 101 transfers a vertical start signal V _ST by a vertical clock signal LP which is periodically repeated in each horizontal scanning period, and signals (D1) and D (2) are brought into a selected state every horizontal scanning, that is, every row. ), ... A shift register that outputs D (m). The vertical clock signal LP is the same signal as the enable signal or the clock signal for writing the image signal row by row in the latches or D-type flip-flops of each column of the drive circuit on the column side. V ₀ is an output signal slightly delayed from D (m) and becomes a vertical start signal of an integrated circuit to be connected next.

The AND 102 transfers the output D (1) of the shift register to the input I _Q of the level conversion circuit 103 by setting the control signal Y of the selection potential output to 0 and the inverter 115 to 1.
It is output as Q is converted from the potential of V _DD -V _SS to a signal of the potential of the V _DD -V _BB at 103. Q ^* is an inverted signal of Q. 104 is a similar level conversion circuit, which uses the output D (1) of the shift register as an input I _D and converts the potential of V _DD -V _{SS to} the potential of V _DD -V _BB and outputs the output signal D and its inverted signal D ^*. Is making. The polarity inversion signal P _O is 116, 117, 11
The circuit of 8 converts the potential of V _DD -V _SS into a signal of the potential of V _DD -V _BB and buffers it at 119 and 120 to become the signal P and its inverted signal P ^* .

With two inputs of the selection / non-selection signals Q / Q ^* and the polarity inversion signal P / P ^* , AND 108, 107 and NAND 105,
106, the N-channel transistors 112 and 111 and the P-channel transistors 109 and 110 are controlled to select a potential from the liquid crystal drive potential bus V, and the signal R (1) of the row electrode of the first row is output. ing. The N-channel transistor 112 is for selecting the selection potential V ₆ ^R , 111 is for selecting the non-selection potential V ₅ , the P-channel transistor 109 is for selecting the selection potential V ₁ ^R , and 110 is for selecting the non-selection potential V _2. The potentials V ₆ ^R and V ₁ ^R are the potentials shown in FIG.

For (Q, P), AND with (1, 1)
The transistor 112 is turned on by 108, and R (1) is set to the selection potential V ₆ ^R, and at (0, 1), the transistor 110 is turned on by the NAND 106 and set to the non-selection potential V ₂ .
When the polarity is inverted (1, 0), the transistor 109 is turned on by the NAND 105, R (1) is set to the selection potential V ₁ ^R , and when (0, 0), the transistor 109 is turned on by AND 107.
11 is turned on to set the non-selection potential V ₅ . When the control signal Y for selecting potential output is 1, the inverter 115
02 outputs 0 and Q = 0, and the non-selection potential corresponding to the polarity inversion signal P is output from R (1).

Output signals D, D ^{* of the} level conversion circuit 104
Controls the N-channel transistor 114 and the P-channel transistor 113 connected to the output line of the row electrode signal R (1), and the transistor 11 during the selection period of D = 1.
4 and 113 are turned on, the signal of the row electrode related to the liquid crystal is guided to the detection line inside the integrated circuit to be V _I ^R, and the switch that is turned on while the output from the first row to the m-th row outputs the selection potential sequentially It is taken out of the integrated circuit and designated as V ^R.

Output D of the first row of shift register 101
(1) and the output of the RS flip-flop composed of the NORs 121 and 122 for inputting the output D (m + 1) corresponding to the (m + 1) th row next to the mth row, respectively. The potential of V _DD -V _SS is converted into the signal of the potential of V _DD -V _BB , and N-channel transistor 126 and P
Controls each channel transistor 125,
Period for sequentially outputting selection potential from row to the m-th row, turns on the transistor 126 and 125, are taken out as V ^R the signal V _I ^R of the integrated circuits inside the detection line to the outside.

That is, inside the integrated circuit which supplies signals to the row electrodes of the first row to the m-th row, analog switches (125, 126) which are turned on during the period when the selected potential is sequentially sent from the integrated circuit to the row electrodes. , And the analog switches (113, 114) for detection of each row that are turned on while the row electrode of each row is outputting the selection potential are connected in series to output the signal of the row electrode of each row to the outside of the integrated circuit. lead as V ^R, the detection signal V ^R the row electrodes are connected in common among a plurality of driving integrated circuits for M rows across has an output of m rows respectively.

With this arrangement, the capacitance of the detection line can be reduced to a plurality of parts as compared with the case where the detection line inside the integrated circuit is directly exposed to the outside and is commonly connected between a plurality of driving integrated circuits.
The change in the signal of the selected row electrode of the liquid crystal display can be more quickly detected. Control signal Y for selecting potential output
As shown in FIG. 4, the reset signal R _O shown in FIG. 4 and FIG. 8 is used to set the potential of the detection line to the non-selection potential while outputting the non-selection potential to the row electrode at the initial stage of each selection period. When the data is output to the row electrode and detected, the condition becomes more constant than when there is no initial setting, and accurate detection is possible.

Circuit 128, similar to circuit 127 in the first row,
Numeral 129 respectively produces the signals R (2) and R (m) of the row electrodes of the second row and the m-th row from the outputs D (2) and D (m) of the second row and the m-th row of the shift register. .

When the detection signal V ^R is used as a signal to be compared with the reference potentials V ₁ ^S and V ₆ ^S of the comparators 33 and 39 in FIG. 4, the selection potentials V ₁ ^R and V ₆ ^R are output from the comparator. Separated and used only for the drive potential of the liquid crystal of the drive circuit on the row side,
One comparator operating at the power source potential of V _CC -V _EE is used, 33 to 36, 39 to 42 and resistors R _{21 to} R ₂₆ are omitted, and the polarity inversion signal P _Z is 1 at the non-inverting input of the comparator. And V
₆ ^S, connect the V ^R at P _Z is 0, V in the polarity inversion signal P _Z is 1 to the inverting input of the comparator ^R, connecting the V ₁ ^S at P _Z is 0, the resistance to the output of the comparator R Connect one end of ₂₇ .

Corresponding to detection of the time t until the row electrode selection signal of the liquid crystal shown in FIG. 1 reaches the reference potential V _X ^S (X = 1, 6), the detection signal in this case is detected. The time t until V ^R reaches the reference potential V _X ^S is detected. An analog switch that outputs an average resistance of the row electrode of the liquid crystal display R _L , a resistance when the selection potential output transistor 112 or 109 of FIG. 9 is turned on R _T , and a corrected selection potential V _X ^A of FIG. 38 or 32 is the output resistance including the resistance when turned on and R _e, when the V _X ^S in FIG. 1 and V _X ^1S, V _X ^S in this case is V
^{_{X S = (V X A -V}} X 1S) R L / (R L + R T + R e) + V
It will be set to the standard potential of _X ^1S .

Average resistance R _L of the row electrodes of the liquid crystal display
Is set to be smaller than the circuit resistance such as the on resistance of the analog switch or transistor through which the correction selection potential is applied, the detection close to that of FIG. 1 can be performed, and the analog switches 38 and 32 in FIG. 4 can be connected in series. The connected additional resistance can be eliminated and R _e can be the output resistance of the analog switch only.

In FIG. 10 (a), reference numeral 131 denotes AND in which the signals Q and P are input and S is output. This is the signal P
N-channel transistor 133 controlled by and P-channel transistor controlled by inverted signal P ^* of P 1
A signal Q is input to the input of a switch in which 32 are connected in parallel, a signal S is output from the output, an N-channel transistor 134 controlled by the signal P ^* is connected to the output, and the source of the transistor 134 is set to the potential of V _BB . Shows the circuit
The circuits 107 and 108 in FIG. 9 have this circuit configuration.

In FIG. 10B, reference numeral 135 indicates a NAND in which the signals Q and P are input and S ^* is output. This is the signal P
N-channel transistor 136 controlled by and the P-channel transistor controlled by P inversion signal P ^*
The inverted signal of Q, Q, is input to the switch connected in parallel with 137.
^* Placed, so as to extract a signal S ^* from the output, P-channel transistor 138 which is controlled by the signal P at the output
Is connected, and the source of the transistor 138 is connected to the potential of V _DD . 105 and 106 in FIG. 9 have this circuit configuration.

FIG. 11 is a signal waveform diagram showing the operation of the row side drive circuit of FIG. Vertical start signal V _ST is 1 (V _DD )
During the period of, the vertical clock signal LP has a narrow width of 0 (V _SS ).
Of located so as to cover the timing when 1 (V _DD) after issuing a pulse, the vertical clock signal LP at a vertical start signal V _ST is 1 in synchronization with the timing of rises 1, the first row of the shift register When the output D (1) becomes 1 and the vertical clock signal LP next rises to 1, the output D (1) of the first row of the shift register is 0 and the output D (2) of the second row is
Has changed to 1. Each time the vertical clock signal LP rises to 1, the 1 row of the shift register is sequentially moved.

The reset signal R _O is the vertical clock signal LP
Becomes 1 in synchronism with the timing of rising to 1, and the control circuit for the selection potential of the row electrode described in FIG. 4 is set to the initial state and becomes 0 after the set period. The time when the polarity inversion signal P _O changes is also the time when the vertical clock signal LP rises to 1.

As the control signal Y for outputting the selection potential of FIG.
The reset signal R _O is used. Signal R (1) is output D (1) of the first row of the shift register becomes 1 in the first row of row electrodes, a non-selective for the polarity inversion signal P _O is 1 the initial Riseto signal R _O is 1 The potential V ₂ is output. The reset signal R _O is the selection potential is output becomes 0, will change while charging the capacitance between the column electrodes crossing the row electrodes of the first row of the liquid crystal display body. After the reference potential V ₆ ^S has passed, the corrected selection potential V ₆ ^A is output until after the period ft shown in FIG. 1, and thereafter the non-selection potential V ₆ is output.

Output D (1) of the first row of the shift register
Becomes 0, the output D (2) of the second row becomes 1, and when the selected state shifts to the next row, the signal R of the row electrode of the first row is output.
(1) changes while discharging the capacitance between the row electrode of the first row of the liquid crystal display and the column electrode crossing it, and the non-selection potential V ₂
It has become. When the polarity inversion signal P _O becomes 0, it becomes the non-selection potential V ₅ . The power supply potential is V _DD ＞ V ₁ ^A ＞ V ₁ ＞
V ₂ > V ₃ > V ₄ > V ₅ > V ₆ > V ₆ ^A > V _BB .

FIG. 12 is a block diagram of the image display device of the present invention. 141 is an upper screen of the liquid crystal display, and 142 is a lower screen of the liquid crystal display. Reference numerals 143 and 144 denote left and right driving circuits on the row side that send selection / non-selection potential signals to the row electrodes of the upper screen 141 of the liquid crystal display, and 147 indicates whether the column electrodes of the upper screen 141 of the liquid crystal display are illuminated or not. It is a drive circuit on the column side that sends a lighted image signal.
Similarly, 145 and 146 are left and right driving circuits on the row side that send selection / non-selection potential signals to the row electrodes of the lower screen 142 of the liquid crystal display, and 148 is the column electrode of the lower screen 142 of the liquid crystal display. It is a drive circuit on the column side that sends the image signal of lighting and non-lighting to.

Reference numeral 151 denotes a central processing unit (CPU),
Reference numeral 2 denotes a logic control circuit including an image memory for storing an image to be displayed on the liquid crystal display, and a logic signal and a control circuit for the image signal sent to the drive circuits on the row side and the column side of the liquid crystal display.
Image data from a storage device / peripheral device inside or outside the computer is processed in a form suitable for the image memory of the liquid crystal display unit, and the CPU 151 outputs the logic control circuit 152.
Sent to

The left and right drive circuits 143 and 144 on the row side of the upper screen from the logic control circuit 152 are composed of a vertical clock signal LP, a vertical start signal V _ST , a control signal Y for selecting potential output, a polarity inversion signal P _{O and the} like. An upper screen vertical logic signal is supplied by a UVL bus, and a horizontal clock signal, a horizontal start signal, an image signal, a latch enable signal, and a polarity inversion signal P are supplied from the logic control circuit 152 to the column side drive circuit 147 of the upper screen.
_An upper screen horizontal logic signal composed of _O or the like is supplied by a UHL bus.

The lower screen vertical logic signal is fed to the left and right drive circuits 145 and 146 on the row side of the lower screen from the logic control circuit 152 by the DV.
It is sent by the L bus, and the drive circuit 148 on the row side of the lower screen
The lower screen horizontal logic signal is sent through the DHL bus.

Reference numeral 153 denotes a power supply circuit, which has the power supply potentials V _CC , V _DD , V _SS , V _PP , V _LL , V _BB shown in FIGS. 2 and 4.
In addition to V _EE and V _ZZ , lighting potentials and non-correction selection potentials V ₁ and V ₆ , non-lighting potentials V ₃ and V ₄ , non-selection potential V ₂ ,
A liquid crystal drive potential of V ₅ is generated and supplied by the V bus. Further, the power supply circuit 153 creates correction selection potentials V ₁ ^A and V ₆ ^A and reference potentials V ₁ ^S and V ₆ ^S , and outputs these correction potentials via the V ^A bus.

Reference numeral 149 is a control circuit similar to the circuit shown in FIG. 4 for correcting the selection potential of the row electrodes on the upper screen. From the logic control circuit 152, a clock signal CL and a reset signal R
_O , polarity inversion signals P _Z , P _Z ^{* and} other upper screen correction logic signals are sent via the UAL bus, and the non-correction selection potentials V ₁ , V ₆ and correction selection potentials are supplied from the V and V ^A buses of the power supply circuit 153. V ₁ ^A ,
V ₆ ^A , reference potentials V ₁ ^S and V ₆ ^S are supplied. Further, the potential signal of the row electrode in the selection period from the left and right drive circuits 143 and 144 on the row side of the upper screen is taken in the upper screen detection signal line of UV ^{R to} the control circuit 149 for correcting the selection potential. There is.

The control circuit 149 for correcting the selection potential is such that the potential signal of the row electrode in the selection period sent by the detection signal line UV ^R is
The time t until reaching the reference potential V ₁ ^S or V ₆ ^S is detected,
Further until the time of ft, the selection potential UV ₁ ^R of the row electrode on the upper screen,
UV ₆ ^{R is set} to the correction selection potentials V ₁ ^A and V ₆ ^A, and during the subsequent selection period, it is set to the non-correction selection potentials V ₁ and V _{6 and} the left and right sides of the row on the upper screen are driven by the bus V of the drive potential of the liquid crystal. The selection potential is supplied to the circuits 143 and 144.

In the control circuit 150 for correcting the selection potential of the lower screen, the lower screen correction logic signal from the logic control circuit 152 is DAL.
Of the power supply circuit 153 and the non-correction selection potentials V ₁ and V ₆ and the correction selection potentials V ₁ ^A and V ₆ ^A from the V and V ^A buses of the power supply circuit 153.
The reference potentials V ₁ ^S and V ₆ ^S are supplied, and the potential signals of the row electrodes in the selected period from the left and right drive circuits 145 and 146 on the row side of the lower screen are taken in by the lower screen detection signal line of DV ^R. ing.

Control circuit for correcting selected potential on lower screen 150
Is the time t until the potential signal of the row electrode in the selection period sent by the detection signal line DV ^R reaches the reference potential V ₁ ^S or V ₆ ^S.
Is detected, and the selection potentials DV ₁ ^R and DV ₆ ^R of the row electrodes on the lower screen are set to the correction selection potentials V _1A and V ₆ ^A until the time ft, and the non-correction selection potentials V ₁ and V ₆ are set during the subsequent selection period. ₆ , the left and right drive circuits on the row side of the lower screen with the bus V of the liquid crystal drive potential 1
The selection potential is supplied to 45 and 146.

The image display device of FIG. 12 has a dual matrix configuration in which one row at a time is selected at the same time as the upper screen 141 and the lower screen 142, but the drive potential applied to the liquid crystal from the drive circuits on the row side and the column side is selected. The polarity may be reversed between the upper screen and the lower screen. With such a configuration of simultaneous selection of a plurality of rows, as in the case of individually correcting the selection potentials supplied to the row-side drive circuits on the upper screen and the lower screen, individual selection potential correction is performed on the potential signals of the selected electrodes. The control circuit is used to individually detect and supply the selection potential.

The upper screen is composed of pixel groups of M rows from the 1st row to the Mth row, and the lower screen is composed of pixel groups of the (M + 1) th row to the 2nd M row. It is driven by the simultaneous selection of the Jth row and the (M + J) th row of the lower screen, or the simultaneous selection of the Jth row of the upper screen and the (2M + 1-J) th row of the lower screen.

The left and right driving circuits 143, 144 and 145, 146 on the row side of the upper screen 141 and the lower screen 142 are configured such that one row of each of the left and right driving circuits simultaneously outputs a selection potential to the same row electrode. At that time, the detection signal line of the selection potential can be wired only to the left side row driving circuits 143 and 145 close to the control circuits 149 and 150 for correcting the selection potential. The control circuit for correcting the selection potential controls the selection potential in the polarity to which the selection potential is applied from the correction selection potential to the non-correction selection potential in each selection period, but selects the selection potential not in the polarity to which the selection potential is added to the non-correction selection potential. The correction selection potential may be output.

FIG. 13 is a power supply circuit diagram of another embodiment for producing the liquid crystal drive potential of the image display device of the present invention, in which the reference potential V ₁ ^S is set with respect to the set correction selection potentials V ₁ ^A and V ₆ ^A. It takes a method of adjusting V ₆ ^S. Resistor R is connected between the power supply potential V _CC and V _ZZ
The voltage is divided by ₈ and the variable resistor R ₉ , and the collector is input to the base of the PNP transistor 161 having the V _ZZ potential, and the resistors R ₃ , R ₁ , R ₁ , R ₂ , R ₁ , between the V _CC potential and the emitter.
R ₁ and R ₃ are connected in series, and the potential at the connection point of each resistor is output through voltage followers 162, 163, 164, 165, 166 and 167 to output V ₁ , V ₂ , V ₃ , V ₄ , V ₅ and Creating a potential of V ₆ . V ₁ , V ₂ and V ₃ are lighting potentials,
The non-correction selection potential at the non-selection potential and the non-lighting potential is V ₆ , and V ₆ , V ₅ , and V ₄ are the lighting potential, the non-selection potential, and the non-lighting potential in the polarity inversion frame, and the non-correction at that time is performed. The selection potential is V ₁ .

The correction selection potential V ₆ ^A is the emitter potential V _EE of the transistor 161, and the correction selection potential V ₁ ^A in the polarity inversion frame is the V _CC potential. Between the V _CC potential and the emitter potential V _{EE of the} transistor 161, further resistors R ₁₄ and R
_15, a variable resistor R _16, resistors R _15, R ₁₄ are connected in series, close resists V _EE potential emitters R _14, the reference potential V ₆ ^S from the connection point of the R _15, V _CC potential near the resistor R _14, The reference potential V ₁ ^S in the polarity inversion frame is taken from the connection point of R ₁₅ .

Each liquid crystal drive potential is determined by the resistance ratio obtained by dividing the power supply potential V _CC and the emitter potential V _{EE of the} transistor 161. Supply voltage variable resistor R ₉ (V _CC -
The voltage of (V _CC -V _EE ) is determined with respect to V _ZZ ) and the liquid crystal drive potentials of V ₁ ^A , V ₁ , V ₂ , V ₃ , V ₄ , V ₅ , V ₆ and V ₆ ^A are set. The reference potentials V ₁ ^S and V ₆ ^S are adjusted by the variable resistor R ₁₆ with respect to the correction selection potentials V ₁ ^A and V ₆ ^A which are the potentials of V _Cc and V _EE .

When the power supply circuit of FIG. 13 is used, the potential V
The power supply potentials V _DD and V _SS of the logic circuit portion of the drive circuit that drives the row electrodes and the column electrodes of the liquid crystal display with respect to _CC and V _EE , and the power supply potentials V _DD and V _BB of the output circuit portion are V _CC = V _DD , V _BB = V
_EE . The positive and negative power supply potentials of the operational amplifiers having voltage followers 162 to 167 are V _CC and V _EE . Capacity C ₁ ,
C ₂ , C ₃ , and C ₆ are for stabilizing the potential of the connection point, and V
It is connected between _CC potential and each drive potential.

FIG. 14 is a detection circuit diagram of the potential signal of the row electrode of another embodiment used in the control circuit for correcting the selection potential of the row electrode of the image display device of the present invention. The reference potentials V ₁ ^S and V ₆ ^S determined by the power supply circuit of FIG. 13 are input to the non-inverting input terminal of the comparator 171 and the inverting input terminal of the comparator 172, respectively, and the potential signal V _{1 of the} row electrode during the selection period is input. ^R and V ₆ ^R are input to the inverting input terminal of the comparator 171 and the non-inverting input terminal of the comparator 172, respectively, and the polarity inverting signal P _Z is 1 for the output of the comparator 172.
It is taken out by the switch 174 which is turned on at (V _CC ), and the output of the comparator 171 is when the polarity inversion signal P _Z is 0 (V _EE ).
It is taken out by a switch 173 which is turned on by 1 of the inverted signal P _Z ^* .

The positive and negative power supply potentials of the comparators 171 and 172 are V _CC and V _EE , and when the polarity inversion signal P _Z is 1, the potential signal V ₆ ^R of the row electrode during the selection period is greater than the reference potential V ₆ ^S. When it becomes low, the comparator 172 changes from the potential near V _{CC to} the potential near V _EE , and the polarity inversion signal P is generated in the polarity inversion frame.
_{When Z} ^* is 1, when the potential signal V ₁ ^R of the row electrode during the selection period becomes higher than the reference potential V ₁ ^S , the comparator 171 changes from the potential near V _{CC to} the potential near V _EE .

At the potential near the V _CC of the comparator within the initial selection period led by the switches 174 and 173, the path of the zener diode 175 and the resistor R ₂₇ does not flow current to the base of the PNP transistor 176, and the resistor R _{The reference numeral 29} turns off the transistor 176 by using the base as the V _CC potential, the collector becomes the potential of V _{SS by} the resistor R ₂₈ , and the buffer 177 outputs 0 (V _SS ) as the detection signal T. At the potential near V _EE of the comparator after the potential signal of the row electrode in each selection period exceeds the reference potential, a current is passed through the Zener diode 175 and the resistor R _{27 to} the base of the PNP transistor 176 to turn on the transistor, Due to the current flowing from the collector through the resistor R ₂₈ , the potential of the collector becomes almost V _CC , and the buffer 177 detects the detection signal T as 1 (V _CC ).

Also in FIG. 14, the potentials V _CC and V _EE and the power source potential V _DD of the drive circuit for driving the row electrodes and the column electrodes of the liquid crystal display,
V _SS and V _BB are V _CC = V _DD and V _BB = V _EE . Potential signal V ₁ ^R row electrode selection period, as V ₆ ^R can be used in common detection signal V ^R the row electrodes shown in row side driving circuit of FIG. The circuit of FIG. 14 is a control circuit for correcting the selection potential of the row electrode of FIG. 4, 33 to 36, R _{21 to} R ₂₃ , 39 to 44, R ₂₄ to
It is used in the detection circuit portion indicated by R ₂₈ .

[0116]

According to the present invention, in a simple matrix type image display device in which liquid crystal is sandwiched between orthogonal row electrodes and column electrodes, when a selection signal is applied to a row electrode of a liquid crystal display, the potential of the row electrode is initially set. The time to reach the reference potential is detected, and the time correction selection potential proportional to that time is set as the non-correction selection potential, and the polarity of the drive signal applied to the liquid crystal is inverted in the frame cycle to perform AC drive. It is the one.

The capacitance between the selected row electrode and the column electrode increases as the number of white portions increases. Conventionally, the response waveform of the selection signal changes depending on the amount of black and white of each row, and the driving effective voltage fluctuates. In the present invention, the longer the detection time for the selection signal applied to the row electrode to reach the reference potential, the longer the display unevenness caused by the changes in the brightness of white and the darkness of black. A correction selection potential larger than the correction selection potential is applied to the row electrodes to correct the decrease in the drive effective voltage and reduce display unevenness.

According to the present invention, display unevenness that occurs on the screen due to a horizontal pattern such as horizontal stripes is reduced, and a clearer display than in the past is achieved.

[Brief description of drawings]

FIG. 1 is a drive signal diagram of a liquid crystal of an image display device of the present invention.

FIG. 2 is a power supply circuit diagram that creates a liquid crystal drive potential of the image display device of the present invention.

3A and 3B are circuit configuration diagrams used in the operational amplifier of the liquid crystal drive potential power supply circuit in FIG. 2, where FIG. 3A is a circuit configuration diagram of a voltage follower and FIG. 3B is a circuit configuration diagram of an inverting amplifier.

FIG. 4 is a control circuit diagram for correcting a selection potential of a row electrode of the image display device of the present invention.

5 is a circuit diagram of a D-type flip-flop used in the control circuit of FIG.

6 is a circuit diagram of a divider used in the control circuit of FIG.

7 is a circuit diagram of an up / down counter used in the control circuit of FIG.

FIG. 8 is a signal waveform diagram showing an operation of the control circuit of FIG.

FIG. 9 is a row side drive circuit diagram used in the image display device of the present invention.

FIG. 10 is a circuit diagram of a portion used in the driving circuit of FIG.
(A) is a circuit diagram of AND, (b) is a circuit diagram of NAND.

11 is a signal waveform diagram showing the operation of the row side drive circuit of FIG.

FIG. 12 is a configuration diagram of an image display device of the present invention.

FIG. 13 is a power supply circuit diagram of another embodiment for producing a liquid crystal drive potential of the image display device of the present invention.

FIG. 14 is a detection circuit diagram of a potential signal of a row electrode of another embodiment, which is used in a control circuit for correcting a selection potential of a row electrode of the image display device of the present invention.

FIG. 15 is a configuration diagram of pixels of a simple matrix image display device.

FIG. 16 is a screen diagram of a liquid crystal display body for explaining display unevenness.

FIG. 17 is a drive signal diagram of liquid crystal.

FIG. 18 is a drive signal diagram of the liquid crystal for explaining display unevenness, and is a drive signal diagram applied to the liquid crystal at the position of 198 in FIG.

FIG. 19 is a liquid crystal drive signal diagram for explaining display unevenness, and is a drive signal diagram applied to the position 200 in FIG.

[Explanation of symbols]

V ₁ ^A , V ₆ ^A : Correction selection potential V ₁ ^S , V ₆ ^S : Reference potential V ₁ , V ₆ : Non-correction selection potential and lighting potential for V ₃ and V ₄ V ₅ , V ₂ : Non-selection potential V ₄ , V ₃ : Non-lighting potential with respect to lighting potentials V ₆ and V ₁ t: Time until the row electrode signal reaches the reference potential V ₁ ^S or V ₆ ^S from the initial stage in the selection period ft: Time proportional to t

Claims (1)

[Claims] 1. A potential signal for sandwiching a liquid crystal between a substrate on which a plurality of row electrodes are formed and a counter substrate on which a plurality of column electrodes are formed, and selecting or deselecting pixels for each row on the row electrodes. In an image display device in which a lighting / non-lighting image signal is sent to the column electrodes, and the polarity of the drive signal applied to the liquid crystal is inverted in a frame cycle to perform AC drive, the selection potential of the row electrodes is different from the correction selection potential. There is a correction selection potential, and the voltage between the correction selection potential and the non-selection potential is set to be larger, and the selection potential is applied to the selected row electrode so that the signal of the row electrode is at the reference potential from the beginning of the selection period. The image display device is characterized in that the liquid crystal is driven by detecting the time until reaching, and using the corrected selection potential as the selection potential and the non-correction selection potential as the selection potential for a time proportional to the time.