JPH0851426A - Pulse generation rate monitoring circuit - Google Patents

Abstract

PURPOSE:To always calculate a pulse generation rate and to execute monitoring without a detection error in a counter circuit for monitoring whether pulses are generated more than within the time (t) or not. CONSTITUTION:In a pulse generation rate monitoring circuit consisting of a cell receiving circuit 1 for generating a pulse at the time of receiving a valid cell, a memory 2 for storing a timer value at the time of generating a pulse, flags 31, 32 for managing the number of overflows in a timer 5, a control circuit 4 for calculating a pulse generation ratio, the timer 5, and an N-notation counter 6 for counting the number of generated pulses, the timer 5 manages the number of overflows by alternately turning respective flags 31, 32 to '1' at the time of generating a timer overflow and the control circuit 4 calculates and monitors a pulse generation rate by a timer value at the time of generating a pulse, a timer value at the time of generating pulses n times ago which has been stored in the memory 2 and the values of the flags 31, 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for monitoring a pulse generation rate such as receiving a cell from an ATM network and monitoring throughput depending on whether or not n or more valid cells are received per time t. The present invention relates to a counting circuit capable of constantly monitoring the pulse generation rate. For example, the present invention relates to a pulse generation rate monitoring circuit that can be used as a traffic limit normality monitoring and error monitoring circuit in a communication network.

[0002]

2. Description of the Related Art For example, an ATM network cannot handle an input exceeding the processing capacity of the receiving side. Therefore, it is necessary to monitor that there is an input that exceeds the processing capability of the receiving side. The conventional circuit is disclosed in JP-A-56-116.
As described in Japanese Patent No. 331,331, when monitoring whether or not there are n or more pulses within a set time t, sampling is performed every set time t and the number of pulse generations during that time is monitored. It was structured.

[0003]

In the above-mentioned prior art, the pulse generation rate is monitored by sampling at set fixed time intervals. For this reason, there is a problem in that if a number of pulses exceeding the specified value occurs within the time t that extends between samplings, this cannot be detected.

According to the present invention, a circuit for monitoring a pulse generation rate can detect when a number of pulses exceeding a specified value occur within a constant time t set when sampling is performed at regular time intervals. An object of the present invention is to provide a monitoring circuit having a high monitoring capability that can detect even if a number of pulses exceeding a specified value occurs within a time t extending between samplings.

[0005]

In order to achieve the above object, the present invention provides a timer value at the time of observing a pulse and a timer value at the time of occurrence of the nth previous pulse stored in the memory. The lapse of time was calculated in accordance with, and the pulse generation rate was calculated based on this. That is, in the pulse generation rate monitoring circuit that detects that the pulse generation rate exceeds a certain value, a timer that counts the pulse generation time, a memory that stores the timer value at the time when the pulse occurs,
A control circuit for calculating the pulse generation rate based on the timer value and the timer value already stored in the memory is provided for each pulse generation.

However, in this case, if the timer value overflows, the pulse generation rate cannot be calculated accurately. Therefore, the present invention manages the number of overflows of the timer value that occurs after the timer value is stored in the memory by using the management information for managing the number of timer overflows.
Accurately monitor the occurrence rate even if the timer value overflows during observation. That is, in the pulse rate monitoring circuit, by providing management information for managing the number of times of overflow of the timer value in association with the memory for storing the timer value, even if the timer value overflows, the management information is stored in the management information. The pulse generation rate can be calculated.

[0007]

According to the present invention, each time a pulse is input, the timer value at the time when the pulse is generated is compared with the timer value at the time when the pulse n times before stored in the memory is generated to calculate the time. Since the pulse generation rate is constantly calculated, the missed detection during sampling that occurs in the conventional example is eliminated. Also,
Two types of timer overflow management flags are provided corresponding to each address of the timer value storage memory, and the timer overflow timer alternately sets the above two types of flags to "1".
The control circuit stores the timer value at the time of pulse generation in the memory and at the same time sets the two types of flags to "0", so that the number of timer overflows (0, 1, 2, More than once) can be managed. For example, if the flag corresponding to the memory storing the timer value is "0" or "0", it indicates that the timer has not overflowed since the timer value was stored in the memory. If the flag is "0", "1" or "1", "0", it indicates that the timer has overflowed once. When the flags are "1" and "1", it indicates that the timer has overflowed twice or more. Thus, even if the timer overflows after the timer value is stored in the memory, the pulse generation rate can be accurately monitored by referring to the management information when calculating the pulse generation rate.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a pulse generation rate monitoring circuit 1 according to the present invention.
It is a block diagram showing an example, and shows an example of a pulse generation rate monitoring circuit for monitoring the throughput by receiving cells from an ATM network and receiving n or more valid cells per time t.

The pulse generation rate monitoring circuit according to the present invention comprises a cell receiving circuit 1, a memory 2, a first timer overflow frequency monitoring flag 31, a second timer overflow frequency monitoring flag 32, a control circuit 4, It is composed of a T time timer 5, an N-ary counter 6, and an alarm circuit 7.

The cell receiving circuit 1 generates a valid cell pulse when it detects a valid cell among the received cells received from the ATM network, and sends it to the control circuit 4. The received cell is sent to communication processing means (not shown) for processing.

The memory 2 has N (≧ n) storage areas, and functions as a timer value storage memory for sequentially storing the timer values at the time when the effective cell pulse is generated by the control circuit 4 in each storage area. To do.

The two timer overflow count monitoring flags 31, 32 each have N flags corresponding to each address of the timer value storage memory 2, and the T time timer 5
Is overflowed, either the first flag or the second flag is changed in response to the signal,
It manages the number of overflows of the timer 5. The initial values of the flags 31 and 32 are all set to "1".

The control circuit 4 stores the value of the T time timer 5 at the time when the effective cell pulse is generated in the memory 2 and at the same time sets the values of the flags 31 and 32 corresponding to the memory to "0", which is n times before. Pulse generation time timer value, current pulse generation time timer value, and flags 31, 32
The time between both times is calculated from the value of, and the pulse generation rate is calculated from this time and the pulse generation number n, and the pulse generation rate is monitored. Further, the control circuit 4 is provided with a register A that changes its state each time a pulse is received.

The T time timer 5 restarts counting from the initial value after counting T (≧ t) time and overflowing. The N-ary counter 6 counts the number of valid cell pulse occurrences, is reset when counting to N, and restarts counting from the initial value.

The alarm circuit 7 is an alarm circuit for notifying that the pulse generation rate has exceeded the monitored value.

The operation will be described below. Here, the value of the T time timer is indicated by t [p, q], and p indicates the time of the p-th pulse input. When the cell receiving circuit 1 detects a valid cell among the cells received from the ATM network, the cell receiving circuit 1 sends a valid cell pulse to the control circuit 4. When the control circuit 4 receives the first valid cell pulse, the control circuit 4 stores the value t [1,1] of the valid cell pulse reception time of the T time timer 5 in the address (0) of the memory 2 and the address (0).
The corresponding flags 31 and 32 are set to "0", and the N-ary counter 6 is further advanced to "1". Next, when the second valid cell pulse is received, the control circuit 4 stores the value t [2 of the reception time of the T time timer 5 at the address (1) of the memory 2 indicated by the content “1” of the N-ary counter 6. , 1] is stored and flags 31 and 3 corresponding to the address (1) are stored.
2 is set to "0", and the value of the N-ary counter 6 is further advanced to "2". As described above, each time a valid cell pulse is received, the value t _m of the T time timer 5 at the reception time is sequentially stored in the memory 2 and the flags 31 and 32 corresponding to the memory address are set to "0", and the N-ary counter is further set. 6
Step by step.

When the Nth valid cell pulse is received, the control circuit 4 receives the value t of the reception time of the T time timer 5 at the address (n-1) of the memory 2 indicated by the content "n" of the N-ary counter 6. [N, 1] is stored, the flags 31 and 32 corresponding to the memory address (n-1) are set to "0", and the value of the N-ary counter 6 is advanced by 1 to "n".

Next, when the (N + 1) th effective cell pulse is received, the control circuit 4 controls the content "n" of the N-ary counter 6.
Stores the value t [n + 1,1] of the T-time timer 5 at the effective cell pulse reception time in the address (n) of the memory 2 indicated by, and the nth valid cell pulse stored in the address (0) of the memory 2 Value t of the T time timer 5 at the reception time
[1,1] and the current value of the T time timer 5 t [n + 1,
1] and the time t [n + 1,1] between both times.
Calculate t [1,1]. Further, the control circuit 4 causes the calculated time t [n + 1,1] -t [1,
1] is used to generate the pulse generation rate N / t [n + 1, 1] -t
Calculate [1,1]. The control circuit 4 compares this pulse generation rate with, for example, a reference value stored in the control circuit 4 itself, and when it exceeds the reference value, it sends a message to that effect to the alarm circuit 7 to notify the receiving circuit. Have them respond appropriately.

Hereinafter, when the effective cell pulses are sequentially received,
The control circuit 4 calculates the difference between the value of the T time timer 5 at the n-th previous valid cell pulse reception time stored in the memory 2 and the value of the T time timer 5 at the current valid cell pulse reception time. , Calculate the pulse generation rate. When the N-ary counter 6 counts up, its value returns to 0, and the address of the memory 2 is again counted from the address (0).

Here, the process when the time T elapses and the timer 5 times up and overflows while receiving the effective cell pulse and monitoring the pulse generation rate is shown in FIG.
This will be described with reference to the operation flow chart.

It is assumed that the flags 31 and 32 are all set to "1" in the initial state as described above. The register A provided in the control circuit 4 changes the state of the register A to "0" or "1" each time it receives a pulse indicating that the T time timer 5 has overflowed. here,
The initial value of the register A may be indefinite.

Now, assuming that the T time timer 5 overflows (S1), the control circuit 4 which has obtained the overflow information judges whether or not its own register A is "0" (S2). When the register A is "0", all the (0) to (n-1) th flags of the first flag 31 are set to "1" (S3), and when the register A is "1", the flag 32 (0 )-(N-1) th flags are all set to "1" (S4). Next, the inverted contents of the register A are stored in the register A (S5).

Now, from the above state, the T time timer 5 is set to 2
If the overflow occurs for the second time (S1), the control circuit 4 which has obtained the overflow information determines whether or not its own register A is "0" (S2). When the register A is "0", all the (0) to (n-1) th flags of the flag 31 are set to "1" (S3), and when the register A is "1", the flags 32 (0) to (( All the (n-1) th flags are set to "1" (S4). Next, the inverted contents of register A are stored in register A (S
5).

As will be described later, the flags 31 and 32 corresponding to the address of the memory 1 have an initial value of "1" and become "0" when the timer value is written in the memory 1. Therefore, the number of timer overflows that occurs after the timer value is written in the memory 1 is 0 when both the flags 31 and 32 corresponding to the memory 1 are “0”, and the number of the flags 31 and 32 is “1”. If once, flag 3
When both 1 and 32 are "1", it can be shown more than once. Further, when both the flags 31 and 32 are "1", the timer value may be an initial value in which no memory value is stored.

On the other hand, the control circuit 4 when a pulse is generated
The processing of will be described.

As described above, in the memory 2, the timer value at that time is stored in the address indicated by the N-ary counter 6 in the control circuit 4 every time the pulse is generated, and the N-ary counter 6 is generated every time the pulse is generated. Is stepped. Therefore, the value of the N-ary counter 6 when a pulse is generated is x, the number of pulses for calculating the pulse generation rate is n, the time when the T time timer 5 overflows is T, and the count-up value of the N-ary counter 6 is N, if x ≧ n, the timer value when the pulse is generated n times before is the address (x−n) of the memory 2.
It is represented by the content M (x-n) of the address, and when x <n, the content M (x-n +) of the address (x-n + N) of the memory 2
N). Further, the number of timer overflows (0, 1, 2 or more) during the n times is the value F1 (x of the (x−n) th flag of the first flag 31 when x ≧ n.
-N) and the value F2 (x-n) of the (x-n) th flag of the second flag 32, F1 (x-n) + F2 (x
-N). When x <n, the (x−n + N) th value F1 (x−n + N) of the first flag 31 and the second
Value F1 of the (x−n + N) th flag of the flag 32 of
From (x−n + N), F1 (x−n + N) + F2 (x−
n + N). If the timer value at the time of generating the pulse n times before is not stored in the memory 2, that is, if the total number of times of generating the pulse is less than n times, the flags F1 (x-n + N) and F2 (x-n + N) are generated. ), Initial values “1” and “1” are, and the overflow count is considered to be 2 or more.

Therefore, when a pulse is generated (S11), the control circuit 4 generates the generation time + T × (F1 when x ≧ n.
When the condition of (x−n) + F2 (x−n)) − M (x−n) <t is x ≧ n, the occurrence time + T × (F1 (x−n)
+ N) + F2 (x−n + N)) − M (x−n + N) <t
If the condition is satisfied (S12), the alarm circuit 7 is notified that the pulse generation rate exceeds the specified value (S13). After this, and when the above conditions are not satisfied, the control circuit 4 stores the timer value at the time of pulse generation in M (x) of the memory 2,
The flag F1 (x) at the address (x-1) of the first flag 31
And the flag F2 at the address (x-1) of the second flag 32
(X) is set to "0" (S14), and finally the internal N-ary counter 6 is incremented to finish (S15).

According to this embodiment, the capacity of the timer 5 can be reduced, and the pulse generation rate can be constantly monitored without having a plurality of timers and control circuits.

Further, in the present embodiment, the management of the number of overflows of the timer value is realized by using two kinds of flags, but it can also be realized by using a counter of 2 bits or more.

Further, in this embodiment, in consideration of the case where the timer 5 overflows, the number of overflows of the timer 5 is managed by the flags 31 and 32. However, when the value T of the timer 5 is sufficiently large, the flags 31 and 32 are used. It can be realized without processing by. For example, a timer value with an accuracy of 1 second is 3
If it has 2 bits, it will not overflow for 136 years.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the first flag 31 and the second flag 32 have flags corresponding to the addresses of the memory 2. Until the T time timer 5 overflows, the first flag 31 and the second flag 32
Are all "0" and "0", respectively. Now
When the T-time timer 5 overflows while the K-th pulse is being received (S21), the control circuit 4 that has obtained the overflow information determines whether or not its register A is "0". A judgment is made (S22). Register A
Is "0", the Kth flag (k) of the flag 31
Is set to "1" (S23), and when the register A is "1", the Kth flag (k) of the flag 32 is set to "1" (S2).
4). Next, the inverted contents of the register A are stored in the register A (S25). Next, it is determined whether or not a new pulse has been input (S26), and when there is no input, the process returns to step (S21) and the overflow of the T time timer 5 is monitored. When a new pulse is input, the overflow monitoring flow ends. Therefore, when the register A is “0”, the first flag 3
In the case of 1, the Kth flag (k) is "1" and the others are all "0", and the second flags 32 are all "0". When the register A is "1", the first flag 31 is in the state of "0", the second flag 32 is the Kth flag (k) is "1", and the others are all "0". Is in a state.

Next, when the T-time timer 5 overflows for the second time when the K-th pulse is in the receiving position (S21), the control circuit 4 which has obtained the overflow information has its register A It is determined whether it is "0" (S22). First when register A is "0"
The Kth flag (k) of the flag 31 is set to "1" (S
3), when the register A is "1", K of the second flag 32
The th flag (k) is set to "1" (S4). Next, the inverted contents of the register A are stored in the register A (S5). Therefore, when the register A is "0", the previous state of the register A was "1", so the Kth flag (k) of the second flag 32 has already changed to the state of "1". , The Kth flag (k) of the first flag 31 is changed to “1” this time. At this time, the first flag 31, the second flag 32 and other flags are all “0”. When the content of the register A is "1", the state of the previous register A was "0", so the first flag 3
The Kth flag (k) of 1 has already changed to the state of “1”, and the Kth flag (k) of the second flag 32 this time.
Changes to "1". At this time, the first flag 31, the second flag 32 and other flags are all “0”.

Therefore, according to the present invention, when the T time timer 5 overflows once while waiting for the Kth pulse, the Kth flag (k) of the first flag 31 or the Kth flag of the second flag 32. Any of the flags (k) of "1" becomes "1" to indicate the state of one overflow, and when the T time timer 6 further overflows for the second time while waiting for the Kth pulse, the first flag 31 Both the Kth flag (k) and the Kth flag (k) of the second flag 32 become "1" and overflow 2
Can show the status of times.

Similarly, when the T time timer 5 overflows while waiting for the (K + 1) th pulse, the K + 1th flag (k +) of the first flag 31 or the second flag 32.
When any one of 1) becomes "1" to indicate the state of one overflow, and the T-time timer 5 further overflows for the second time while waiting for the (K + 1) th pulse, the first flag 31 and the second flag 31 Any of the Kth flag (k + 1) of the flags 32 can be set to "1" to indicate the state of two overflows.

Next, the processing of the control circuit 4 when a pulse is generated will be described.

As described above, in the memory 2, the timer value at that time is stored in the address indicated by the N-ary counter 6 in the control circuit 4 for each pulse generation, and the N-ary counter 6 is generated for each pulse generation. Is stepped. Therefore, the value of the N-ary counter 6 when a pulse is generated is x, the number of pulses for calculating the pulse generation rate is n, the time when the T time timer 5 overflows is T, and the count-up value of the N-ary counter 6 is N, if x ≧ n, the timer value when the pulse is generated n times before is the address (x−n) of the memory 2.
It is represented by the content M (x-n) of the address, and when x <n, the content M (x-n +) of the address (x-n + N) of the memory 2
N). In addition, the number of timer overflows from n times before is the first flag 31 when x ≧ n.
Of the (x−n) th to (n) th flags of the second flag 32, and the sum of the values of all (x−n) th to (n) th flags of the second flag 32, ΣF2 Sum Σ
It is represented by F1 + ΣF2. When x <n, the sum ΣF1 of the values of all the flags from the (x−n + N) th to the (n) th of the first flag 31 and the (x−n of the second flag 32
It is represented by the sum ΣF1 + ΣF2 with the sum ΣF2 of the values of all the flags from the + N) th to the (n) th.

Therefore, when a pulse is generated, the control circuit 4 generates the generation time + T × (ΣF1 + ΣF) when x ≧ n.
2) When the condition of -M (x-n) <t is x≥n, the occurrence time + Tx (ΣF1 + ΣF2) -M (x-n + N) <
It is determined whether or not the condition of t is satisfied, and if this condition is satisfied, the alarm circuit 7 is notified that the pulse generation rate exceeds the specified value. After this, and when the above conditions are not satisfied, the control circuit 4 stores the timer value at the time of pulse generation in M (x) of the memory 2, and the flag at the address (x-1) of the first flag 31. F1 (x) and the flag F2 (x) at the address (x-1) of the second flag 32 are set to "0" (S14), and finally the internal N-ary counter 6 is incremented to finish.

In the first and second embodiments, an example of hardware implementation is shown, but firmware implementation is also possible. Further, although the alarm circuit 7 is an alarm circuit for notifying that the pulse generation rate exceeds the monitoring value, it may be an alarm device for notifying that the pulse generation rate does not reach the monitoring value.

[0039]

According to the present invention, since the pulse generation rate can be calculated and monitored at all times, the monitoring performance can be improved.

For example, assuming that the generation of pulses follows an exponential distribution, in the conventional method, the number of pulses exceeding the specified value is generated within a certain period of time between samplings, so that it may be overlooked. But
The present invention eliminates such an oversight.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a counting circuit according to the present invention.

FIG. 2 is an operation flowchart of the timer when the timer overflows in the first embodiment of the present invention.

FIG. 3 is an operation flowchart of a control unit when a pulse is generated in the first embodiment of the present invention.

FIG. 4 is an operation flowchart of the timer when the timer overflows in the second embodiment of the present invention.

[Explanation of Codes] 1 cell reception circuit 2 memory 4 control circuit 5 T time timer 6 N-ary counter 7 alarm circuit 31 first flag 32 second flag

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H04Q 3/00 (72) Inventor Yasuharu Kohi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi, Ltd. Information & Communication Division (72) Inventor Shinichi Esaka 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (2)

[Claims] 1. A pulse generation rate monitoring circuit for detecting that the pulse generation rate exceeds a certain value, a timer for measuring the pulse generation time, and a memory for storing the timer value at the time of the pulse generation. A pulse generation rate monitoring circuit comprising a control circuit that calculates a pulse generation rate based on the timer value and the timer value stored in the memory each time a pulse is generated. 2. Management information for managing the number of times the timer value overflows is provided in association with a memory for storing the timer value, and even when the timer value overflows,
The pulse generation rate monitoring circuit according to claim 1, wherein the pulse generation rate can be calculated based on the management information.