JPH0851257A - Board of mounting microminiatured electronic para and its manufacturing method - Google Patents

Abstract

PURPOSE:To connect with very high density by a method wherein an opening is formed in a support base and a bottom region of a thin film structure formed in the support base is exposed and next a z-axis connector is directly connected with both surfaces of the thin film structure. CONSTITUTION:One end of a z-axis connector 80 is connected with an upper surface of a multichip module substrate 50, and another end is connected with an exposed lower surface of a thin film structure 30. An opening is formed in a support base 40 to expose a lower surface of the thin film structure 30. Thus, the thin film structure 30 blocks an opening 90. Lower and upper junction pads are formed in the thin film structure 30 in order to connect with the z-axis connector 80. The opening 90 is formed in the support base 40 and blocked by the thin film structure 30, whereby the z-axis connector can be directly fitted on both surfaces of the thin film structure. Thus, as density in a connection capable of manufacturing becomes remarkably high, the number of interlayer signal channels is remarkably increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of packaging integrated circuit chips, and more particularly to a structure for accommodating a plurality of integrated circuit chips in a three-dimensional array.

[0002]

BACKGROUND OF THE INVENTION This application continues US patent application Ser. No. 07 / 925,962 filed on August 5, 1992 and US patent application Ser. No. 08 / 157,332 filed on November 22, 1993 (invention). Name of "3D multi-chip module (THREE-DIMENSIONAL M
ULTICHIP MODULE))) partly continued application.

IC (integrated circuit) "chips" made up of a large number of electronic components are ubiquitous in modern society. Today, all types of electronic devices and components, from central processing units used at all levels of computing to highly specialized controllers used to control various forms of equipment and machines, It can usually be used as an integrated circuit chip. Since the initial introduction of IC chips, the size of the individual electronic components formed on the chips has decreased dramatically, and the number of devices on a single chip has increased significantly. As device geometries with line widths on the order of 1 micron have become commonplace, individual IC chips now typically contain over one million electronic components. Even higher density devices are planned.

Due to the increasing complexity of the device and the shrinking size of the device, for most types of IC chips, the complexity of forming the interconnection between the chip and the external device is greatly increased. The above factors are due to the third related phenomenon, namely, the increase in the speed at which many digital devices function, as well as the number of chips to the point that active cooling is required to prevent thermal damage. Increases the heat generated per unit volume.

Most devices, such as computers, utilize a large number of discrete IC chips. For example, a computer has at least one CPU (Central Processing Unit) chip, various memory chips, a controller chip,
It has an I / O (input / output) device chip and the like. Typically, each chip is in a separate package connected to a printed circuit board, such as a computer "motherboard" that supplies power to the chips and signals between the chips on the board and to various I / O devices. It is implemented. However, if the electronic device utilizes a substantial number of chips, then packaging each chip separately significantly increases the total area of the printed circuit board required to interconnect all the chips. Moreover, as device speeds increase, the distance between individual components gradually becomes an important factor, so in many applications it is possible to minimize the signal path between the IC chips used in the system. is important.

In order to solve the above-mentioned problems, many device manufacturers use "multi-chip module"("MCM").
Sometimes abbreviated), that is, they are beginning to use packages that contain a large number of individual IC chips. A typical multi-chip module incorporates not only means for interconnecting IC chips with external devices, but also means for interconnecting IC chips within the module. A general introduction to multichip modules, including their development history,
Van Nostrand Rein
hold) "Multi-chip module technology and other technologies, basic edition" published by DA Doane, etc. (1993)
(Multichip Module Technologies and Alternatives, T
he Basics) ”. Multi-chip modules significantly reduce the overall space required to house IC chips and promote high speed device operation by reducing the distance between chips within the module.

The original multichip module was two-dimensional, that is, all the IC chips contained in the package were mounted on a planar substrate. Next, a three-dimensional multi-chip module was developed, which made it possible to further increase the density of IC chips contained in one package. However, I accommodated in a relatively small area
Increasing the number of C chips complicates the method of actively cooling the chips while increasing the overall heat generated by the chip array per unit volume. Similarly, the close proximity of many high density chips complicates the ability to provide power and signals between the chips.

[0008] A number of issues related to the three-dimensional multi-chip module have been reported by Teuksberg of SPIE Volume 1390 (1990) published by The International Conference on Optical Engineering.
(SK Tewksbury) et al., "The Second Volume of the International Symposium on Advanced Interconnections and Packaging, Microelectronic Interconnects and Packaging:
System and Processing Integration "
resco), "System interconnect issues for sub-nanometers.
osecond signal transmission) ”.
In terms of complication factors associated with three-dimensional arrays, two-dimensional multi-chip arrays are still the most common form of multi-chip module currently in use.

Two main board methods have been developed to handle power and signal supply in multi-chip modules.
Initially, the "co-fired" ceramic substrate method was utilized, but is gradually moving to the "thin film" substrate method. In either case, the IC chip is connected to at least one substrate that has all the signal and power lines needed to supply power, connect the chips together, and interconnect the chips with external devices. . To create the required number of interconnects, the substrate may be multi-layered and include dozens of separate layers. For example, even early ceramic substrate technology utilized a large number of discrete layers, up to 35 layers, on a multichip substrate. However, problems occur when arranging the signal lines with respect to each other and near the power supply lines. The dielectric constant of the substrate material is
It plays an important role in solving (or inducing) such a problem. As a result, the popularity of ceramic technology has diminished because of the high dielectric constant associated with ceramic materials typically selected for substrate materials. Instead of ceramic materials,
Low dielectric constant thin film substrates made from materials such as copper and polyimide have become more prevalent.

Since a multi-chip module substrate having a thin film structure such as a multi-layer polyimide structure originally has no rigidity, it has to be stacked on a rigid support base. Various materials are used for rigid support bases including ceramic, silicon, and various metals. An important factor in choosing a support base is compatibility with other materials and processes used in multichip modules and ease of processing. Factors of material compatibility include those that have a CTE (coefficient of thermal expansion) similar to the IC chip mounted on the thin film structure and the substrate, and that can withstand the process steps associated with manufacturing the thin film structure. include. Such treatments can subject the supporting base material to excessive temperatures and harsh chemistries.

The support base used to support the thin film structure may perform no other function than as a base for the thin film structure. Alternatively, the support base may be used to supply power and ground lines to the thin film / ceramic combination multichip module substrate.

[0012]

In a typical three-dimensional multi-chip module, a plurality of coplanar IC chip substrates are stacked to increase the package density of the chips. In the above module, signal, power and ground lines need to be provided not only in the plane of the board, but from one board to the next. When the plane in which the substrate exists is an xy plane, a signal needs to be supplied also in the z direction in order to communicate with an IC chip mounted on a layer of a different level. In known 3D multi-chip modules, the path of the z-axis signal path lies at the edge of the substrate. The edge-side supply path in the z-axis direction has the drawback of lengthening the signal path between chips mounted on different substrates.

A problem with the typical method of packaging IC chips in a multi-chip array is the method of delivering power to the chips. As mentioned above, one aspect of this problem arises from running power lines through the same substrate used to transfer signals between chips. Equally important, the power supply to the IC chip has a fairly high impedance due to the thinness of the substrates used in typical thin film multichip modules. High impedance induces unwanted noise, power loss, and the generation of excessive thermal energy.

In view of the above-mentioned conventional problems, it is an object of the present invention to improve the signal and power supply line supply paths to an integrated circuit chip in a three-dimensional multi-chip module.
It is a particular object of the present invention to provide a substrate and a method of manufacturing the same that provides a high density z-axis signal supply path that does not require the signal to pass through the edge of the substrate to connect to an IC chip on another substrate. Is to provide.

Another object of the present invention is to provide an improved low impedance means for delivering power to the chips of a multichip module. Another object of the invention is to provide a three-dimensional multi-chip module structure that is highly modular so that individual parts can be tested before final assembly of the module, with at least some parts being replaceable. That is.

[0016]

The above and other objects apparent to those skilled in the art upon reading this specification in conjunction with the accompanying drawings and claims will be realized by the multi-chip module substrate of the present invention. The multi-chip module substrate of the present invention, which is a substrate on which microelectronic components such as integrated circuit chips are mounted, has a substantially planar rigid support base having an opening formed in a wide surface thereof, and a rigid support base formed in the opening. A thin film structure formed on the support base to expose upper and lower surfaces of the balance, the lower surface of the thin film structure having a plurality of connection points formed thereon. A high density connector is placed in the opening and attached to a connection point on the exposed lower surface of the thin film structure.

Preferably, the rigid support base is made of ceramic or silicon and the thin film structure is of patterned copper such as copper and an organic polymer such as polyimide. Paths are formed in the support base to provide direct low impedance power and ground paths to integrated circuit chips or other microelectronic components. High density connectors may be used to provide signals between adjacent substrates in a 3D multi-chip module.

The method of manufacturing a substrate according to the present invention comprises the steps of providing a substantially flat rigid support base, forming a thin film structure on the surface of the support base, and forming a part of the lower surface of the thin film structure. Removing a portion of the support base for exposure. The above method comprises the steps of providing a substantially planar rigid support base, forming an opening in the support base, filling the opening in the support base, and planarizing the surface of the support base. And removing fill material from the opening to expose the lower surface of the thin film structure.

Furthermore, the above method comprises the steps of providing a substantially planar rigid support base, forming an opening in the support base, depositing an adhesive material on the surface of the support base, and Placing a plate on the adhesive material to cover the opening; forming a thin film on the plate; providing a plurality of bond pads on the lower surface of the thin film; Removing a portion of the plate within the opening to expose a surface and the bond pad provided therein.

[0020]

The present invention comprises a highly modular, three-dimensional, multi-chip module used to package a large number of integrated circuit "chips" into a dense array. Recent trends in digital IC technology aim at higher signal speeds, that is, very high frequency operations. Since such devices operate in the microwave frequency range, the physical distance between the components has a significant impact on the performance of the components. Therefore, a new IC chip packaging technology has been developed that accommodates a large number of chips in close proximity. The highest chip density is obtained with a three-dimensional chip array.

In the three-dimensional multi-chip module,
A plurality of separate IC chips are mounted in a planar array on a typically planar substrate, and then the planar substrates are stacked. The planar chip substrate of the present invention is hereinafter referred to as a multi-chip module substrate. For convenience, the x and y directions are used to define the axes on the plane of the multi-chip module substrate, the z direction is used to define the axis orthogonal to the planar substrate, ie, the z axis is the stacking of the substrates. Match the direction.

[0022] In determining the chips optimal placement of the three-dimensional array when the signal speed between the chip and the chip are limiting factors, the number of chip features per unit in the module and (N _F), x And the pitch between chips in the y direction (P _x , P _y ) and the pitch between layers in the z direction (P _x
z ) and the number of functional units required to communicate with other functional units (N _s ) need to be considered. The functional unit is defined as a group of at least one chip that functions as a device, such as a CPU and a controller. Optimal number of chips per board (N _b ) if all signal feed paths appear along the axis of the system
^Can be calculated by the following formula: N _b = [2N _s N _F P _z V _xy / (P _x + P _y ) V _z ] ^2/3 , where V _xy and V _z are
It represents the transmission speed of electromagnetic waves in the xy and z directions and depends on the material used for electrical connection in each direction. The above calculation is based on the assumption that for a given number of chips per module, the distance between all two chips (ie the length of the signal feed path) should be minimized. Generally speaking, it is clear that for V _xy = V _z , each layer should be approximately square and the entire module should be approximately cubic in order to minimize the distance between the chips. is there. For P _x = P _z , the number of chips placed along the x and z axes of the substrate should optimally match. Even with a small number of chips implemented, the above formula gives surprising results. For example, if only four chips are used, it can be seen that under typical conditions the optimum number of chips per board is just one, i.e. it is best to just stack the chips. However, if the number of chips is large, the above formula is used, for example,
It is most significant when it exceeds 0.

Another assumption of the above equation is that the signal supply path in the z-axis direction is direct, that is, the signal traveling from a chip on one substrate is a direct path to a chip on another substrate. Pass through. However, in the known multi-chip module,
The z-axis path is at the edge of the substrate, thus increasing the length of the signal path. According to the invention, there is a "communication bar", also called a "z-axis connector", mounted on the surface of the chip substrate, which is remote from the edge of the substrate, i. To do. When the z-axis connector is provided on the board, the signal must be fed through the board in the z-direction. However, it is difficult to form high density signal paths in a fairly thick rigid support base, thus limiting the number of connections when the z-axis connector is mounted on the support base. Therefore, according to the invention, an opening is formed in the support base, which
Exposing the bottom region of the thin film structure formed on the support base.
The z-axis connector is then directly connected to both sides of the thin film structure, which results in a very dense connection.

[0024]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Referring to FIG. 1, there is shown a cross-sectional view of a multichip module 10 according to one embodiment of the present invention. For purposes of illustration, only two layers are shown, each having four rows of substantially identical integrated circuit chips.
One of ordinary skill in the art will recognize that additional layers and IC chips may be added in accordance with the present invention, and the IC chips need not be identical.

In FIG. 1, a plurality of IC chips 20 are directly flip-chip mounted on the surface of the thin film structure 30 formed on the surface of the support base 40. Thin film structure 30
Hereinafter, the combination of the support base 40 and the support base 40 is referred to as a multi-chip module substrate 50. The flip-chip connection may be a solder bump well known in the art or described in U.S. patent application Ser. No. 07 / 977,571, filed Nov. 17, 1992, the disclosure of which is hereby incorporated by reference. It may also be wire interconnects. Flip-chip mounting is preferred because it can achieve very high density interconnects, but the invention is not limited to flip-chip mounting. Similarly, although the illustrated IC chip 20 is directly mounted on the thin film structure 30, the IC chip is mounted on the interposer substrate, and then the interposer substrate is mounted on the multichip module substrate 50. A substrate may be used. The interposer substrate may be used to provide a bypass capacitor in the immediate vicinity of the IC chip.

In one preferred embodiment of the invention, thin film structure 30 comprises a plurality of interleaved layers of polyimide and patterned copper. Methods for producing the preferred form of thin film structure are well known to those skilled in the art and need not be described in detail. The patterned copper layer is used to provide signal feed paths within the multichip module. The signal lines lie substantially along the x and y axes of the system,
It can be made to have a controlled impedance. In addition, the patterned copper layer may be used to form a bypass capacitor in the thin film structure 30 and provide power redistribution within the thin film structure.

However, preferably, the main power distribution of the present invention is provided by a power bar 60 attached to the lower surface of the rigid support base 40 (ie, the surface of the support base opposite the surface on which the thin film structure 30 is formed). Provided. As shown in FIG. 1, the power bar 60 is preferably mounted directly below the row of IC chips 20 so that the distance between the power bar 60 and the overlying IC chip 20 is minimized. The power is relatively thick, and thus the path 70 formed from the low impedance power bar 60 through the support base 40.
(See FIGS. 2 and 3) and then fed to the IC chip 20 through a path (not shown) formed in the thin film structure 30. The diameter of the path of the support base 40 is relatively large so that a low impedance power supply path having a short length can be obtained. As mentioned above, the thin film structure 30 may optionally have a power redistribution layer if the pads on the IC chip are not directly over the power bar at the proper potential. A power bar suitable for use in the present invention and a method of making such a power bar is described in US patent application Ser. No. 07/093, filed Aug. 5, 1992, the disclosure of which is incorporated herein by reference. / 925,962.

In the preferred embodiment described above, the power bar 60 comprises a number of bands, each carrying a different potential.
In the example shown in FIG. 1, the power supply bar 60 includes three power supply bands 61, 62 and 63. Two of the power strips are
Used for separate power supply voltages, the third band is held at ground reference potential. Of course, the number of power strips will vary according to the requirements of the IC chip or other components mounted on the board.

The support base of the present invention can be any suitable material such as silicon, ceramic, glass, or other rigid dielectric. Conductive, for example metal, plates may be used. If metal plates are used, the plates must have the ability to hold rigid geometric specifications at the high processing temperatures associated with thin film structure fabrication and thin film module operation. For example, the polyimide layer is substantially cured at a temperature of at least 400 ° C. Moreover, the metal must be able to tolerate the chemistries used in the fabrication of thin film structures. Finally, a power bar and structure for electrically insulating the metal plate from the thin film structure and the paths used to supply the electrical potential to the IC chip are added. Ceramics and silicon are preferred substrate materials due to the highly developed technologies associated with electronic applications. As described in detail below, the processing steps that make up the multi-chip module substrate of the present invention may vary depending on the material selected as the support base.

A plurality of z-axis connectors 80 are used to connect adjacent multichip module substrates 50. In a preferred embodiment, the z-axis connector is
It has a plurality of signal lines used for coupling IC chips on different substrates. As shown in FIG. 1, an exemplary z-axis connector 80 has a multi-chip module board 5 at one end.
0 upper surface (ie, the upper surface of thin film structure 30) and the opposite end to the exposed lower surface of thin film structure 30. Although the connector is not shown in FIG. 1,
The connection between the z-axis connector 80 and the thin film structure 30 can be made using any suitable means such as solder bumps, wire interconnections, or the like.

The lower surface of the thin film structure 30 has a support base 4
It is exposed by forming an opening at 0 (see Figure 2). Thus, the thin film structure 30 closes the opening 90.
Lower and upper bond pads 310, 320 (see FIG. 3) are formed in the thin film structure 30 for connecting to the z-axis connector 80. By forming the opening 90 in the support base 40 and closing the opening with the thin film structure 30, it is possible to directly attach the z-axis connector to both sides of the thin film structure. This significantly increases the density of connection points that can be manufactured and thus significantly increases the number of signal path channels between layers. For example, the above-mentioned US patent application Ser. No. 07 / 977,571.
When using the wire interconnections described in
Since the minimum wire diameter is 12 μm, the interconnection pitch is as short as 25 μm. On the other hand, the maximum interconnect density obtained when the connections are formed on a ceramic support base is approximately 200 μm.

It can be seen from FIG. 1 that the stacked layers of the present invention form closed cooling channels between adjacent layers. Fluid may be flowed through such cooling channels to remove the heat generated by the multichip module. Heat generation and removal is a major concern in high performance 3D multi-chip module applications. If cooling channels are required, a z-axis connector (or passive dummy spacer) forms the top surface of the top multi-chip module board and the channels for the top mounted IC chips. Attached to a passive plate attached to the top surface. Similarly, it is possible to attach an active or passive substrate to the bottom z-axis connector to close the cooling channel. Finally,
Edge-side connectors, not shown, are attached to link the multichip module to external devices. Alternatively,
The bottom z-axis connector 80 may be used for this purpose.

The multichip module substrate of the present invention is
It can be manufactured in a variety of ways, the choice of which depends in part on the material of the support base. In the method of manufacturing a multi-chip module substrate of the present invention, the support base is first provided and the path 70 is provided.
Are formed on the support base. The thin film structure is then made on top of the support base using known methods. In a preferred embodiment, the thin film structure 30 is polyimide, B
It consists of alternating layers of layers of CB (benzocyclobutene) or other suitable organic polymer and layers of copper, aluminum or other suitable metal. The copper layer may have a thin film of another material such as chromium to enhance adhesion to the polyimide layer. The thin film structure is made to include a lower bond pad that mounts the z-axis connector. The bond pad 320 shown in FIG. 3 for purposes of illustration projects downward from the surface of the thin film structure 30. However, it will be appreciated by those skilled in the art that the bond pad 320 is flush with the lower surface of the thin film structure 30 in accordance with the preferred fabrication method of the present invention. Similarly, the bond pad 310 is
Formed on the upper surface of thin film structure 30 for attachment to a z-axis connector. Similarly, the bond pad 330 is
Formed for mounting the chip to the multi-chip module substrate 50.

As mentioned above, the thin film structure 30 includes means such as a path for coupling power from the path 70 to the bond pad 330 and may further include a bypass capacitor, a power redistribution layer, and a signal supply path. . For illustration purposes,
A small number of bond pads 310, 320 and 330 and path 7
Only 0 is shown. It will be appreciated by those skilled in the art that in actual embodiments, a larger number of each of the above elements will be present.

After the thin film structure 30 including the bond pads 310, 320 and 330 is manufactured, a portion of the support base is removed, thereby forming a plurality of openings in the support base and exposing the bond pad 320. Note that the thin film structure 30 blocks the openings in the support base. The method of removing a portion of the support base depends in part on the type of material selected. Etching, sandblasting, or turning processes are suitable for many types of materials such as silicon and ceramics. Photoimageable ceramics may be used to facilitate the etching process.

However, some ceramics are difficult to remove without the risk of damaging the thin film structure. Another method of forming the multi-chip module substrate of the present invention comprises removing a portion of the support base to form an opening for the z-axis connector before making the thin film structure. The above method requires a subsequent step of covering or filling the openings in order to enable the later formation of the thin film structure. An advantage of the above method is that the material needed to cover the openings can be removed more easily after the thin film structure is made than some ceramics that may be used for the support base.

Another method, as shown in FIG.
0 and the passage holes 70 start from the support base 40 formed therein. In one embodiment, high temperature polyimide, or
A tacky material such as low melting or softening point glass is deposited on top of the support base. A fairly thin plate is then glued to the surface of the tacky material. The thickness of the adhesive material and the plate can be controlled according to the requirements of mechanical support and path manufacturing. Plates made of ceramic, silicon, or PWB (Printed Wiring Board) materials typically have a thickness of 400 μm to 1200 μm. The adhesive layer is typically 25 μm to 100
It has a thickness of μm. The via holes are then extended through the adhesive material and the plate to form vias in the via holes. Alternatively, a support base 40 without via holes is first formed, and in the first stage all three layers (ie support base and
A passage hole is formed through the adhesive material and the plate.
Via holes are formed in the layer using conventional means such as laser melting or reactive ion etching. A thin film structure is then made on top of the plate with vias 70 and bond pads for connecting to the z-axis connector. Finally,
The portion of the plate overlying the opening 90 is etched away to expose the bond pads for the subsequently attached z-axis connector.

In another manufacturing method of the present invention, the support base 40 having the opening 90 formed therein is made of KAPTON.
(“KAPTON” is a registered trademark of EI DuPont de Nemours, Inc. of Wilmington, Del.), A dry film of a material such as polyamide, which is widespread in the electronics industry. . The membrane can be attached to the support base using thermal lamination or the tack described above. The openings in the support base are filled with an easily etchable material such as polyimide, glass or metal. A thin film structure is then created over the KAPTON layer, including bond pads on both sides, as described above. Finally, the fill material is etched away and a portion of the KAPTON or other film that spans the opening is exposed to expose the underside of the thin film structure that includes the bond pads for connecting the z-axis connector.

Another method of manufacture of the present invention, like the method described above, comprises the step of starting with a support base having an opening formed therein for the z-axis connector. A plate of suitable material, such as graphite, is placed on the support base and the openings are filled with an easily removable material such as glass or metal. Preferably, the filling material is flushed to ensure that the openings are completely filled. After cooling the filled support base, the graphite plate was removed,
The upper surface of the support base is polished to create a smooth surface and possibly remove any filler material that may flow into the gap between the plate and the support base. z
A thin film structure including an axial connector bond pad is formed on the smoothed surface of the support base. Finally, the fill material is removed, such as by etching or melting, exposing the bond pads for the z-axis connector. Of course, if a metal fill material is used, it needs to be a different metal than the metal used for the bond pad to allow selective etching. In such another variant of the manufacturing method of the invention, metal is deposited on the walls of the opening and a filling material, such as glass, is applied to the remaining part of the opening.
This allows the metal to be easily etched to remove the filling material as a plug.

[0040]

According to the multi-chip module substrate of the present invention, a high density interconnection can be obtained between the substrates laminated on the three-dimensional multi-chip module. The thick support base not only supports thin film structures that are too thin to maintain rigidity, but also uses a relatively large diameter path directly under the IC chip to provide a low resistance power supply. And an electrical path for the ground wire. The thin film structure provides high density signal lines and interconnects with controlled impedance not available when using thick film (eg, ceramic) technology. The ability to connect to the top and bottom surfaces of the thin film structure allows the bond pads defined in the thin film structure to be small, so that the vertical direction (z-
The interconnect density of the (axis) is significantly increased.

Although the present invention has been described with reference to its preferred embodiments, it will be apparent to those skilled in the art that there are numerous equivalents and substitutions for the structures as described herein. For example, although the present invention has been described with respect to a three-dimensional multi-chip module, the present invention may be applied to a two-dimensional multi-chip module or other applications where microelectronic components are mounted on both sides of a high density thin film structure. Applicability is readily appreciated by those skilled in the art. Therefore, the present invention is not limited to the above detailed description of the invention, and is intended to be understood only based on the matters described in the claims.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a multi-chip module of the present invention including two multi-chip module substrates.

FIG. 2 is a perspective view of a rigid support base used in the present invention during an intermediate stage of manufacture.

FIG. 3 is a cross-sectional view of a multichip module according to the present invention.

[Explanation of symbols]

 10 multi-chip module 20 IC chip 30 thin film structure 40 support base 50 multi-chip module 60 power bar 61, 62, 63 power band 70 path hole 80 z-axis connector 90 opening 310, 320 bond pad

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor David Kuzuma USA California 95131 San Jose Martin Ju Street 1700 (72) Inventor Michael Geelie USA California 95118 San Jose De Chine Drive 4421 (72) Inventor Murase Shigeo USA California 95132 Santa Jose Laurent Way 3512 (72) Inventor Michael G. Peters USA California 95051 Santa Clara Giannini Drive 485 (72) Inventor James Jay Roman USA California 94022 Los Altos San Miguel Avenue 1128 (72) Inventor Som S Swami Ameri United States California 94506 Danville baton Wood DRIVE 508 (72) inventor Wen - Chow Vincent Wan United States California 95014 Cupertino Ed Bloomington-DRIVE 18457

Claims (31)

[Claims] 1. An upper and lower main surface, a substantially planar rigid support base having an opening between the upper and lower surfaces, and a portion of the rigid support base that closes the opening and closes the opening. A microelectronic component comprising a thin film structure deposited on one of the major surfaces of the rigid support base such that the lower surface is exposed and a plurality of connection points on the exposed lower surface of the thin film structure. Board to mount. 2. The board according to claim 1, further comprising a high-density connector mounted in the opening and connected to the connection point. 3. The substrate according to claim 1, wherein the rigid support base is made of silicon. 4. The substrate according to claim 1, wherein the rigid support base is made of ceramic. 5. The substrate of claim 1, wherein the thin film structure comprises a plurality of patterned metal layers sandwiched by a plurality of organic polymer layers. 6. The substrate according to claim 5, wherein the metal layer is made of copper and the organic polymer layer is made of polyimide. 7. The substrate of claim 2, further comprising a plurality of connection points on the upper surface of the thin film structure for connecting to a plurality of integrated circuit chips. 8. The substrate of claim 1, wherein the support base has a plurality of substantially identical openings and a portion of the thin film structure occludes each of the openings. 9. The substrate of claim 1, further comprising a plurality of paths extending between the upper and lower surfaces of the support base. 10. A rigid support base having a plurality of paths and an opening therein, and a support base having an upper surface and a lower surface for closing the opening to expose the lower surface within the opening. An integrated circuit chip substrate comprising a thin film structure deposited on a surface of the thin film structure, a connector mounted on the exposed lower surface of the thin film structure in the opening, and a connector mounted on the upper surface of the thin film structure. A multi-chip module including a plurality of integrated circuit chips. 11. The multi-chip module according to claim 10, wherein the rigid support base is made of ceramic or silicon. 12. The multi-chip module of claim 10, comprising a plurality of said integrated circuit chip substrates stacked to form a three-dimensional multi-chip module. 13. The multi-chip module according to claim 12, wherein the connector joins adjacent substrates in the three-dimensional multi-chip module. 14. The multi-chip module of claim 12, wherein each of the integrated circuit chip substrates has a plurality of openings formed therein. 15. The multi-chip module of claim 12, wherein the support base of each substrate has a plurality of paths extending between and formed in the faces of the support base. 16. A step of providing a substantially planar rigid support base, the step of forming a thin film structure on the surface of the rigid support base having exposed upper and lower surfaces overlapping the surface of the rigid support base. Leaving the thin film structure intact to expose the area of the underside of the structure and removing a portion of the support base to form an opening in the support base. Production method. 17. The method of claim 16, further comprising forming a path between the faces of the rigid support base. 18. The method of claim 16, further comprising forming bond pads on both sides of the thin film structure. 19. The method of claim 16, further comprising mounting a connector in the opening on any of the bond pads. 20. The method of claim 16, wherein a plurality of openings are formed in the rigid support base. 21. Providing a substantially planar rigid support base; forming at least one opening in the rigid support base; filling each of the openings in the support base; Planarizing a surface, forming a thin film structure on the planarized surface of the support base, and removing fill material from the opening to reopen the opening to expose the lower surface of the thin film structure. And a method for manufacturing a substrate for a microminiature electronic component. 22. The method of claim 21, wherein the rigid support base comprises silicon or ceramic. 23. The opening is filled with metal.
The method described in 1. 24. The method of claim 21, wherein the opening is filled with glass or polyimide. 25. The opening is partially filled with metal,
22. The method of claim 21, wherein the method is partially filled with another material. 26. The thin film structure comprises a plurality of patterned metal layers sandwiched by a plurality of dielectric layers.
The described method. 27. The method of claim 26, wherein the metal layer comprises copper and the dielectric layer comprises polyimide. 28. The method of claim 26, wherein the thin film structure has bond pads on both sides thereof. 29. The method of claim 21, further comprising forming a path between the faces of the rigid support base. 30. The step of filling the opening in the rigid support base comprises covering the rigid support base with a plate, flowing a fluid through the opening, curing the fluid, and removing the plate. 21. The method described in 21. 31. A step of providing a substantially flat rigid support base, a step of mounting a plate on a surface of the support base, a step of forming a plurality of paths in the support base, and a plurality of bonding pads on the plate. Forming a region, forming a multilayer thin film structure on the plate and the bond pad, and removing a portion of the support base and the plate under the bond pad to expose the bond pad. Thereby forming an opening in the supporting base.