JPH0851133A - Semiconductor package evaluating method - Google Patents
Semiconductor package evaluating methodInfo
- Publication number
- JPH0851133A JPH0851133A JP18443094A JP18443094A JPH0851133A JP H0851133 A JPH0851133 A JP H0851133A JP 18443094 A JP18443094 A JP 18443094A JP 18443094 A JP18443094 A JP 18443094A JP H0851133 A JPH0851133 A JP H0851133A
- Authority
- JP
- Japan
- Prior art keywords
- lsi
- viscous fluid
- die pad
- data
- distribution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ダイ・パッドおよびダ
イ・パッド界面およびＬＳＩチップ表面に粘性流体を設
けることで、モールド封止後に存するＬＳＩチップ表面
上の応力分布とＬＳＩ特性項目との相関関係を解析でき
るようにした半導体パッケージ評価方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a viscous fluid on the die pad, the die pad interface, and the LSI chip surface to correlate the stress distribution on the LSI chip surface existing after mold sealing with the LSI characteristic items. The present invention relates to a semiconductor package evaluation method capable of analyzing a relationship.
【０００２】[0002]
【従来の技術】近年、大型チップにおいて、半導体パッ
ケージ評価方法としてモールド封止後の封止樹脂応力を
評価する方法があり、上記樹脂応力を評価する方法に
は、光弾性法によるものがある。2. Description of the Related Art In recent years, as a semiconductor package evaluation method for a large chip, there has been a method of evaluating the encapsulating resin stress after mold encapsulation, and the method of evaluating the resin stress includes a photoelastic method.
【０００３】上記従来例には、『ＶＬＳＩパッケージン
グ技術』（上巻）１９９３年５月第２１１〜２１２頁に
示すような例がある。The above-mentioned conventional example includes an example as shown in "VLSI Packaging Technology" (first volume), May 1993, pp. 211-212.
【０００４】この光弾性法による応力の測定は、モール
ド樹脂内の応力によって発生した複屈折現象を利用して
行っている。The stress measurement by the photoelastic method is carried out by utilizing the birefringence phenomenon generated by the stress in the mold resin.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この半
導体パッケージ評価方法では、透明樹脂を用いなければ
ならず、実製品内の樹脂応力の大きさを求めるには、透
明樹脂による測定結果を着色樹脂での値に換算するため
の係数が別途必要となり、煩雑になることや、ＬＳＩ特
性項目との相関関係を解析することができない等の解決
すべき課題が残されていた。However, in this semiconductor package evaluation method, a transparent resin must be used, and in order to determine the magnitude of resin stress in the actual product, the measurement result of the transparent resin is determined by a colored resin. There is still a problem to be solved such that a coefficient for converting to the value of is required separately, which is complicated and the correlation with the LSI characteristic item cannot be analyzed.
【０００６】本発明は、このような課題を解決するもの
で、簡単に構成できる装置を用いて、モールド樹脂応力
を評価できる半導体パッケージ評価方法を提供すること
を目的とする。An object of the present invention is to solve such a problem, and an object thereof is to provide a semiconductor package evaluation method capable of evaluating a mold resin stress by using an apparatus which can be simply constructed.
【０００７】[0007]
【課題を解決するための手段】この目的を達成するため
に本発明の半導体パッケージ評価方法は、モールド封止
前に、粘性流体生成装置を用いて粘性流体を薄膜状にし
て、ＬＳＩチップ表面と、ダイパッドおよびダイパッド
界面の上に塗布する工程と、粘性流体を塗布した後、封
止樹脂および封止樹脂バルクを用いて、モールド封止
し、ばり取りと外装とトリムおよびフォームとマーク等
の処理を施す工程と、上記処理後、ＬＳＩ評価治具にＬ
ＳＩを設置し、ＬＳＩ特性項目の条件に従い、コントロ
ール・ユニットおよび解析装置を用いて、上記ＬＳＩ評
価治具を制御しながら、ＬＳＩ特性項目のデータを測定
し、測定されたデータを上記解析装置に保持する工程
と、上記ＬＳＩ特性項目のデータを測定後、上記ＬＳＩ
を封止樹脂除去装置に設置し、ＬＳＩチップ表面と、ダ
イパッドおよびダイパッド界面の上部の封止樹脂を除去
する工程と、上記封止樹脂除去後、凹凸分布計測装置に
よってＬＳＩチップ表面とダイパッドおよびダイパッド
界面に塗布した粘性流体の流体化した粘性流体だけを取
り除き、粘性流体の凹凸の分布を計測し、上記凹凸分布
計測装置によって計測した粘性流体の凹凸分布データを
制御用ケーブルを通して、解析装置に伝送し、上記解析
装置によって凹凸分布データを応力分布に換算し、上記
凹凸分布データと上記ＬＳＩ特性項目のデータとの相関
解析を行う工程を用いてパッケージ応力を評価する方法
を有している。In order to achieve this object, a semiconductor package evaluation method of the present invention uses a viscous fluid generator to form a thin film of a viscous fluid before molding and to form an LSI chip surface. , Step of applying on die pad and die pad interface, and after applying viscous fluid, mold sealing using demolding resin and encapsulating resin bulk, deburring, exterior and trim, processing of form and mark etc. And the process for applying
The SI is installed, the data of the LSI characteristic item is measured while controlling the LSI evaluation jig by using the control unit and the analyzing device according to the condition of the LSI characteristic item, and the measured data is stored in the analyzing device. After the process of holding and measuring the data of the above LSI characteristic items,
Is installed in an encapsulation resin removing device to remove the encapsulating resin on the LSI chip surface and the die pad and the upper part of the die pad interface. After removing the encapsulating resin, the LSI chip surface, die pad and die pad are measured by the unevenness distribution measuring device. Only the fluidized viscous fluid applied to the interface is removed, the unevenness distribution of the viscous fluid is measured, and the unevenness distribution data of the viscous fluid measured by the above unevenness distribution measuring device is transmitted to the analysis device through the control cable. Then, the package stress is evaluated by using the step of converting the unevenness distribution data into the stress distribution by the analysis device and performing the correlation analysis between the unevenness distribution data and the data of the LSI characteristic item.
【０００８】[0008]
【作用】この発明の構成によれば、モールド封止前にダ
イ・パッドおよびダイ・パッド界面およびＬＳＩチップ
表面に粘性流体を設けることで、モールド封止後に存す
るＬＳＩチップ表面上の応力分布とＬＳＩ特性項目との
相関関係を解析でき、ＬＳＩ特性項目に及ぼす応力の集
中箇所の限定ができ、ひいては、パッケージ構造の最適
化に寄与することができる。According to the structure of the present invention, by providing a viscous fluid to the die pad, the die pad interface and the LSI chip surface before the mold sealing, the stress distribution on the LSI chip surface existing after the mold sealing and the LSI It is possible to analyze the correlation with the characteristic item, limit the concentration of stress exerted on the LSI characteristic item, and thus contribute to the optimization of the package structure.
【０００９】[0009]
【実施例】以下本発明の一実施例について、図１および
図２を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
【００１０】図１は本発明の一実施例である半導体パッ
ケージ評価方法を示すブロック図である。図１におい
て、１はＬＳＩチップ表面、２はダイパッドおよびダイ
パッド界面、３はボンディング・ワイヤー、４はリード
フレーム、５はたとえば、電気粘性流体などの粘性流
体、６は粘性流体５をＬＳＩチップ表面１およびダイパ
ッドおよびダイパッド界面２に塗布する粘性流体生成装
置、７はモールド封止後の封止樹脂および封止樹脂バル
ク、８はＬＳＩ特性項目のデータを測定するためのＬＳ
Ｉ評価治具、９はＬＳＩ評価治具８を制御するコントロ
ール・ユニット、１０はモールド封止後にＬＳＩチップ
表面の封止樹脂を除去する封止樹脂除去装置、１１は封
止樹脂除去後にＬＳＩチップ表面上の粘性流体５の凹凸
分布を計測するために設けた凹凸分布計測装置、１２は
粘性流体５の凹凸、１３は凹凸分布計測装置１１をＸ軸
方向およびＹ軸方向に制御するコントロール装置、１４
は凹凸分布を応力分布に換算し、応力分布とＬＳＩ特性
項目のデータとの相関関係を解析するために設けた解析
装置、１５はＧＰ−ＩＢ等の制御用ケーブル、１８は正
電極、１９は負電極、２０は電場発生装置、２１は生成
室である。FIG. 1 is a block diagram showing a semiconductor package evaluation method according to an embodiment of the present invention. In FIG. 1, 1 is an LSI chip surface, 2 is a die pad and a die pad interface, 3 is a bonding wire, 4 is a lead frame, 5 is a viscous fluid such as an electrorheological fluid, and 6 is a viscous fluid 5. And a viscous fluid generator applied to the die pad and the die pad interface 2, 7 is a sealing resin and a sealing resin bulk after mold sealing, 8 is an LS for measuring data of LSI characteristic items
I evaluation jig, 9 is a control unit for controlling the LSI evaluation jig 8, 10 is a sealing resin removing device for removing the sealing resin on the surface of the LSI chip after mold sealing, 11 is the LSI chip after removing the sealing resin The unevenness distribution measuring device provided to measure the unevenness distribution of the viscous fluid 5 on the surface, 12 is the unevenness of the viscous fluid 5, 13 is the control device for controlling the unevenness distribution measuring device 11 in the X-axis direction and the Y-axis direction, 14
Is an analyzer provided for converting the unevenness distribution into a stress distribution and analyzing the correlation between the stress distribution and the data of the LSI characteristic items, 15 is a control cable such as GP-IB, 18 is a positive electrode, and 19 is A negative electrode, 20 is an electric field generator, and 21 is a generation chamber.
【００１１】以上のように構成された本実施例の半導体
パッケージ評価方法について、以下に評価方法を説明す
る。An evaluation method of the semiconductor package evaluation method of this embodiment having the above-described structure will be described below.
【００１２】まず、図１（ａ）に示すように、モールド
封止前に、粘性流体生成装置６を用いて粘性流体５を薄
膜状にして、ＬＳＩチップ表面１と、ダイパッドおよび
ダイパッド界面２の上に塗布する。粘性流体生成装置６
には、粘性流体５が電気粘性流体等の場合には、正電極
１８、負電極１９、電場発生装置２０、生成室２１等を
有しており、また、電極部を除く上記ボンディング・ワ
イヤー３およびリードフレーム４には、粘性流体５が付
着しないようにする必要がある。粘性流体５を塗布した
後、図１（ｂ）に示すように、封止樹脂および封止樹脂
バルク７を用いてモールド封止し、ばり取りと外装とト
リムおよびフォームとマーク等の処理を施す。この処理
後、図１（ｃ）に示すようにＬＳＩ評価治具８にＬＳＩ
を設置し、ＬＳＩ特性項目の条件に従い、コントロール
・ユニット９および解析装置１４を用いて、ＬＳＩ評価
治具８を制御しながら、ＬＳＩ特性項目のデータを測定
し、測定されたデータは解析装置１４に保持される。Ｌ
ＳＩ特性項目のデータを測定した後、図１（ｄ）に示す
ように封止樹脂除去装置１０に設置し、ＬＳＩチップ表
面１と、ダイパッドおよびダイパッド界面２の上部の封
止樹脂を除去する。封止樹脂除去装置１０には、応力の
発生する研摩装置等の物理的除去装置よりも、粘性流体
５に影響のない化学的除去装置を有することが好まし
い。封止樹脂除去後、図１（ｅ）に示すように、たとえ
ば、レーザー干渉計測による凹凸分布計測装置１１によ
ってＬＳＩチップ表面１とダイパッドおよびダイパッド
界面２に塗布した粘性流体５の流体化した粘性流体だけ
を取り除き、粘性流体の凹凸１２の分布を計測する。上
記凹凸分布計測時には、たとえば、Ｘ軸方向およびＹ軸
方向に制御可能なＸ−Ｙステージのようなコントロール
装置１３を用いる。凹凸分布計測装置１１によって計測
した粘性流体の凹凸分布データは、たとえばＧＰ−ＩＢ
ケーブルのような制御用ケーブル１５を通して、解析装
置１４に伝送され、上記解析装置１４によって凹凸分布
データを応力分布に換算され、上記凹凸分布データと上
記ＬＳＩ特性項目のデータとの相関解析が行われ、応力
分布と相関のあるＬＳＩ特性項目の限定や、ＬＳＩ特性
項目と相関のある応力分布の限定が行われ、上記応力の
かかる回路部が特定できる。First, as shown in FIG. 1A, a viscous fluid 5 is formed into a thin film by using a viscous fluid generating device 6 before molding and sealing the LSI chip surface 1 and a die pad / die pad interface 2. Apply on top. Viscous fluid generator 6
When the viscous fluid 5 is an electrorheological fluid or the like, it has a positive electrode 18, a negative electrode 19, an electric field generator 20, a generation chamber 21 and the like. It is necessary to prevent the viscous fluid 5 from adhering to the lead frame 4. After applying the viscous fluid 5, as shown in FIG. 1B, mold sealing is performed using a sealing resin and a sealing resin bulk 7, and deburring, exterior and trim, foam and mark processing are performed. . After this process, as shown in FIG.
Is installed, the data of the LSI characteristic item is measured while controlling the LSI evaluation jig 8 by using the control unit 9 and the analyzing device 14 according to the condition of the LSI characteristic item. Held in. L
After measuring the data of the SI characteristic item, it is installed in the encapsulation resin removing device 10 as shown in FIG. 1D, and the encapsulation resin on the LSI chip surface 1 and on the die pad and the die pad interface 2 is removed. It is preferable that the sealing resin removing device 10 has a chemical removing device that does not affect the viscous fluid 5 rather than a physical removing device such as a polishing device that generates stress. After removing the sealing resin, as shown in FIG. 1E, for example, the viscous fluid 5 of the viscous fluid 5 applied to the LSI chip surface 1 and the die pad and the die pad interface 2 by the unevenness distribution measuring device 11 by laser interference measurement is used. Then, the distribution of the unevenness 12 of the viscous fluid is measured. At the time of measuring the unevenness distribution, for example, a control device 13 such as an XY stage that can be controlled in the X-axis direction and the Y-axis direction is used. The unevenness distribution data of the viscous fluid measured by the unevenness distribution measuring device 11 is, for example, GP-IB.
It is transmitted to the analysis device 14 through a control cable 15 such as a cable, the unevenness distribution data is converted into a stress distribution by the analysis device 14, and a correlation analysis between the unevenness distribution data and the data of the LSI characteristic item is performed. The LSI characteristic item having a correlation with the stress distribution and the stress distribution having a correlation with the LSI characteristic item are limited, and the circuit portion to which the stress is applied can be specified.
【００１３】図２は本発明の半導体パッケージ評価方法
において、粘性流体５の固体化と応力による流体化を示
す理論図である。この理論には、電気粘性流体の場合、
ハルセイ（Ｈａｌｓｅｙ）、マーチン（Ｍａｒｔｉ
ｎ）、アドルフ（Ａｄｏｌｆ）の理論がある。FIG. 2 is a theoretical diagram showing solidification of the viscous fluid 5 and fluidization by stress in the semiconductor package evaluation method of the present invention. In this theory, for electrorheological fluids,
Halsey, Martin
n) and Adolf's theory.
【００１４】以下、図２を用いて、粘性流体の仕組みに
ついて説明する。図２において、１６はたとえば、ガラ
ス球をシリコーンオイルに分散したような電気粘性流
体、１７は電気粘性流体１６の粒子鎖、１８は正電極、
１９は負電極、２０は電場発生装置、２１は電気粘性流
体１６で満たされた生成室、２２はせん断応力である。The mechanism of the viscous fluid will be described below with reference to FIG. In FIG. 2, 16 is an electrorheological fluid such as glass spheres dispersed in silicone oil, 17 is a particle chain of the electrorheological fluid 16, 18 is a positive electrode,
Reference numeral 19 is a negative electrode, 20 is an electric field generator, 21 is a generation chamber filled with the electrorheological fluid 16, and 22 is shear stress.
【００１５】まず、図２（ａ）に示すように生成室２１
内に、電気粘性流体１６と正電極１８および負電極１９
で満たし、電場発生装置２０によって、正電極１８と負
電極１９との間に電場が発生すると、電気粘性流体１６
中に電気粘性流体１６の粒子鎖１７が発生する。粒子鎖
１７は成長し、粒子鎖１７同士で新たに粒子鎖を生成
し、電気粘性流体１６を固体へと導く。次に、図２
（ｂ）に示すように、せん断応力２２を固体化した電気
粘性流体１６が受けた場合、電気粘性流体１６の粒子鎖
１７が破壊され、元の流体化した電気粘性流体１６へと
戻る。したがって、たとえば、洗浄等の方法によって、
せん断応力部分の流体化した電気粘性流体だけを取り除
けば、電気粘性流体の凹凸形状ができる。First, as shown in FIG. 2A, the generation chamber 21
Inside the electrorheological fluid 16, the positive electrode 18 and the negative electrode 19
And an electric field is generated between the positive electrode 18 and the negative electrode 19 by the electric field generator 20, the electrorheological fluid 16
Particle chains 17 of the electrorheological fluid 16 are generated therein. The particle chains 17 grow, new particle chains are generated between the particle chains 17, and the electrorheological fluid 16 is guided to a solid. Next, FIG.
As shown in (b), when the solidified electrorheological fluid 16 receives the shearing stress 22, the particle chains 17 of the electrorheological fluid 16 are broken, and the original fluidized electrorheological fluid 16 is restored. Therefore, for example, by a method such as washing,
By removing only the fluidized electrorheological fluid in the shear stress portion, the uneven shape of the electrorheological fluid is formed.
【００１６】以上のように本実施例によれば、ダイ・パ
ッドおよびダイ・パッド界面およびＬＳＩチップ表面に
粘性流体を設けることで、モールド封止後に存するＬＳ
Ｉチップ表面上の応力分布とＬＳＩ特性項目との相関関
係を解析でき、ＬＳＩ特性項目に及ぼす応力の集中箇所
の限定ができ、ひいては、パッケージ構造の最適化に寄
与することができる。As described above, according to this embodiment, by providing the viscous fluid on the die pad, the die pad interface and the LSI chip surface, the LS existing after the mold sealing is present.
It is possible to analyze the correlation between the stress distribution on the surface of the I-chip and the LSI characteristic item, limit the location of stress concentration on the LSI characteristic item, and thus contribute to the optimization of the package structure.
【００１７】[0017]
【発明の効果】本発明は、モールド封止前にダイ・パッ
ドおよびダイ・パッド界面およびＬＳＩチップ表面に粘
性流体を設けることで、モールド封止後に存するＬＳＩ
チップ表面上の応力分布とＬＳＩ特性項目との相関関係
を解析でき、ＬＳＩ特性項目に及ぼす応力の集中箇所の
限定ができ、ひいては、パッケージ構造の最適化に寄与
することができ、産業上、極めて有用な半導体パッケー
ジ評価方法を得ることができる。According to the present invention, by providing a viscous fluid on the die pad, the die pad interface and the LSI chip surface before the mold sealing, the LSI existing after the mold sealing is present.
It is possible to analyze the correlation between the stress distribution on the chip surface and LSI characteristic items, limit the concentration of stress exerted on LSI characteristic items, and eventually contribute to the optimization of the package structure. A useful semiconductor package evaluation method can be obtained.
【図１】本発明の一実施例の半導体パッケージ評価方法
を実施するための装置のブロック図FIG. 1 is a block diagram of an apparatus for implementing a semiconductor package evaluation method according to an embodiment of the present invention.
【図２】本発明の一実施例の半導体パッケージ評価方法
の理論図FIG. 2 is a theoretical diagram of a semiconductor package evaluation method according to an embodiment of the present invention.
１ ＬＳＩチップ表面 ２ ダイパッドおよびダイパッド界面 ３ ボンディング・ワイヤー ４ リードフレーム ５ 電気粘性流体などの粘性流体 ６ 粘性流体生成装置 ７ 封止樹脂および封止樹脂バルク ８ ＬＳＩ評価治具 ９ コントロール・ユニット １０ 封止樹脂除去装置 １１ 凹凸分布計測装置 １２ 粘性流体の凹凸 １３ コントロール装置 １４ 解析装置 １５ 制御用ケーブル １６ 電気粘性流体 １７ 粒子鎖 １８ 正電極 １９ 負電極 ２０ 電場発生装置 ２１ 生成室 ２２ せん断応力 1 LSI chip surface 2 Die pad and die pad interface 3 Bonding wire 4 Lead frame 5 Viscous fluid such as electrorheological fluid 6 Viscous fluid generator 7 Encapsulating resin and encapsulating resin bulk 8 LSI evaluation jig 9 Control unit 10 Encapsulation Resin removal device 11 Concavo-convex distribution measuring device 12 Concavity-convexity of viscous fluid 13 Control device 14 Analysis device 15 Control cable 16 Electro-rheological fluid 17 Particle chain 18 Positive electrode 19 Negative electrode 20 Electric field generator 21 Generation chamber 22 Shear stress
Claims (1)
用いて粘性流体を薄膜状にして、ＬＳＩチップ表面と、
ダイパッドおよびダイパッド界面の上に塗布する工程
と、前記粘性流体を塗布した後、封止樹脂および封止樹
脂バルクを用いて、モールド封止し、ばり取りと外装と
トリムおよびフォームとマーク等の処理を施す工程と、
上記処理後、ＬＳＩ評価治具にＬＳＩを設置し、ＬＳＩ
特性項目の条件に従い、コントロール・ユニットおよび
解析装置を用いて、前記ＬＳＩ評価治具を制御しなが
ら、ＬＳＩ特性項目のデータを測定し、測定されたデー
タを前記解析装置に保持する工程と、前記ＬＳＩ特性項
目のデータを測定した後、前記ＬＳＩを封止樹脂除去装
置に設置し、前記ＬＳＩチップ表面と、前記ダイパッド
および前記ダイパッド界面の上部の封止樹脂を除去する
工程と、封止樹脂を除去した後、凹凸分布計測装置によ
って前記ＬＳＩチップ表面と前記ダイパッドおよび前記
ダイパッド界面に塗布した前記粘性流体のうちの流体化
した粘性流体だけを取り除き、前記粘性流体の凹凸の分
布を計測し、前記凹凸分布計測装置によって計測した粘
性流体の凹凸分布データを制御用ケーブルを通して、解
析装置に伝送し、前記解析装置によって凹凸分布データ
を応力分布に換算し、凹凸分布データと前記ＬＳＩ特性
項目のデータとの相関解析を行う工程とでパッケージ応
力を評価することを特徴とする半導体パッケージ評価方
法。1. A method for forming a viscous fluid into a thin film by using a viscous fluid generating device before molding with a mold,
Applying on the die pad and the die pad interface, and after applying the viscous fluid, mold-seal using the encapsulating resin and encapsulating resin bulk, deburring, exterior and trim, and processing of forms and marks, etc. And the process of applying
After the above processing, place the LSI on the LSI evaluation jig and
According to the condition of the characteristic item, while controlling the LSI evaluation jig by using the control unit and the analyzing device, measuring the data of the LSI characteristic item, and holding the measured data in the analyzing device, After measuring the data of the LSI characteristic item, the LSI is installed in a sealing resin removing device, and the step of removing the sealing resin on the surface of the LSI chip, the die pad and the interface of the die pad, After the removal, only the fluidized viscous fluid of the viscous fluid applied to the LSI chip surface, the die pad and the die pad interface is removed by the unevenness distribution measuring device, and the unevenness distribution of the viscous fluid is measured, The unevenness distribution data of the viscous fluid measured by the unevenness distribution measuring device is transmitted to the analyzer through the control cable, Converted data of unevenness distribution in the stress distribution by the analysis device, the semiconductor package evaluation method and evaluating a package stress in the step of performing a correlation analysis between the uneven distribution data LSI characteristic item of data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18443094A JPH0851133A (en) | 1994-08-05 | 1994-08-05 | Semiconductor package evaluating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18443094A JPH0851133A (en) | 1994-08-05 | 1994-08-05 | Semiconductor package evaluating method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0851133A true JPH0851133A (en) | 1996-02-20 |
Family
ID=16153020
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18443094A Pending JPH0851133A (en) | 1994-08-05 | 1994-08-05 | Semiconductor package evaluating method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0851133A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455348B1 (en) * | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
-
1994
- 1994-08-05 JP JP18443094A patent/JPH0851133A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6455348B1 (en) * | 1998-03-12 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Lead frame, resin-molded semiconductor device, and method for manufacturing the same |
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