JPH08502844A - How to control the sprite rendering processor - Google Patents

Abstract

(57) [Summary] A linked list of sprite control blocks is prepared in memory (108) and traversed by the sprite rendering engine. Each sprite control block (106) controls the rendering of each sprite in the display buffer and is performed in the pointer pointing to the source data for the corresponding sprite, the position increment specification for the destination quadrilateral, and the sprite image source data. It contains information such as a control word for the operation to be performed, and an indication of which of a number of available formats the sprite image source data will be packed into. Once the linked list is prepared, the Sprite Rendering Engine (106) writes some values to specific memory mapped hardware registers and then writes the dummy data to the address identified by the hardware for the Sprite Rendering operation (106). ) Can be called by writing it as a command to start.

Description

Detailed Description of the Invention             How to control the sprite rendering processor   A portion of the disclosure of this patent document contains material which is subject to copyright protection. Copyright The proprietor of this patent document as it appears in the U.S. Patent and Trademark Office patent file or record. Or, no one disagrees with facsimile reproduction of the patent disclosure, All other copyright rights shall be retained.Cross reference   The present invention relates to the following:   "Audio / Video Co." PC entitled "Computer Architecture (AUDIO / VIDEO COMPUTER ARCHTECTURE)" T patent application No. PCT / US92 / 09349 and same title, same inventor And US patent application Ser. No. 07 / 970,308 filed on the same date;   Inventor Maikal et al. Filed on the same day as the present invention. Video display resolution enhancement (RESOLUTION ENHANCEMENT FOR VIDEO DISP PCT patent application No. PCT / U entitled "LAY USING MULTI-LINE INTERPOLATION)" S92 / 09342 and the same title, same inventor and filed on the same day US Patent Application No. 07 / 970,287;   Inventor David C. F. filed on the same day as the present invention. "Three-dimensional sound by Pratt P. entitled "METHOD FOR GENERATING THREE DIMENSIONAL SOUND" CT patent application No. PCT / US92 / 09348 and same title, same invention And US patent application Ser. No. 07 / 970,274 filed on the same date;   "Sprite Rendering" by the inventor, Mr. Mycal, who applied on the same day as this invention To control the processor (METHOD FOR CONTROLLING A SPRYTE RENDERING PRO PCT Patent Application No. PCT / US92 / 09350 entitled "CESSOR)", and Title, same inventor and US patent application Ser. No. 07/970, filed on the same date, Issue 278:   Inventor Needle et al. Filed on the same day as the present invention, "improved corner meter Sprite Rendering with Arithmetic Engine and Improved Polygon Paint Engine SPRINGE RENDERING SYSTEM WITH IMPROVED CORNER CALCULATING EN PCT patent application No. PCT entitled "ZINE AND IMPROVED POLYGON-PAINT ENZINE)" / US92 / 09462 and same title, same inventor and same date U.S. patent application Ser. No. 07 / 970,289;   Inventor Maikal et al., Filed on the same day as the present invention, said " METHOD AND APPARATUS FOR UPDATING A CLUTD PCT patent application No. PCT / US92 / 0 entitled "URING HORIZONTAL BLANKING)" No. 9460 and US patents filed on the same date with the same title Application No. 07 / 969,994;   Inventor Maikal et al. Filed on the same day as the present invention "process image data IMPROVED METHOD AND APPARATUS FOR PROCE PCT Patent Application No. PCT / US92 / 09461 entitled "SSING IMAGE DATA)" Issue, and US patent application Ser. No. 07 filed on the same title, same inventor and same date / 970,083; and   “Player bus device and PCT patent application No. PCT / entitled "PLAYER BUS APPARATUS AND METHOD" US92 / 09384 and the same title, same inventor and filed on the same date U.S. Patent Application No. 07 / 970,151.   All of these related patent applications are assigned in common with the present invention and are incorporated by reference in their entirety. And will be taken up here.Field of the invention   The present invention relates generally to image data processing, and more particularly to mapping to a destination grid. Shading, highlighting and other in the source image to be rendered Engine to perform functions related to the functions of Related to the technology for controlling.Prior art description   Nowadays, the representation and processing of visible images is essentially analog form and essentially digital. It is transitioning to the tal form. Digital processing of image data presents unique challenges. It Tolerate these problems by providing sufficient storage capacity for digital image data. Maintaining a possible data throughput rate is included. Furthermore, digitally The problem of forming a realistic sensation in the image that is formed, especially in the animated image, is there.   Visualization of images formed by digital video game systems, simulators, etc. Realistic feeling is improved by giving special effects such as shading and highlight processing. Is done. For example, view a statue of a plane flying over a flat area on a sunny day When it should, the overall scene is created by forming a shadow image of the plane within the local image. The sense of reality is enhanced. Instead of making the area of the shadow cast completely black The effect becomes more realistic when made cloudy. The observer Even if the area is shaded by airplanes, we continue to see the essence of its nature. This effect is This is called "shading".   Another example of the effect of giving a sense of reality is highlight processing. Detonator attached to an airplane It is assumed that an explosion will occur in the near future and it will be displayed. The brightness of the plane image is momentarily increased ( (Illite processing), and the impression that the light from the explosion is reflected from the fuselage of the airplane By creating, the visual reality is enhanced. This effect is different for airplanes Between certain parts (eg, cockpit, fuselage, wings) It becomes more realistic when maintained.   Home game systems like Sega's "Genesis" are on the Two-source image fusion to create shadow and highlight effects in lie (real time) Have an integrated system. When a shadow effect is desired, the first source "Thailand" "Or" sprite "(of the bitmap data representing the shadow area of an airplane) A rectangular block) is overlaid with tiles from the second source that represent the area below. Be done. For each pixel position where the first (shadow) sprite intensity is non-zero, the second The digital signal that represents the corresponding area intensity in Ile is cut in half, which It produces a "dimming" effect. Then this dimmed version of the regional tiles It is output as a part. (However, this dimmed image data is stored in the memory. I can't remember. )   To create the highlight effect, Sega's "Genesis" system Divides the shading values of all the pixels in the sprite by 2 and half the maximum shading value Is added to each pixel. It maintains a relative shading relationship between parts of the plane While making each one brighter. The enhanced version of the airplane tile is then It is output as part of the video signal, but not saved. Sega's "Genesis In a “s” system, it is not possible to simultaneously shade and highlight tiles. Can not.   The above shading and highlighting techniques have limited applications. Optically complex A large number are required for various animated scenes. For example, the Knights of the Kingdom Consider a scene in a (Knights of the Realm) type game. Hero of the association Enter the arched room. Different heights, colors, transparency, shapes and angles around the room There is a stained glass. The villain is looking at the stained glass window Approach from outside the room at an angle to the douglas window. This scene is two-dimensional Of the image (hereinafter referred to as an observation plane), or displayed there. Reality The position of the viewing plane (the window where the game player views the scene) to add Is slowly rotated around the hero, and a cubic is applied to the displayed 2D scene. The original quality is given.   For realistic rendering of such a scene, external light should be stained. The change in light must be taken into account when passing through the window of the window to the viewing plane at various angles. I have to. Also, the internal light reflects from the stained glass window toward the observer plane. You must also consider doing. In addition, a bad guy stones one of the stained glass windows When throwing, the visual effect of the hole must replace the removed window material. Absent. If the villain throws mud at the window, the transparency of the affected area of the window And the color must change accordingly.   Previously available home game systems (eg Nintendo Entertainment System, Sega Genesis) is an optically complex animation Scenes cannot be processed in real time. Silicon graphics Some commercially available imaging systems, such as the "iris" system of the It provides a mechanism to handle the clutter in real time, but this is a fast computing This is only possible by using data, large memory and special custom circuits. Therefore, these commercially available systems are only available at very high cost.   Up to now, the low cost of realistic rendering of complex animated scenes System not available.   Digital graphic processing also uses a digital signal representing image data as a single tissue fog. -Based on the physical conversion of matte to another format. Converted Some or all of the captured image data may be displayed on a suitable display means (eg cathode ray tube or LCD display).   Digital image data is often converted from one format to another Is desired to be converted at a relatively high rate. This is the image displayed Creates the sensation of animation and user input in the case of interactive systems Done to form the feeling of real-time response to. Such a fast change The conversion is called real-time digital graphic processing. This real-time digital Talgraphic processing can be used for flight or other simulation systems or interactive It is practically useful for game systems and the like.   One feature often required for real-time digital graphics processing. The function is to map the source image onto the destination surface. Normally, The source image comprises one or more pixels, each of which is filled with a particular color or shadow. It The mapping function is for the pixels from the source area to the destination area. It is a one-to-one copy. Alternatively, the mapping function is a size conversion And / or shape changes (eg skew) and / or some angle of rotation plus color Alternatively, a change in image brightness may be included.   For example, a simulated scene in a real-time army game Think The plane appears to fly towards or away from the observer It should be displayed on the display panel. Observer is a real-time controller At least some of the actions on the display by the cursor (eg joystick) Control a part. When the plane should appear to fly towards the observer The image grows larger as the apparent distance from the observer decreases. It Conversely, if the plane should appear to fly away from the observer, the The image becomes smaller as the distance from the observer increases. Furthermore, the plane If he rolls during its flight, it must rotate its image.   If the detonator ignites near the plane when the plane flies, The display brightness of the main body is momentarily increased, and the light from the explosion reflects from the fuselage of the airplane. But I have to simulate it.   Airplanes have large, foam-like cockpit windows and transparent parts such as holes in some parts of the aircraft. May have a minute and the hole is suddenly formed by the impact of a projectile. It In such cases, when the plane flies in front of the background scene Display background scenes visible through cockpit windows and / or holes in the aircraft Is desirable.   This form of animated real-time scene display in a number of ways Can be formed into a means.   The violent solution is to separate each whole frame of animated scene data separately. Form and form the frame data in high speed memory (eg video RAM) And store each complete frame (background and plane) in a suitable frame. Transfer to display means at boom speed. This violent solution wastes memory space And requires high-speed performance from a processing circuit that generates sequential frames of image data. It   A better solution is based on the concept of sprite painting. One memory area stores unchanged background image data, and a second memory area. The Mori area stores image data for airplanes and other moving objects. Each displayed frame Along with the boom, the image of the airplane is displayed in the background area from the second memory area to the first Mapped to the land image. Mapping function size over time Change over time to give an increase or decrease and rotation of the. Also, mapping Functions to simulate various lighting conditions, such as those caused by nearby explosions. It also gives a change in color and / or brightness in order to adjust.   Ideally, you can take any source image and scale it up or down to any size. It must be possible to map it, including reduction. Also mapped With or without rotation and / or shape distortion (skew) Must be able to project onto the destination grid. In addition, the mapped Pee can also be projected onto the destination grid with or without color changes I have to do it.   High-performance electronic computer system capable of converting image data in this way System such as the Silicon Graphics Iris® system described above. Available. Such a system is a complex software-controlled data conversion And bulk transfer of image data from one memory area to another. Pan The computer unit for the task is tasked with supporting all calculations. Be done. Unfortunately, these computer systems are expensive and circuit support Large size, complexity and / or slow image rendering speed I'm troubled.   The industry offers low cost in one or several integrated circuit (IC) chips Code that can be implemented and can perform complex image transformations at high speed. There is a need for a compact image rendering system.   It also allows multiple software to be called by higher level routines. Logic of such an image rendering system with altines or primitives Control in a fundamentally trivial way to reduce the complexity of detail in the image rendering system. It is also required to be hidden. Also, such a routine is Protection against unintended misuse of the operating system.Summary of the invention   According to the present invention, a sprite control block is described in a roughly linked The list is prepared in memory and traversed by the sprite rendering engine It Each sprite control block renders each sprite to the display buffer. This controls the dulling, and is a pointer to the source data of the corresponding sprite. Interface, destination quadrilateral position and perspective specifications, sprite image source data Control word for the operation to be performed and the number of available formats. Includes information such as which of which sprite image source data will be packed There is. In addition, the sprite control block is a new sprite image source data Modify a portion of the existing display data with either constant data You can also control the sprite rendering engine like this. Linked Once the list has been prepared, it is populated with specific memory mapped hardware registers. Write some values, and to the address seen by the hardware, Write dummy data as a command to start the sprite rendering operation This allows you to call the sprite rendering engine.Brief description of the drawings   The present invention will now be described in detail with respect to specific embodiments with reference to the accompanying drawings.   FIG. 1 is a block diagram showing the main elements of a hardware system in which the present invention is used. It is a diagram.   FIG. 2 is a symbol block diagram of the address manipulator of FIG.   FIG. 3 is a block diagram showing a part of the address generator of FIG.   FIG. 4 is a block diagram of the stack address logic of FIG.   FIG. 5 is a block diagram of the left address pad logic of FIG.Detailed description of the preferred embodiment   The embodiments disclosed herein are described in related patent application “Audio / Video Computer Applications”. -AUDIO / VIDEO COMPUTER ARCHITECTURE "; Related patent application" Image data " IMPROVED METHOD AND APPARATUS FOR PROCE SSING IMAGE DATA) ”; and related patent application“ Improved corner calculation engine and And improved polygon paint engine sprite rendering system (SPRYTE RENDERING SYSTEM WITH IPROVED CORNER CALCULATING ENGINE AND IMPR OVED POLYGON-PAINT ENGINE) " Is intended to work. These applications are also taken up here as reference So the description of the hardware disclosed in such an application will not be repeated here . However, some of the information provided below is useful in understanding the present invention. It I.All hardware architecture   FIG. 1 is a block diagram showing the main elements of a hardware system. This The stem has a CPU 102, which is Swaham Barbe, Cambridge, England. ARM manufactured by Advanced RISI Machines Limited 60 RISC processor. ARM60 is taken up here as a reference "ARM 60 Data Sheet" by Advanced RISC Machines (1992) Year). The address bus 104 is an address manipulator chip It is provided as an input to 106. This address manipulator chip 10 6 is, among other things, the DMA generated address to system memory and from other sources. An address generator for giving an address; a D bus arbiter; two Sprite engine; to player bus, low speed bus and a set of external processors And interface. The address manipulator chip 106 is on the left. System memory 108 including memory bank 108A and right memory bank 108B Generate an address for. This system memory is 32 bits wide, each 3 The upper 16 bits of the 2-bit word are placed in left memory 108A and the lower 16 The bits are placed in right memory 108B. CPU 102 uses system memory Address, but the address manipulator chip 106 is Each half of can be addressed independently. Address manipulator chip 106 is an LA bus 110 and an LCTL bus 112 for address and control signals, respectively. To the left memory 108A, and the address and control signals are respectively supplied to the RA bus. And to the right memory 108B via 114 and the RCTL bus 116.   The system memory 108 includes 1 or 2 "sets" of video RAM (VRAM). It may include 0, 1 or 2 sets of DRAMs. One set of VRAM 1M in total including 512k bytes left memory and 512k bytes right memory It becomes a byte. One set of DRAM is 1, 4 or 16 depending on the system configuration. It will be megabytes long. As with VRAM, half of each set is left memory And the other half are located in the right bank of memory. However, Unlike VRAM, DARM is always accessed in full 32-bit words. Shi The stem memory 108 is considered a big-endian.   All left and right bank system memory sets are address manipulator chips Receive each left and right half address generated by 106. Also, all left banks Data is connected to the left half data bus D (3L: 16) 118 in both directions. It also has a port. Similarly, all sets of data ports in the right bank memory It is bidirectionally connected to the half data bus D (15: 0) 120. Also, the VRAM set It also has a serial port S bidirectionally connected to the S (31: 0) bus 122.   Further, the address manipulator chip 106 receives the CPU 10 via the line 128. 2 for exchanging control signals, and bidirectional with left and right data buses 118 and 120 It is connected. The address manipulator chip 106 is a CPU ROM. 132, battery-backed SRAM and / or various front panel devices Low speed bus 130, which is an 8-bit bus for accessing devices such as Interface to. Also supports additional CPU accessible RAM It can also support FM sound generator devices. Low speed bus 130 is a 14-bit A (16: 2), 8-bit data buffer of the address bus 104. PD PD (7: 0), PDRDB read strobe, PDWRB write strobe And various control lines. PDRDB and PDWRB are 8 bits wide Transport to two lower address lines to access the CPU ROM 132 of Used to do.   The address manipulator chip 106 also interfaces with the player bus 136. -Face, this bus is joystick, 3-D glass, hand control , Steering wheel, and game server cartridges. Used to connect the system to a user input / output device of the. Furthermore, the address The manipulator chip 106 is also connected to the control bus 138, which in FIG. Used to exchange control signals with other processors in the system.   The system of FIG. 1 further comprises an audio / video processor chip 140. The chip is bidirectionally connected to both halves 118 and 120 of the D bus. Together, it is connected to receive data from the 32-bit wide S bus 122. The audio / video processor chip 140 is also connected to the control bus 138. Address bit A (15: 2) from the system address bus 104 Connected to receive. Generally, an audio / video processor chip 14 0 is the display path circuit, audio subsystem, timer, interrupt Includes controller, expansion bus interface, and watchdog timer There is. The expansion bus interface connects to the expansion bus 142, which is a control bus. Carries line 144 and multiplexed address and data information. An 8-bit bus 146 is provided. The expansion bus 142 is a CD / CD-ROM Supports devices such as layer 148 and optional expansion bus RAM 150 It The CD / CD-ROM player 148 is installed in the housing of the system shown in FIG. Embedded software (including routines described herein) in the CPU 102. It has a primary mechanism for loading into the system for execution.   The audio / video processor 140 has an audio line 157, a control line. Audio / video output circuit 15 via a 156 and a 12-bit AD bus 158. Communicate with 2. This audio / video output circuit 152 generally And the output video waveform. This is a composite video output, standard television RF output, SVHS output and separate left and right audio signals Give output.   The system of FIG. 1 also includes a decompression coprocessor 166, which controls Bus 138, bits A (15: 2) of system address bus 104 and D bus It is connected to both halves 118 and 120. The decompression coprocessor 166 uses C D / CD-ROM player 148 or software loaded into the system from another source Used to decompress software.   System starting from address 0 and extending to 0, 8, 16 or 32 kbytes The section of memory is defined as SYSRAM. Soft size selection Done by software. The address manipulator chip 106 is a user software. Software to write to and read from SYSRAM It has a protection function. The software executed in the supervisor mode of the CPU12 Only the software writes to SYSRAM.   All system address and timing signals are addressed by the address manipulator chip. Is generated by the group 106. CPU 102 or audio / video processor Any request to access system memory from the 140 Data chip 106.   Except for the SYSRAM allocation, and shifted from the video RAM S port 1-megabyte limit for the expected data structures (physical (Exists only because there is a VRAM boundary) The constraints on where the various parts of the system are placed in system memory are minimized. It Smallest system with only 1 megabyte of system memory (VRAM) Also, the lower 64k 32-bit words contain CPU instructions and data. Next 300 kbytes of contains the uncompressed 8-bit image source data, and The next 172 kbytes contain audio and other data. Next 150 kbytes Is allocated to one frame buffer (320 x 240 pixels x 2 bytes / pixel), and the last 150 kbyte is the second frame buffer Assigned to the user.   These frame buffers have even data lines in the left memory bank. And odd data lines are present in the right memory bank. Pixel It is represented as a 16-bit value divided as follows. That is, 5 bits is a red pen Number, 5 bits represent the green pen number, 4 bits represent the blue pen number , And the two bits are the sub-position bits H and V. Another data format , One of the H or V bits replaces the fifth blue pen number bit Can be When pixel values are sent down the display path, The look-up table stores each 4 or 5 bit pen number into the corresponding color DAC. Is converted to an 8-bit value. Color lookup table updated before each scan line can do. Pixels are as low as 320x240 pixels / frame Are stored at the resolution, and the H and V sub-position bits actually map to the specified color. The quadrant of the low resolution pixel area is considered to be placed.   FIG. 2 is a main function of the address manipulator chip 106 of FIG. It is a symbol block diagram which shows a unit. This is the internal 32-bit MDT data It has a bus 202 and an internal 32-bit MADR address bus 204. The MDT data bus 202 passes through the buffer 222 and the left and right half system D buses 11 8, 120 is connected. The chip 106 is a CPU interface unit. It also includes a switch 206, which receives the CPU generated address via the A bus 104. Both are communicatively coupled via control line 128 to CPU 102. Control In 128, the MCLK signal is sent to the CPU by the CPU interface 106. Sent to the MCLK input of 102 (memory clock input of CPU 102). Ad Resmanipulator 106 extends CPU cycles for slow access With this clock signal, the CPU 102 is put into a sleep state for a long time. Control the waveform. ARM60 CPU maintains minimum clock input frequency It is a static part that is unnecessary.   The address generated by the CPU 102 is stored in the D bus arbiter 210 When granting the control right of the D bus and the address generator 208 to the 102 And is passed to the address generator 208 by the CPU interface 206. It The address generator 208 uses the upper address bits from A (31:16). Drive to the MADR bus 204, where the address decoder 212 Loaded. The address decoder 212 receives the desired add from these bits. Determines whether memory represents a memory-mapped hardware register, and if so, Activating the appropriate select lines to activate the appropriate hardware elements in the system of FIG. To notify. This hardware element is then loaded onto the system address bus 104. Perform the desired function in response to bits A (15: 2). Desired ad Address decoder 212 determines that the address is part of system memory 108. If so, the address generator 208 is so notified. Address generator The lator 208 includes LCTL and LA buses 112 and 110 and RCTL and RA buses. Appropriate address and control signals are generated on buses 116 and 114.   The address generator 208 connects the CPU interface 206 to the CPU. After receiving the address, the address is also received from the sprite engine 214. take. The address generator 208 also maintains a stack of DMA control information. Then, an address for DMA transfer can be generated. D-bus arbiter 2 10 receives requests from various devices for transfer over the D bus and sends them Arbitrate and indicate to address generator 208 which request should be met It Even though the two halves of system memory are addressed and controlled individually Even so, only one master works at a time. The winning requester is DMA If a send request is made, the D bus arbiter 210 will respond to the requested transfer. DMA group indicating where in the DMA stack the desired control information is found The address is supplied to the address generator 208. In fact, DMA group The dress identifies a particular DMA channel. The DMA interface is It is completely handled within the dress manipulator chip 106.   The sprite engine 214 is connected to the internal MDT data bus 202, and The function and operation of the sprite engine 214 will be described in detail below.   The address manipulator chip 106 also includes a player bus 136 and a low-speed bus. Player bus interface 21 for interfacing with each device 130. 6 and low speed bus interface 218 are also provided. These are explained in detail here There is no need to reveal.   The D bus arbiter 210 accesses the D bus and D port of the system memory 108. Receive requests from various requesters to access. The D-bus arbiter 210 is When the bus is granted to a specific requester, a confirmation signal is sent to the requester. D Basua Although it is not necessary to describe the arbiter in detail here, the CPU 102 is Intentionally lowest priority in arbitration for access to 108 D ports Note that is given. Because in the architecture of Figure 1 Because the CPU 102 is considered to execute only the housekeeping function. is there. All other functional units in the system are more memory than CPU It is closely connected to and can perform those functions at high speed. Wear. To date, the CPU has numerous detailed fans of interactive multimedia systems. The requirement to perform actions is either limited to system performance and realism, or In addition, it is necessary to use an expensive CPU, or both. II.Sprite operation subsystem   The sprite engine 214 (FIG. 2) uses the “improved corner calculation engine” described above. Sprite Rendering System with Jin and Improved Polygon Paint Engine Stem "and" improved method and apparatus for processing image data ". It is described in detail in the patent applications. I will not repeat these explanations, but here Conventional imaging systems are built around the concept of "sprite" However, it should be noted that the examples described here rather refer to "spryte". It is useful to see. The spelling difference is intentional. Conventional "Sprite (sprite) '' consists of a rectangular area of image data, The scan lines have the same length. On the other hand, "spryte" is here Editing a horizontal scan line that extends from a vertical (hypothetical) sprite edge line to its right Each scan line is defined to contain data representing a number of successive source pixels. Each The length of the plite scan line is the EOL (end of line) end code or other suitable means. Individually controlled by. The vertex of the sprite edge line is the sprite corner position. Defined by The total number of horizon lines that collectively define a sprite is Given by Prite line count. Sprites run without pixels Can be included in the sprite and certain pixels within the sprite are transparent (transparent Can be instructed as Therefore, in reality, sprites It can be considered as having any desired size. III.Address generator 208   FIG. 3 is a block diagram of a portion of address generator 208 (FIG. 2). FIG. 4 is a block diagram of stack address logic 336 (FIG. 3), and FIG. 5 is a block of left and right address pad logic units 345, 353 (FIG. 3). It is a figure. These units are based on the above-mentioned patent application "Audio / Video Computer". Data architecture, and will not be repeated here. Shi However, the address generated by the CPU and emitted from the sprite engine Address is sent to the memory 108 via each input port of the multiplexer 316. Be done. All other system memory accesses use the DMA stack 312 for D Performed by MA.   The 128 22-bit registers in the DMA stack 312 are grouped together. Organized, each group provides the information needed to control each DMA "channel". Remember. Each group has a fixed set of addresses in the DMA stack 312. And each channel is routed from a particular source device to a particular destination device. Predefined to control delivery. Table I used for sprite engine It shows some information about the channel being played.                               Table i IV.Sprite control block (SCoB)   How the sprite source data is provided to the sprite engine 214 Before explaining, the data known as Sprite Control Block (SCoB) It may be useful to describe the structure. SCoB is a specific sprite Control the hardware operations to be performed. Sprite engine 214 Before calling, the CPU 102 makes such an SC in the system memory 108. Prepare a linked list of oBs and address the memory map registers. It loads into the register 208 and indicates where the first SCoB is found.   The SCoB data structure contains the words shown in Table II below.                               Table II                           SCoB data structure Number of bits   name        Explanation   32 FLAGS Classified flags. This is a sprite rendering                       It is the first word read by the software.                       (Flag bits are detailed in Table III below.)   24 NEXTPTR Address of the next SCoB to process. (The format is absolute                       (Relative or relative) sprite rendering                       By going through the linked list with SCoB                       Done. The first source sprite is defined by its SCoB                       Is painted and mapped to the destination grid area                       After the sprite rendering engine, the next SCoB                       Process the source sprite, if any, and                       Render to the specified destination surface of. Linked                       The list can be repeated if desired.                       It is circular.   24 SOURCEPTR The image data to be rendered as a sprite.                       Address in stem memory 108.   24 PIPPRT loaded into the IPS unit of Sprite Engine 214                       Should be stored in the system memory 108 of the Pen Index Palette (PIP).                       Address to open.   32 XPOS in the upper left corner of the sprite to be rendered                       Horizontal position in destination grid (640 maximum pixel                       16) that represents the decimal (non-integer) position definition part                       Including   32 YPOS in the upper left corner of the sprite to be rendered                       Vertical position in destination grid (480 maximum pixel                       Matt), including a 16-bit fractional part.   32 DX scan first sprite row and remap to destination grid                       Is the first mapped corner of the source pixel when                       From the source pixel to the second mapped corner of the pixel                       Position increment (format is two 16-bit halfwords                       Yes, these are fractional forms of integers such as 12.20                       Represented by.)   32 DY Saw when scanning and remapping the first sprite row.                       Source Pixel from the first corner of the Spixel map                       Increase vertical position to third mapped corner of cell (1                       2.20).   32 LINEDX First from the upper left corner of the first mapped sprite line                       Rows to the top left corner of the 2 mapped sprite rows                       Increase horizontal position in the front grid (16.16).   32 LINEDY Vertical position increase from 1st line to 2nd line (16.16).   After each row of 32 DDX sprites are rendered                       Increase to DX for the row (12.20).   32 DDY Increase to DY for each successive line processing after the 1st line                       Added (12.20).   32 PPMPC PPMP control word (two halves: 16,16)                       (See Table IV).   32 PREO Possible first word.   32 PRE1 Possible second preword.   The bits of the FLAGS word above are defined as described in Table III. . These flag bits are specific flags of the sprite rendering engine 214. Control the switch and rendering operations. Data specific control bits are source Found in the previous word of the data.                               Table III                           FLAGS word   bit    name        Explanation     B31 = SKIP If set, skip this SCoB.     B30 = LAST If set, this is the last SCoB to process.                         is there.     B29 = NPABS 1 = absolute address for NEXTPTR, 0 = relative address.     B28 = SPABS 1 = Absolute address to SOURCEPTR, 0 = Relative address     B27 = PPABS 1 = absolute address for PIPPTR, 0 = relative address.     B26 = LDSIZE Load 4 words of size and slope data.                         (DX, DY, LINEDX, LINEDY)     B25 = LDPRS Load two words of perspective (skew control) data                         (DDX, DDY).     B24 = LDPPMP New PPMP control word (PPMPC) in PPMP control register                         To load.     B23 = LDPIP Load new PIP data into PIP.     B22 = SCoBPRE front position. 1 = end of SCoB, 0 = start of source data.     B21 = YOXY Convert XY value to system memory address value and                         Write the corresponding data to the hardware.     B20: B19 = xx has been specified.     B18 = Render the destination pixel for ACW CW (clockwise) orientation.                         forgive.     B17 = ACCW Allows rendering of destination pixels for CCW.     B16 = TWD If this splice is encountered in the wrong direction (CW-CCW)                         To finish rendering the image.     B15 = LCE Lock the operation of two corner calculation engines together                         (In H change).     B14 = ACE Allow the second corner calculation engine to work.     B13 = Allow ASC super clipping (local switch                         ANDed with ASCALL).     B12 = MARIA 1 = Disable all match area loading operation and set destination line                         Use only fast Munkee decisions as instructions to the filler                         To do.     B11 = PXOR 1 = Set PPMP XOR mode. (Disable adder                         XOR the A and B sources during )     B10 = USEAV 1 = Use "-AV" bit of PPMPC to control PPMP-match function                         To do.     B9 = PACKED primary source sprite type, 1 = packed, 0 = complete                         Literals, (secondary source sprites are always                         It is Le. )     B8: B7 = DOVER D-Mode override. 00 = generated by IPS unit                         Select the output of CMUX using the D bit stored. 01 =                         Specified. 10 = Select A input of CMUX. 11 = CMUX                         Select B input.     B6 = Alternative to SCoB selection made by PIPPOS B15P0S and BOPOS                         Alternate PIP generation bit to sub position bit (output PEN signal                         Used as BO & B 15).     B5 = BGND 1 = Background sprite type.     B4 = NOBLK 1 = No black sprite type.     B3: BO = PIPA PIP address bits. These are Unpacker's BPP                         If (bit / pixel) output is less than 5 bits wide                         For packing PIP address input signals that are 5 bits wide                         used.   The PPMP Control Word (PPMPC) has two 16-bit wide halves. There is. One half is used when the CMUX select control bit = 0, and The other half is used when the CMUX select control bit = 1. Only the upper half Bits are defined as shown in Table IV. The lower half has the same structure.                               Table IV                             PMPPC word   bit    name        Explanation     B31 = S1 Selects first multiplier input signal. 0 = IPN (source A)                         use. 1 = use cFB data (source B)     B30: B29 = MS Select the second multiplier input signal. 0 = MxF (source is                         SCoB), 1 = MUL (source is IPS), 2 = IPNM (source is IPS)                         3 = xx (multiply by default value 1 or 0).     B28: B26 = MxF multiplication coefficient. 0-> means multiplication by 1-> 8.                         (Used only when MS = 0.)     B25: B24 = Dv1 1st division by multiplying factor. Divide by 1 = 2. Divide by 2 = 4.                         3 = + 8, divided by 0 = 16.     B23: B22 = S2 Secondary input signal selector. 0 = "value 0 on adder port B                         Grant ”. 1 = Use AV word (from SCoB).                         2 = use cFBD (source B) 3 = IPS output (source A)                         use.     B21: B17 = AV adder value. 5-bit value to be added when S2 = 1                         Is. This 5-bit signal is, if USEAV = 1,                         Also used as a match control word.     B16 = Dv2 post-addition, second divider. Divide by 0 = 1. Divide by 1 = 2.   In addition to giving the "addition value", the AV bit is Perform a secondary function. This secondary function is shown in Table V.                               Table V                       Secondary AV bit function   bit    function     At AVO = PMPP, the output of the second divider is inverted and the carry of the adder is set.             To put.     AV1 = Sign extension funk for the signal flowing downstream on the second matching side of PMPP             Option (XOR enabled later).     AV2 = Disable wrap limiter function. (8 bits             Uses the 5 LSBs of the adder output and is above 31 in decimal or in decimal             Ignore the possibility of wrapping below 0. )       AV3: AV4 = Select the second side divider value as follows. Divide by 00 = 1. 01 = 2l             division. Divide by 10 = 4. 11 = Divide by (reciprocal).   Also, a general sprite rendering engine control tool called SCOBCTL0. There is also a code. It is loaded only by the CPU. Take these bits Shown in Le VI.                               Table VI                   SCOBCTL0 engine control word   bit    name        Explanation     B31: B30 = B15P0S B15 oPEN selector for the output of PMPP. (This bit                         Defines the bits used by the pre-display interpolator                         Can function as a sub-position. ) 0 = 0, 1 = 1,                         2 = xx, 3 = same as source data.     B29: B28 = BO o PEN selector for output of BOPOS PMPP. (This bit                         Also defines the bits used by the pre-display interpolator                         Can function as a sub-position. ) 0 = 0, 1 = 1,                         2 = PPMP match, 3 = same as source data.     B27 = SWAPHV 1 = Swap H and V sub-positions before entry to PPMP                         Up.     B26 = ASCALL 1 = Allow super clipping function.                         (Master enable switch)     B25 = xx has been specified.     B24 = CFBDSUB 1 = cFB When data is selected as PPMP source,                         Instead of the ply source value, the H and V s                         Use the position bit.                         (Note: CFBDse1 = (S1 = 1) OR (S2 = 2))     B23: B22 = CFBDLSB cFBD PPMP Blue LSB source. 0 = 0, 1 = cFBD [BO],                         2 = cFBD [B4], 3 = x.     B21: B20 = IPNLSB IPN PPMP Blue source. 0 = 0, 1 = IPN [BO],                         2 = IPN [B4], 3 = x.   "Relative" to NEXTTR, SOURCECEPT or PIPPTR flags Is specified, the value that must be entered in SCoB has a relative value. Desired to be a new address MINUS FOUR from the RAM address Note that it is the word distance to the address of the RAM that is stored. (REL = Target-PC-4). Also, for the BOPOS value of "2", use PPMP match. And the only setting to control the B0 bit in the actual output oPNEN signal Also note that When this setting is selected, the black detector The input parameters also include Blue LSB.   The sprite image data includes a full literal format and an incomplete literal format. There are two basic formats of matte. Within each basic format There are subgroups. In non-perfect literal sprites, the image data is Data source scan line. Full literal sprite Image data is pure image data (mixed control functions). There is no service).   Non-perfect literal sprites require a 1-word preamble (preamble) However, a full literal sprite requires a 2-word preamble. These front stage The subword is the end of the SCoB word as shown in Table II (but the PIP May be placed before), or may be placed at the beginning of the image data. these The normal position of a word is at the beginning of the image data, but the frame buffer format For a fully literal sprite of a It is the end of CoB.   Non-exact literal sprites save both memory space and rendering time. It can be made compact to save. Each source scan line of data is It has a horizontal word size specified as part of the data. Full literals The prite has a rectangular format specified in the front part of the data.   The first pre-word for all sprites is the data structure pre-stage. It contains data specific control bits for the source data, Defined in Le VII.                               Table VII   B31-> B21 = Specified. Set to 0.   B20 = PACKED. This is equal to the PACKED bit in SCoB.   B19-> B16 = Specified. Set to 0.   B15-> B6 = VCNT The vertical number of source data lines in this image data,               Eggplant 1 (10 bits).   B5 = Specified. Set to 0.   B4 = LINEAR. 0 = Use PIP to generate IPN output for IPS unit               To do. 1 = Use PIN to output IPN   B3 = REP8, 1 = duplicate bits in linear 8 sprites.               It satisfies 0 = 0.   B2-〉 B0 = BPP. Bit / pixel, pixel type.   VCNT is loaded into the sprite requester's hardware counter, and It is decremented at the end of each source scan line fetch of data. Count is -1 When there are no more data source lines in the object. Sprite processing is here But this is just one of the events needed to finish a sprite. Please note that. VCNT = line count-1.   The initial value of -1 for VCNT is "real large sprite". Let it go. There is no "zero line count" value.   The LINEAR bit has a BPP type of 8 bits / pixel or 16 bits / Only applicable when pointing to pixels. In these cases, without PIP There are enough PIN bits to give a 15-bit IPN at. PIN bit is IP Disperses linearly over N and produces a linear conversion from PIN to IPN Therefore, this mode is referred to as "LINEAR". This LINEAR bit LINEAR8 and LINEAR16 (for "normal" 8 or 16) four Pairs with sprites with 8 or 16 bits / pixel known as Matt And then set.   REP 8 bits are only available with a source data size of 8 bits / pixel It is effective.   Table VIII defines BPP control bit decoding.   If the PACKED bit of SCoB is "0", the source data is complete Is a literal. In the case of a completely literal sprite, the second front end work There is This is a horizontal line for each line of source data, among other things. Xcel count and word off from one line of source data to the next Including set and. These bits are completely literal sprite rendered Is only valid while being spawned, and currently the sprite is not completely literal. Not used The bit field of the second front word is defined in Table IX below. Mean                               Table IX                   2nd sprite data front word   B31-> B24 = WOFFSET (8). Word from one data line to the next                 Offset (-2) (8 bits). Offset bits 23-> 16 are set to 0                 Is set.   B25-> B16 = WOFFSET (10). The data from one data line to the next                 Offset (-2) (10 bits). Offset bits 31-> 26 are 0                 Is set to.   B15 = Specified. It is set to 0.   B14 = NOSWAP 1 = SWAPHV bit from general sprite control word               Disable.   B13-> b12 = TLLBS IPN PPMP Blue LSB source. 0 = 0, 1 = IPN [0],                        2 = IPN [4], 3 = IPN [5].   B11 = LRFORM left / right format.   B10-> B0 = TLHPCNT Horizontal pixel count (-1) (11 bits).   The TLSLSB bit tells IPNLSB what to do in a normal sprite. Perform the same function.   If LRFORM = 1, the source data is the screen frame buffer. Format as a source format. Rectangular display space Vertically adjacent pixels in a memory cell are Adjacent to the flat. This is a fully literal data format of 16 bits / pixel. Useful for mats. Unpacker for Sprite Engine 214 is "B" Disables FIFO data requests and allows pixels from the source to both Alternate in O. The left 16 bits go to the "A" FIFO, the right 16 bits Go to "B" FIFO. "A" FIFO data requests are for page breaks and other Requests are made "paired" to minimize the latency of. Hardware corners Lock the engine to work together (regardless of the LCE bit).   TLHPCNT is the number of pixels in the horizontal dimension minus one. This is because the sprite engine 214 has The number of pixels to try to render. This value can be used. A "0" value for TLHPCNT attempts 1 pixel. "-1" value is Try a large number of pixels. There is no "0 pixel count" value.   WOFFSET is the method from the start of one data line to the start of the next line. It is the offset of the Mori word minus 2. BPP of this sprite Is 8 or 16 bits / pixel format, WOFFSE T (10) or WOFFSET (8) are suitable. This number is the minimum size Zero for sprites (2 words).   By properly arranging WOFFSET and TLHPCNT, a large size The rectangular data area can be extracted from the rectangular data area.   Also, the address generator 208 uses WOFFSET for normal data fetching. Used as a length value in the process. WOFFSET and TLHPCNT are WOFFSET must be set so that it does not finish first.   In the sprite packed data format, the sprite source data The first 1 or 2 bytes of data on each line of data are the source data Subtract 2 from the word offset from the start of the in to the start of the next data line Includes things. In sprites with less than 6 bits per pixel Uses an offset of only 1 byte (bits 31:16). But Naga Thus, the actual offset has a maximum size of 10 bits. 2 bytes left More bits are set to 0. 10 bits of word offset is 16 bits There are 2048 pixels per pixel. 6 bits / pixel The 8 bits of the offset are 1365 pixels. 12 are needed It is 80 pixels.   This offset is used by address generator 208 to Compute the start of the next line of source data (add it to the start of the current line Set the maximum length for the current DMA transfer (by subtracting 1) (By adding it to the DMA stack length register).   Also, in the packed sprite data format, after the offset The next data is the control byte and zero or more PIN data bits. For each PIN The number of bits used is specified by BPP.   The control byte consists of a 2-bit code and a 6-bit count as follows.   00xxxxxx End of line, xxxxxx need not be present.   01count Literal PIN for "count + 1".   10count "transparent" defined for "count + 1".   11count "PIN" packed against "count + 1".   The definition of "transparent" actually outputs the "transparent" bits from the unpacker. This causes the rest of the pixel processing pipe to ignore this pixel. V.Sprite rendering process   To render the sprite into an area of system memory 108, the CP The U102 first sets up the necessary data in different areas of the system memory 108. Up. All such data is located adjacent to system memory 108. 6 to 15 32-bit words shown in Table II above and the PIP data 4, 8 or 16 options located adjacent to system memory 108 to represent the data A 32-bit word of the segment and sprite image data of arbitrary length. Te Of the six to fifteen words shown in Bull II, a number of groups are Note that the loop is optional. Also, the second word of SCoB is A pointer to the next SCoB to process, so the CPU processes sequentially Form a linked list of multiple SCoBs, each of which has its own Sprite source data, optional PIP data and sprite render Note also that the grouping control information is defined.   Also, before starting the sprite engine, the CPU 102 outputs some desired information. Write directly to that memory-mapped hardware register as follows:   SCOBCTL0． A 32-bit word defined in Table VI above.   REGCTL0． Source frame buffer data to the sprite engine 214 Read into the primary and / or secondary input ports of the From the sprite engine 214 to the destination frame buffer of the system memory 108. Control the modulo for writing to This modulo is the system memory 10 8 effectively indicates the number of pixels per scan line represented in each frame buffer It   Only the lower 16 bits of REGCTL0 are used. The lower 8 bits are source code Specifies modulo for the rame buffer, and the next 8 bits are the destination frame Specify the modulo for the buffer. Lower for each of the two modulo destinations The 4 bits specify the G1 value, and the upper 4 bits specify the G2 value. Specific Ba The modulo specified for the buffer is calculated as G1 + G2. Therefore, The next bit of REGCTL0 is defined (CFBD is the current frame buffer Data, sprite source data that the sprite engine reads as input data And refer to a separate source buffer).   REGCTL0 bit      Explanation       0 G1 = 32 for CFBD read buffer.       1 Not defined. It is set to 0.       2 G1 = 256 for CFBD read buffer.       G1 = 1024 for 3 CFBD read buffers.       4 G2 = 64 for CFBD read buffer.       G2 = 128 for 5 CFBD read buffers.       G2 = 256 for 6 CFBD reading buffer.       7 Not defined. It is set to 0.       G1 = 32 for 8 destination buffers.       9 Not defined. It is set to 0.       G1 = 256 for 10 destination buffers.       G1 = 1024 for 11 destination buffers.       G2 = 64 for 12 destination buffers.       G2 = 128 for 13 destination buffers.       G2 = 256 for 14 destination buffers.       15 Undefined. It is set to 0.   Software should ensure that no more than one bit is set in each nibble. Must be kept. The hardware doesn't have more than one bit set It does not protect. If the bit is not set in the nibble, it causes the raw The contribution to the modulo is zero.   REGCTL1． The pixels in the X and Y dimensions that form the frame buffer Clip values for X and Y that effectively indicate the number of. Bits 26:16 are in the Y dimension Indicates the last writable row (counting from row 0) and bit 10: 0 is the last writable column in the X dimension (counting from column 0) Instruct. All other bits must be zero. For example, the value 00EF In 013F, the frame buffer data is represented in 320x240 format. Instruct that.   REGCTL2． Read the base address. Source frame buffer data The address in the system memory 108 of the upper left corner pixel of   REGCTL3． Write the base address. Destination frame buffer (CFB Point the address in the system memory 108 of the upper left corner pixel of D). It   Also, the CPU 102 is linked before the sprite engine is started. The address of the first SCoB in the list is set to D Put in MA stack 312 register. The CPU then indicates SPRSTRT. Writes to the specified memory map address to execute the operation of the sprite engine. Let it start. When the sprite engine starts working, all Exclusive control of the D bus until all SCoB processing is completed or an interrupt occurs Hold. In the event of an interrupt, the Sprite Engine will come to a convenient stopping point. , And then release the D bus. The CPU then takes the appropriate interrupt Send the handler vector, and when it is finished, turn the sprite engine back on. Return to the routine that started first. This routine is a memory-mapped status Check the status bit SPRON in the Interface is stopped because of an interrupt or when processing is complete, If it is the former, restart the sprite engine. In another example In that, the CPU has a separate bus for programming the memory, While the sprite engine 214 is rendering the sprite, the CPU 102 It can allow other tasks to be performed. In this example, the sprite The engine interrupts the CPU 102 when the sprite processing is completed. Can be generated, at which time the CPU 102 causes the interrupt handler Can be sent.   The DMA stack 312 has 8 register groups for sprite control. ing. The eight registers are as follows.   0 Current SCOB address (CURRENT SCOB ADDRESS)   1st SCOB address (NEXT SCOB ADDRESS)   2 PIP address (PIP ADDRESS)   3 Sprite data address (SPRYTE DATAADDRESS)   4 Engine A fetch address (ENGINE A FETCH ADDRES)   5 Engine A length (ENGINE A LENGTH)   6 Engine B fetch address (ENGINE B FETCHADDRES)   7 Engine B length (ENGINE B LENGTH)   When the CPU writes to the SPRSTRT address, the sprite engine After obtaining control of the system data buses 118 and 120, the DMA error of FIGS. It is the system specified in the NEXT SCOB register of the DMA stack 312. Load the first 6 words from the first SCoB starting from the stem memory address It To do this, the address of the first word to be loaded is the NEXT SC It is read from the OB register and passed through the source multiplexer 314 to the memory address. Given to the line. In addition, this address is added by the adder / clipper 320. CURR of the DMA stack 312 is incremented and through the multiplexer 310 It is written back to the ENT SCOB register. All 6 words are written like this The CURRENT SCOB register is read from each Keep the address of the word.   The first SCoB word read, FLAGS, is the address manipulator. It is written to the 32-bit hardware register of the data chip 106. Read The next SCoB, NEXTTPTR, is the NEXTS of the DMA stack 312. Written to the COB register. SOURCECEPTR is the DMA stack 312 To the SPRYTE DATA ADDRESS register of PPRT writes to PIP ADDRESS register of DMA stack 312 Get caught XPOS and YPOS are two formats, each with x and y format. Written to memory map hardware registers XYPOSH and XYPOSL . That is, the upper 16 bits from XPOS and the upper 16 bits from YPOS are X Written to the upper and lower half-words of YPOSH, respectively, and lower of XPOS 16 bits and lower 16 bits of YPOS are upper and lower half-words of XYPOSL. Each is written to the card. After the first 6 words of SCoB are loaded, FL Up to 7 additional SCoB words based on the bit set in AGS Loaded. Possible words are grouped as a single DMA transfer up to 7 words. Looped. If the LDSIZE bit of FLAGS is asserted , And the DMA controller of FIGS. 3 and 4 uses D for the first 4 words of this 7 group. Expected to be X, DY, LINEDX and LINEDY. These words are , The first 6 words of SCoB are loaded and incremented as DM Stored in the CURRENT SCOB register of the A stack 312. DX and DY is two memory mapped hardware registers DXY in x, y format H and DXYL, and LINEDX and LINEDY are x, y Two memory map hardware registers DDXYH and DDX in format Written to YL. The SKIP bit of the FLAGS word equals 1 and is currently S Indicate that CoB should be skipped, or if the YOXY bit is zero In some cases, X and Y values are not written to hardware.   If the LDPRS bit of FLAGS is set, then the DMA of FIGS. The control unit uses the first two words (or the next two) of any 7 Of words) include DDX and DDY. These are the x, y format Write to two memory map hardware registers DDXYH and DDXYL. Get caught.   3 and 4 if the LDPPMP bit of the FLAGS word is set. The DMA control unit of this is the first (next) word of any 7 words. I expect P to be PPMPC. This word is a memory map PMPPC Written to the hardware register.   After the second SCoB load of 0 to 7 words, the DMA controller of FIGS. The roll unit performs a 1 or 2 word pre-load. FLAGS S If the COBPRE bit is set, the preceding word (s) are It is assumed to be at the end of SCoB, in which case the CU of DMA stack 312 The RRENT SCOB register contains the address of the first preword. SC If OBPRE is not set, the preceding word (s) is data Is assumed to be at the start of, and in this case SPRYTE DATA ADDRESS Contains the address of the first preword. The DMA control unit is Select an appropriate register source as the start address of the partial load, and increment The returned address to the same register.   The first preword is always present and loaded into the appropriate hardware register. It The second pre-word has the PACKED bit of the FLAGS word equal to zero. Indicates that the sprite image data is in a "fully literal" format Only exists when. WOFF when DMA unit reads this word The information in the SET field is written to the offset register and TLHPC The NT field information is written to the hardware pixel count register. It The offset indicates the width of the fully literal sprite in memory, Then, by the DMA controller, the star of each next line of the sprite source data Used to calculate the rate. Pixel count is a fully literal splat Specifies the number of pixels to be transferred in each scan line of source data. These two values show that both the width and height of the large bit image are larger than the full bit image. Can be set individually to allow transfer of only small rectangular pieces it can.   The LDPIP bit of the FLAGS word was set after the previous load In this case, the DMA control unit is the PIP A of the DMA stack 312. Starting from the address of the DDRESS register, PIN-IPN conversion information 4, 8 or Reads 16 bits. In addition, the increased address is also used for the same DMA stack register. It is rewritten in the studio. The number of 4-word bursts (if any) performed is It is based on the data compression format of the ply image source data, which 1 is specified in the BPP (bit / pixel) field of the preceding word. Than In detail, as shown in Table VIII above, for BPP = 0, 1 or 2 All 4 PIP words are loaded, 8 PIs if BPP = 3 16 words if P words are loaded and BPP = 4, 5, 6 or 7. The IP word is loaded. The PIP data in the system memory 108 is indirectly referenced. The same PIP data can be downloaded from multiple SCoBs Please note that Also, the PIP is currently the sprite image source Data, even if it is not used to decompress the data (the 1st preword LINE The AR bit is 1). 16 PIP words If all are loaded, all PIPs are overwritten. 16 words For less loads, the PIPA field of the FLAGS word is Indicates the start address of the PIP for receiving   After the PIP load, the DMA unit of FIGS. From the sprite image source device to the data input FIFO of the sprite engine 214. Data transfer is started. As mentioned above, the sprite image source data is packed. If it is written (that is, not in full literal format), the sprite source At the beginning of each scanline in the data, the first 1 or 2 bytes of the first word are the source data. Data from the beginning of the current line to the beginning of the next line of source data Includes minus 2. This offset is sourced by the DMA controller. Compute the start of each next line of data, as well as the length of the DMA transfer of the source data line. Used to set the height. Therefore, the DMA controller Address specified in SPRYTE DATA ADDRESS register Read this word from the address, increment the address and put it in the DMA stack Enter the 312 ENNGINE A FETCH ADDRESS register. The upper 8 or 10 bits of this word are the ENNGINE of the DMA stack 312. A LENGTH register and all words are in Corner Engine A Is also sent to the spray engine data input FIFO for. Sprite engine Knows that this word should be ignored. Sprite statue source day If the data is in full literal format, it is specified in the second preword. And the above-mentioned single offset value (and pixel count value) is the same for all sprites. Applied to.   After the offset is loaded, the DMA controller will write a burst of up to 4 words each. Additional words of sprite image source data for the current scan line in the , When requested by the sprite engine 214. For each burst The start address is ENGINE A FETCHA of DMA stack 312. The address seen in the DDRESS register and incremented into the same register. Can be Correspondingly, the DMA controller is based on the number of words transferred. Then, the value of the ENGINE A LENGTH register of the DMA stack 312 is decreased. Less.   The DMA controller also adds the specified offset to the first word of the scan line. The DMA stack 312 SPRYTE DATA ADDRES Update the S register so that the register always sees the next scanline to be processed. To point to.   The above-mentioned patent application "Improved corner calculation engine and improved polygon pay" Based on the conditions described in "Sprite Rendering System with a Print Engine". Then, the sprite engine 214 is set to ENGINE B FETCH ADD. Sprite image using RESS and ENGINE A LENGTH registers Corner engine B data input 4 word burst of next scan line of source data It is also possible to issue a request for DMA transfer to the FIFO. In this way, sprite Both corner engines A and B of engine 214 have different sprite image source data. Can operate simultaneously for different scan lines, and the DMA controller can Data can be burst transmitted to each of them when required.   There are many invalid SCoB bit settings that are not protected in the hardware. Please note that. Software will never assert these combinations Must be secured. These combinations include:   1. The LINEAR bit is set in the first word of the first sprite data And if BPP is set for 8 bits / pixel, then FLAGS D-mode selection in the word DOVER field is determined by the BPP. Must not be set to use the selected choice.   2. If LINEAR is selected, BPP will be 8 or 16 bits / pixel. Must be selected.   3. The BPP field and LINEAR settings in SCoB are set by the incoming software. Must match the format of the source data. If not, then Can not predict the result of.   These are just a few examples, and many others. VI.Software routine   Before describing the software routines used to implement the present invention, the following It would be useful to describe such C language type definitions and macro definitions.   A.Screen and bitmap routines   The sprite engine 214 includes a screen, a screen group ( Three software known as ScreenGroup) and Bitmap Conveniently controlled using a data structure. These structures are On the other hand, is owned by the system and the illegal combination of control information is hardware The information in these structures is stored in the CPU 102 in order to prevent -It cannot be changed unless it is a routine that operates in supervisor mode. screen , Type definitions for screen groups and bitmap data structures are as follows: On the street.   As can be seen, the bitmap structure is sprite engine 214 Destination buffer (typically the display buffer But not limited to this). this Such global information is stored in the buffer base address (bm Buffer) And its width, height and features (each bm With, bm Height and bm Flags) and beyond that, the sprite engine 214 will replay sprites. Clipping width and height (bm) ClipWit h and bm C1ipHeight) and vertical offset value (bm Verti calOffset) and the values of the five sprite engine control registers (bm SCOBCTL0, bm REGCTL0, bm REGCTL1, bm RE GCTL2, bm REGCTL3) is included. The screen structure should be Bitmap structure, screen group structure, and display It contains some other information about   Several for manipulating bitmaps, screen groups and screens A sample routine is shown below. Some of these routines are trivial Is an operating system that can be called by a user program It is convenient to provide it as a routine anyway. Thus, these are CP It can run in supervisor mode of U102. The following routine shows how to modify the buffer's bitmap directly.   The following routine reads the bitmap directly. These are supervisors -No need to be in mode.   B.Sprite rendering routine   As mentioned above, the sprite engine 214 is created and populated with the list together. Linked sprite control block (SCoB). Dolling. Software data structure for SCoB (also called SCB) The construction is conveniently as follows.   Once the SCoB linked list is created, the next supervisor The power mode routine can be used to start the sprite engine 214.   As mentioned above, the sprite engine 214 uses the SC for that sprite. When a proper value is given to oB, the sprite source image is transformed into a quadrilateral (appropriate Or degeneracy). The following routine is the destination quad Given a point in the destination buffer, the user can scb in SCoB X, sc b Y, scb HDX, scb HDY, scb VDX, scb VDY, scb DDX and scb Useful as an aid in calculating the correct DDY value It   A wide variety of basic sprite rendering routines have been added to the above primitives. Is built. These sprite rendering routines use the appropriate SCoB Just form and create them with DrawSprites Link to a list for subsequent rendering by such routines May be written in, or by calling the sprite engine 214 directly Good. Such routines draw a horizontal or vertical line with a specified end point. Routines, routines for filling specified rectangles, and graphics context It may include a routine to draw a line from the current pen position of the strike to the new position. Wear. These routines are all currently in the graphics context foreground color. Forming an SCoB pointing to the sprite image source data containing a single pixel, and scb X, scb Y, scb hdx, scb hdy, scb vdx, scb vdy, scb ddx and scb Set an appropriate value for ddy, and By allowing the Prite Engine 214 to stretch the pixels into the desired shape. Can operate. This routine can then also link SCoB to the list. You can, or use a routine like DrawSprite to sprite The gin 214 can also be called immediately. Fortunately, these routines Maintains the "current" foreground and background colors using the GrafCon data structure And maintain the "current" X and Y pen positions in the destination bit map. This Such a data structure is defined as follows.   When using the GrafCon structure, use DrawSprites A rouch for calling the light engine 214 and drawing a line on the specified bitmap. An example of   Although the present invention has been described with respect to particular embodiments, it will be understood that many may be made without departing from the scope of the invention. It will be apparent that changes can be made to

Claims (1)

[Claims]   1. In the method of rendering the graphic image to the destination buffer,   Prepare the control block in memory, and   The graphics operations processor responds to the control block with the destination buffer. To render the sub-image, The method characterized in that it has a step of.   2. The control block above provides rendering information for each corresponding sub-image. Is one of a linked list of control blocks to hold, and   The step of rendering renders the processor into the linked list. Initiate the sub-image rendering stage in response to successive ones of the above control blocks in The method of claim 1 including the step of:   3. Display the rendered sub-image in the destination buffer as a single image The method of claim 2, further comprising steps.   4. The control block according to claim 1, wherein the control blocks are arranged adjacent to each other in the memory. Method.   5. The step of preparing the control block is the sub-image corresponding to the control block. A sub in the memory used by the processor to render A method comprising writing a pointer to image source data in the control block. The method according to Item 1.   6. The step of preparing the control block is the sub-image corresponding to the control block. Used by the above processor to convert the pixel color values of the source data. The step of writing a pointer to the data conversion table to be written in the control block The method of claim 1 including.   7. The step of preparing the control block is the sub-image corresponding to the control block. Multiple flag bits used by the processor to process the source data. The method of claim 1, including the step of writing a set to the control block.   8. The step of preparing the control block is performed by the processor including the control block. The above image where the rendering of the sub-image source data corresponding to Writing the start coordinate instruction in the play buffer to the control block The method of claim 1, comprising:   9. The step of preparing the control block is performed by the processor including the control block. Each pic to be rendered along the first line of sub-image source data corresponding to Horizontal and vertical pixels in the above destination buffer that should be incremented for each cell Of the number of each, DX and DY, respectively, in the control block. The method according to Item 1.   10. The above steps of preparing the control block are performed by the processor in the control block. The above for each rendered line of the sub-image source data corresponding to Horizontal and vertical in the destination buffer where the values DX and DY should be increased respectively. 10. The method of claim 9, further comprising writing an indication of the number of direct pixels in the control block. The method described.   11. The above steps of preparing the control block are performed by the processor in the control block. Where the rendering of the second line of sub-image source data corresponding to The starter coordinates in the destination buffer are set by the processor to the control block. Should start rendering the first line of sub-image source data corresponding to The processor increases relative to the start coordinate in the destination buffer of the roller The control block gives an indication of the number of horizontal and vertical pixels in the destination buffer that should be The method of claim 1 including the step of writing to a dock.   12. The above step of preparing the control block corresponds to the sub-block corresponding to the control block. Which of several available data compression formats to use for the image source data 2. The method of claim 1 including the step of writing the instructions in the control block.   13. The steps of preparing the control block include the sub-image source device in the memory. The data source to indicate which of the available data compression formats to use. The method further comprising writing to the beginning of the sub-image source data in the memory. The method according to 5.   14. What the processor should consider when defining scanlines in the destination buffer. Writing a value instructing the number of pixels in the control register (REGCTL0) The method of claim 1, further comprising:   15. The processor renders the sub-image into the destination buffer While combining the sub-images with additional image parts, and   The processor should consider the following points when defining scan lines in the additional image portion. The step of writing a value indicating the number of xcels to the control register (REGCTL0) is added. The method according to claim 1, which is provided for.   16. The base address in the memory of the destination buffer is set to the processor. And a step of writing a value instructing the server to the control register (REGCTL3) The method of claim 1.   17． The processor renders the sub-image into the destination buffer When combining the sub-image with the additional image part,   The base address in the memory of the additional image portion is given to the processor. The method further comprising the step of writing an indicating value to the control register (REGCTL2). The method according to Item 1.   18. Write the horizontal clip value to the control register (REGCTL1) Destination pixels that exceed the horizontal clip value horizontally do not need to be rendered The method of claim 1, further comprising the step of instructing the processor to:   19. Write the vertical clip value to the control register (REGCTL1) Destination pixels that exceed the vertical clip value vertically need not be rendered The method of claim 1, further comprising the step of instructing the processor to:   20. How to render a graphic image to a display buffer hand,   A control block link that holds rendering information for each corresponding sub-image. Prepared list in memory, and   The graphics operations processor responds to successive blocks of the above control blocks. To start the sub-image rendering stage, The method characterized in that it has a step of.   21. CPU used with CPU, graphic manipulation processor and memory In a computer-readable medium,   First computer instructions executable by the CPU, the instructions being stored in the memory First computer instructions for preparing a control block;   Second computer instructions executable by the CPU, the graphics The operation processor responds to the control block with a destination buffer in the memory. A second computer instruction causing the sub-image to be rendered. Characteristic computer-readable medium.