JPH0846496A - Circuit and method for time delay and data fetch apparatus - Google Patents

Abstract

PURPOSE: To provide a high-speed time delay circuit with which time delay can be digitally set. CONSTITUTION: A 1st gate device 10 has input and output terminals and one of capacitors 20A-20d has 1st and 2nd terminals at least. The value of this capacitor can be digitally set and its 1st terminal is connected to the output terminal of 1st gate device. An accumulator 22 is connected to the 2nd terminal of capacitor, supplies one digital constitutive signal to the capacitor at least and sets the capacity characteristics of this capacitor. Thus, the signal supplied to an input terminal 14 is delayed and propagated to an output terminal 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time delay circuit and a method of using the same, and more particularly to a high speed time delay circuit in which the delay time can be set digitally, a method of setting the delay time of such a circuit, and The present invention relates to a data acquisition device used.

Time delay circuits have a wide range of applications in the electronics field. In particular, the time delay circuit is useful in a high speed and high precision data acquisition device that samples an analog signal for digital processing. These applications include, for example, oscilloscopes and digitizers. In these applications, a predetermined number of time delay circuits are combined to form a delay line that produces a series of strobe signals. Note that each strobe signal triggers sampling of the analog signal. Ideally, the delay line produces a continuous strobe signal at uniform time intervals so that the sampled values accurately represent the analog signal.

However, in practice, a conventional delay line that operates at high speed is generally caused by a variation between time delay circuits.
We could not properly generate continuous strobe signals at uniform time intervals. These variations include, for example, timing errors, which led to incorrect sample values.

One approach to this problem is to use digital signal processing correction algorithms to correct the sample values. The correction algorithm uses the timing information for the particular delay line along with the sample value taken to calculate the value of the sample closer to the value taken in the absence of timing error. However, the correction algorithm has significant limitations. One of these limits is that the algorithm reduces the acquisition throughput, ie the number of samples per unit time. Furthermore, this algorithm
In general, not all timing errors can be corrected accurately.

Another approach minimizes delay variation between time delay circuits in the delay line. In the conventional time delay circuit, among various methods, as shown in FIG. 2, a selected number of time delay circuits TDC1 to TDCn are connected in series, and taps T1 to Tn are provided at the output terminals of each time delay circuit. It can also be configured by The clock signal is the first
It is supplied to the clock input terminal of the time delay circuit TDC1,
It propagates through each of the subsequent time delay circuits TDC1 to TDCn. The delayed clock signal is output as a strobe signal at each tap. When the clock signal propagates, strobe signals are generated at time intervals according to the time delay of each time delay circuit.

A conventional time delay circuit used to construct the delay line of FIG. 2 is shown in FIG. This time delay circuit
It comprises serially coupled inverters I1 and I2 and a capacitor C1 having one end connected between these inverters and the other end grounded. As shown in FIG. 4, when the clock signal is supplied to the input terminal of the inverter I1, the inverter I1
It is delayed from 2 by Δt and output from the output terminal. The main factor of this delay is a function of the capacitance of the capacitor C1, the output impedance of the inverter I1, and the switching threshold of the inverter I2, although there are other factors. When the output of the inverter I1 becomes "high", the capacitor C1
Is charged at a rate according to its capacity, and when the output of this inverter becomes "low", the capacitor C1 is discharged at that rate. When the capacitor C1 charges and discharges, the switching threshold of the inverter I2 crosses and the inverter I2 switches the output state. Therefore, the time delay circuit outputs the delayed clock signal.

In order to minimize the timing error of the delay line composed of a plurality of the time delay circuits shown in FIG. 3, the inverter and the capacitor through the delay line are ideally matched. However, in general, even if it is possible, it is technically and economically difficult to appropriately select a suitable component for a high-speed and high-precision application when constructing a circuit using semiconductor technology. . For example, the semiconductor technology, which is self-aligned polysilicon gate CMOS, is used not only between circuits on different dies on a wafer,
Even between circuits on a single die, one encounters variations that affect component parameters. Moreover, as applications continue to demand higher speeds and higher precision, it becomes more difficult to properly match the parts.

Another approach to generate a continuous strobe signal at uniform intervals and at high speed is to make the time delay adjustable in each time delay circuit of the delay line.
One of such time delay circuits is shown in FIG. This time delay circuit is almost the same as the circuit of FIG. 3, but the fixed capacitor C1 of FIG. 3 is replaced with a voltage control capacitor. This voltage controlled capacitor can be realized using a field effect transistor Q1, whose drain and source are coupled together and whose gate is supplied with a variable analog voltage input Vg. In order to control the circuit delay, Vg is selectively set to a gate voltage such that a desired capacitance can be obtained from the transistor Q1. That is, the capacity is made to correspond to the desired delay. If a delay line is constructed using this time delay circuit, the delay of each circuit can be adjusted individually and the strobe signals of successive delay circuits can be made uniform. A time delay circuit using a non-linear voltage control capacitor realized by using field effect transistors is disclosed in US Pat. (Corresponding to Japanese Patent Laid-Open No. 6-28884) "High-speed sample and hold signal generator".

These time delay circuits have adjustable time delays, but they have significant limitations. For example, M
The voltage adjustment capacitor realized using the OS transistor is a non-linear function of the bias voltage. So, in particular,
When the required capacitance is within the capacitance range that is very sensitive to the gate voltage, it is difficult to obtain the specific capacitance required to adjust the delay of the time delay circuit. Also, if not, the situation is not good. Furthermore, each time delay circuit of the delay line is
Different analog voltages need to be supplied to adjust the delay. Supplying these voltages tends to have undesirable consequences. For example, if the time delay circuit is implemented in an integrated circuit, an undesired area of the die area must be used for the circuits that provide different gate voltages to each time delay circuit. For this circuit,
For example, digital-to-analog converters and associated metal interconnects.

FIG. 6 shows another time delay circuit which makes it possible to adjust the time delay in each time delay circuit. This time delay circuit is almost the same as the circuit of FIG. 3, but instead of the fixed capacitor C1 of FIG. 3, it is replaced with a plurality of capacitors using field effect transistors Qc. The drain and source of each transistor are coupled together and grounded.
The gate of each transistor is set to one of a plurality of linear switches SW.
Each switch SW is composed of an n-channel transistor and a p-channel transistor. Each switch is used to selectively connect or disconnect the capacitor provided by the associated transistor to the time delay circuit. These switches connect the transistor in parallel with the inverter. The overall capacitance of the transistor, ie
The corresponding delay of this circuit is adjusted by connecting the appropriate number of transistors. A time delay circuit using a plurality of capacitors realized by using field-effect transistors that switch in this way is disclosed in U.S. Pat. No. 5,051,630 by Kogan et al. Delay Generator ".

This time delay circuit has an adjustable time delay, but has a significant limitation in high speed applications. For example, switches and their associated induced resistances and stray capacitances limit the speed of time delay circuits.
Thus, this type of time delay circuit is generally not well suited for high speed applications.

[0012]

Accordingly, there is a need for an improved time delay circuit and method of utilizing the same. In particular, there is a need for a method in which the time delay can be set digitally and the delay of such a circuit can be set (configured) accurately.

Accordingly, one of the objects of the present invention is to provide a new and improved time delay circuit and method of using the same. Another object of the present invention is to provide a high-speed time delay circuit capable of digitally setting (configuring) a time delay. Still another object of the present invention is to provide a method capable of precisely adjusting the delay of a digitally settable high-speed time delay circuit. Another object of the present invention is to provide a circuit and a method capable of digitally constructing capacitors each having a selectable capacitance for use in a time delay circuit to provide a time delay. Yet another object of the present invention is a circuit that uses digital configuration signals rather than analog voltage to select capacitance to overcome the difficulties commonly associated with analog regulation of voltage controlled capacitors implemented using field effect transistors. And the provision of a method.
Another object of the present invention is to provide a circuit and method that selects the capacitance of one or more digitally set capacitors and does not use independent linear switches. Another object of the present invention is to provide a circuit and method in which the capacitance can be approximately binary weighted with selectable capacitors whose semiconductor dimensions are scaled.

It is another object of the present invention to provide a circuit and method that provides at least two capacitors in which the capacitance difference between the capacitors is a predetermined very small increment and a very small delay difference can be set. Another object of the present invention is to provide a circuit and method for constructing and setting a tapped delay line that can be used especially in precision data acquisition and measurement equipment to generate continuous strobe signals with uniform time intervals. Yet another object of the present invention is to provide a circuit which, when implemented on a relatively large number of integrated circuits, has a relatively small overall die area and consumes relatively little power, especially continuous power. It is in.

[0015]

The present invention will be described in detail in (i) below.
The above need is met by providing a time delay circuit comprising (ii) and (ii). That is, (i) is a first and a second gate device, preferably an inverter, the output end of which is coupled to the input end of this second gate device at a common node. (Ii) is a plurality of digitally configured capacitors. Each capacitor is preferably constructed using field effect transistors. The gates of one or more such transistors are connected to one of a plurality of component lines, the corresponding drains and sources of which are coupled to each other and to a common node. Instead, the gates of one or more of the transistors are coupled to a common node while their corresponding drains and sources are coupled to each other and to one of the plurality of component lines. This configuration line carries each digital configuration signal stored in and provided by the digital storage device. The digital configuration signal sets the capacitance characteristics of each digitally set (configured) capacitor. The capacitor becomes a capacitive load on the first gate device at the common node.

Particularly, the capacitance characteristic of a digitally configured capacitor is the same as that of the other capacitors, but is almost the same. In one aspect, the semiconductor dimensions of the capacitor are scaled, resulting in a near binary weighted capacitance. In another aspect, the characteristic of the at least two capacitors is a predetermined very small increment by which the capacitance difference between the two capacitors is predetermined.
In this case, the delay difference becomes very small.

The capacitive load provided at the common node of the time delay circuit constitutes the corresponding delay of the circuit. More specifically, configuring this load involves characterizing the actual delay of the circuit, selecting the digital configuration signal appropriately to change the capacitive characteristics of the circuit, and storing this selected signal in a storage device. , Supply the selected signal to capacitors across the configuration line. This process is repeated to obtain the appropriate accuracy in the configuration. If the capacitor is a binary weighted capacitive characteristic, the digital configuration signal corresponds approximately to a binary encoding of the settable capacitance.

[0018]

1 is a block diagram of a preferred embodiment of the time delay circuit of the present invention. The time delay circuit of the present invention includes a first gate device 10, a second gate device 12, and an input terminal 14.
An output terminal 16, a common node 18, a plurality of digitally configured (digitally set) capacitors 20,
It comprises a storage device (selection circuit) 22 and a plurality of component lines 24. First and second gate devices 10 and 12
Are preferably implemented in CMOS inverters, with the sources of p-channel transistors 28 and 32 connected to voltage source Vdd and the sources of n-channel transistors 30 and 34 connected to voltage source Vss. The gates of each transistor of the first and second gate devices 10 and 12 are interconnected to form the input of each device 10 and 12. First and second gate devices 10 and 12
The drains of each transistor of the
Form 0 and 12 outputs, respectively. The first gate device 10 and the second gate device 12 are realized as CMOS inverters as shown, but either the first or second gate device 10 or 12 can be realized without departing from the spirit of the present invention. Please note that. For example, one or both of devices 10 and 12 may be implemented as buffers, which buffers are suitable for the application of interest.

The input terminal of the first gate device 10 is connected to the input terminal 1
4 and connect its output to the common node 18,
It is also coupled to the input terminal of the second gate device 12 via this node. The output terminal of the second gate device 12 has an output terminal 16
Bind to. Thus, the clock or other signal received by the input terminal 14 is supplied to the first gate device 10, propagates through it and appears at its output, from which the input of the second gate device 12 via the common node 18. Supplied on the edge. Second
A clock or other signal received at the input of gate device 12 propagates through this device 12 to its output and appears at output terminal 16.

Digitally configured capacitor 20
Comprises first and second terminals 21A and 21B by which a plurality of capacitors 20 are connected to the common node 18 and the configuration line 24. Preferably, each capacitor 20 is implemented using n-channel field effect transistors 20A, 20B, 20C and 20D.
In the case of the first embodiment shown in FIG. 7, the first of each capacitor 20
The terminal 21A is composed of the gates of the transistors 20A to 20D, and the second terminal 21B is the transistor 20A to 20D.
20D of each interconnected source and drain. In the case of the second embodiment of FIG. 8, each capacitor 20
The first terminal 21A is composed of the interconnected sources and drains of the transistors 20A to 20D, and the second terminal 21B is composed of the gates of the transistors 20A to 20D. One of the advantages of this second embodiment is that
Since the source and drain of each of the transistors 20A to 20D are shared, the die area can be reduced. Although the capacitor 20 has been implemented using n-channel field effect transistors as shown, the capacitor 20 may be implemented using p-channel field effect transistors or other digitally configured elements without departing from the spirit of the invention. You may. Further, although four capacitors 20 are shown, it should be noted that more or less capacitors 20 may be used without departing from the spirit of the invention.

The storage device 22 is coupled to the configuration line 24 and stores the digital configuration signals, provides these signals to each configuration line 24, and further to the capacitors 20 associated with that configuration line. The storage device 22 is coupled to a control bus 26 from which the storage device receives signals corresponding to digital configuration signals. This bus may be one or more lines without departing from the spirit of the invention. The storage device 22 is preferably a register, a latch,
It can be implemented using flip-flops, random access memory or other digital storage elements. When the time delay circuit is implemented as an integrated circuit, the storage device 20 is preferably configured so that the die area may be relatively small and the power consumption may be relatively small.

Configuration line 24 conveys each digital configuration signal provided by storage device 22 to each capacitor 20.
Each digital configuration signal is logic "high" or logic "low". As will be described later, the digital configuration signal sets (configures) each capacitor 20 to have substantially fixed capacitance characteristics. In such operation, the digital configuration signal sets (configures) the time delay circuit. This is common node 1
This is because the predetermined capacitive load at 8 corresponds to the desired time delay.

The corresponding gate and channel of each transistor 20A-20D form the plate of each capacitor 20, while the oxide layer between the gate and channel forms the dielectric layer of the capacitor. Although there are various factors, the usable capacitance characteristic of each capacitor 20 depends on the size of the specific transistors 20A to 20D, the parameters of the semiconductor process (doping density, the thickness of the gate oxide layer of the transistor, etc.) and the bias voltage. Decided.

The capacitance characteristic of the capacitor 20 realized by using the field effect transistor as shown in FIG. 7 is almost modeled for the inversion and depletion bias regions and is as follows.

[Equation 1] (1) CGSD is the capacitance of the gate, the source and the drain (excluding the overlapping capacitance described later), and is as follows.

[Equation 2] as well as

(Equation 3) Note that W = channel width L = channel length εox = dielectric constant of oxide gate Tox = thickness of oxide gate

(2) CGB is a gate and bulk (substrate: substrate) capacitance, and is as follows.

[Equation 4] And VGS <VT,

(Equation 5) Where D = thickness of depletion on the substrate εB = dielectric constant of the substrate

(3) CGSO is the capacitance in which the gate and the source overlap, and is as follows.

(Equation 6) It should be noted that COL is a substantially constant overlapping capacity per unit length related to the assembly layout and process.

(4) CGDO is the overlapping capacitance of the gate and drain, and is as follows.

(Equation 7) Thus, the overlapping capacitance does not depend on the bias of the transistor, while the gate-source and drain capacitance and the gate-bulk capacitance depend on the bias.

The capacitance C of the capacitor 20 realized by using the field effect transistor shown in FIG. 8 is as follows with respect to the transistor bias in the inversion and depletion regions.
It is almost characterized and is as follows.

(Equation 8) Note that (1) CGDO, CGSO and CGSD are the same as above. (2) CDB is the capacitance of the drain and the bulk, and is as follows.

[Equation 9] Note that q = electron charge NB = bulk doping concentration ΦT = voltage related to doping concentration VDB = voltage between drain and bulk (3) CSB is the capacitance of the source and the bulk, and is as follows.

[Equation 10] Note that VSB = voltage between source and bulk

Therefore, as described in the above equation, the capacitor realized by using the field effect transistor generally has a capacitance characteristic of being biased. Preferably, these capacitance characteristics are used to select the voltage levels for the logic "high" and "low" of the digital configuration signal. Typically, the logic "high" and "low" voltage levels are the values of the supply voltages Vdd and Vss.

Referring to FIGS. 9 to 12, capacitor 20
The typical capacitance characteristics of In FIG. 9 and FIG. 10, these capacitance characteristics are as shown in FIG.
And the capacitors 20 realized using n-channel field effect transistors connected to their respective configuration lines 24. FIG. 9 shows that the digital configuration signal is logic "low".
(That is, Vss), and the voltage of the node 18 is 0 to 5V
The high-capacity characteristics obtained by switching to are shown. Figure 10
The digital configuration signal is a logic "high" (ie, Vdd).
Shows the low capacitance characteristic obtained when the voltage of the node 18 is switched from 0V to 5V. 11 and 12, the capacitance characteristic corresponds to the capacitor 20 realized by using the n-channel field effect transistor connected to the node 18 and each constituent line 24, as shown in FIG. FIG. 11 shows that the digital configuration signal is a logic "low" (ie, V
ss), which shows the low capacitance characteristic obtained when the voltage of the node 18 is switched from 0 to 5V. FIG. 12 illustrates the high capacitance characteristics obtained when the digital configuration signal is a logic "high" (ie, Vdd) and the voltage at node 18 switches from 0 to 5V.

To construct a time delay circuit, not all capacitors 20 need to have the same or nearly the same available capacitance characteristics. In one aspect of this circuit, the capacitor 20 is a scaled semiconductor dimension, which results in a substantially binary weighted capacitive characteristic. As described above, the capacitance characteristic of each of the transistors 20A to 20D is
In part, it is a function of the gate area. Therefore, the gate regions of the transistors 20A to 20D are scaled to obtain the selected capacitors 20 having different capacitance characteristics. For example, assuming that the region of the transistor 20A is X, the region of the transistor 20B may be 2X, the region of the transistor 20C may be 4X, and the region of the transistor 20D may be 8X. Therefore, since the capacitance of the MOS capacitor is substantially proportional to each gate region, the transistors 20A to 20A
The relationship of each capacitance at 0D is approximately 1: 2: 4: 8.
In these capacitances, if the capacitance of the transistor 20A is "1C", the total capacitance of the capacitor 20 can be increased or decreased in steps substantially equal to 1C over a range between approximately 0C and 15C. That is, the capacitances are approximately binary weighted and the time delay configuration sets the digital configuration signal to a binary value that is encoded into the desired overall capacitance characteristic connected to the common node 18.

From another point of view, the capacitance characteristics of at least two capacitors 20 have a predetermined slight difference.
This slight difference is achieved, for example, by configuring transistors with approximately the same length but slightly different widths or with approximately the same width but slightly different lengths. By giving this small difference, a small difference occurs in the obtained capacitance, and therefore, a small change also occurs in the time delay to be performed.

Although two aspects have been described, it should be noted that the aspects of binary weighting and small difference may be combined without departing from the spirit of the invention. It should be noted that capacitor 20 may have other related capacitive characteristics other than those described above in these respects, including the same or nearly the same capacitive characteristics without departing from the spirit of the invention.

In operation, the clock signal is applied to the input terminal 1
4 and outputs from the output terminal 16. The delay is a function of the overall capacitance characteristic of the capacitor 20, the output impedance of the first gate device 10 and the switching threshold of the second gate device 12. When the output signal of the first gating device 10 is "high", the capacitor 20 charges at a rate associated with each capacitive characteristic. Also, when the output signal of the first gate device 10 is "low", these capacitors discharge at a rate associated with each capacitance characteristic. When the capacitor 20 is charged and discharged, the switching threshold of the second gate device 12 is crossed and the device 12 switches the output state. Therefore, the time delay circuit outputs the delayed clock signal.

As mentioned above, driving the digital configuration signal into a predetermined "high" and "low" logic combination sets the overall capacitance characteristic of the capacitor 20. Since the digital configuration signal is determined for each of the capacitors 20,
The corresponding capacitance characteristics of all capacitors 20 are the sum of the predetermined total capacitance characteristics corresponding to the desired delay of the clock signal propagating through this circuit. On the falling edge of the clock signal, the first gate device 10, which is preferably implemented with a CMOS inverter, provides the rising edge on the common node 18, so that the capacitor 20 charges. With respect to this clock edge, the switching threshold of the second gating device is taken into account to set the combination of the digital configuration signals supplied to the capacitor 20 so that the charging rate corresponds to the desired delay. Next, at the rising edge of the clock signal,
The first gating device 10 supplies the falling edge to the common node 18 to discharge the capacitor 20. The digital configuration signal does not change from the value set for charging the capacitor. However, since the voltage of the node 18 is "low" during the discharging period, the total capacitance characteristic of the capacitor 20 changes. Nevertheless, as is known in the art, scaling the dimensions of the transistors 28 and 30 of the first gate device causes the capacitor 20 to discharge by an amount approximately equal to the delay corresponding to the clock falling edge. The rising edge of the clock is delayed.

13-16, for example, the clock signal edge 300 received by input terminal 14 transitions between 0 and 5V and is delayed by a variable time to occur as output edge 302 at output terminal 16. To do. FIG. 13 shows eight delay amounts corresponding to various combinations of digital configuration signals when three capacitors 20 are used and these capacitors are realized by using an n-channel field effect transistor as shown in FIG. There is. In FIG. 14, the time axis is expanded,
These delays are shown in detail. FIG. 15 shows eight delay amounts corresponding to various combinations of digital configuration signals when three capacitors 20 are used and these capacitors are realized by using an n-channel field effect transistor as shown in FIG. There is. FIG. 16 shows these delays in detail by expanding the time axis. In these two sets of figures, the incremental delay (unit of change in delay) is about 0.0 each.
03 ns (nanosecond) and 0.007 ns.

The time delay circuit is configured to perform a predetermined time delay. More specifically, it characterizes the delay of the circuit for a selected combination of digital configuration signals, selects the appropriate digital configuration signal to change the capacitance characteristic of the capacitor 20 of the circuit, and stores the selected signal in the storage device 22. And the selected digital configuration signal is supplied to the capacitor 20 to configure (set) the time delay circuit.
The digital configuration signal is preferably selected external to the time delay circuit so that the storage device 22 of each circuit receives the signal corresponding to the selected digital configuration signal via the control bus 26 associated with the circuit. The storage device 22 provides a digital configuration signal on each configuration line 24 to supply the associated capacitor 20. In particular, the above construction process may be repeated in order to obtain optimum accuracy in this construction. Preferably, the capacitor load provided by the associated capacitors 20 is at or near the middle of the circuit range of capacitance, and when characterizing the capacitance characteristics of each capacitor 20, time delay characterization is performed first, so that a digital configuration is provided. With proper selection of signals, virtually any particular delay is obtained.

FIG. 17 shows a tapped delay line using a plurality of time delay circuits according to the present invention. The time delay circuit 36 is coupled in series at each coupling node 38. Further, each coupling node 38 has a plurality of taps 40.
, Each of which is associated with one of the time delay circuits 36. The delay line comprises a clock input terminal 42 which acts as an input terminal for the first delay circuit 36α. The delay line also has a clock output terminal 44 which acts as the output terminal of the final time delay circuit 36Ω. In addition, the delay line
A master control bus 46 is coupled to each of the control buses 26 associated with one of the time delay circuits 36, respectively. As shown, the master control bus 46 comprises a multi-line bus, but it should be noted that the master control bus 46 may have this configuration or another configuration without departing from the spirit of the present invention. .

In operation, when the clock signal is input to the clock input terminal 42, it propagates through each time delay circuit 36 and finally, after a predetermined overall time delay characteristic of the delay line, the clock output. The terminal 44 is reached. When the clock signal propagates through the delay line, it is delayed in each time delay circuit 36. The type of this clock signal is
A strobe signal is generated at each tap 40. Preferably,
Since the continuous strobe signals are generated at uniform time intervals, the time delays of the time delay circuit 36 are preferably equal, as described above. It should be noted that the illustrated delay line has a serial structure, and the time delays of the respective time delay circuits are preferably substantially the same, but the delay lines may have a parallel structure without departing from the gist of the present invention. . With such a parallel structure, the time delay circuit receives the clock signals in parallel and provides unequal delays. The delay of any one time delay circuit is longer or shorter than the delay of an adjacent time delay circuit by a substantially uniform predetermined increment (predetermined time).

Characterizing the delay of each time delay circuit, setting the capacitor 20 associated with each time delay circuit 36 to configure the delay, or delay line, of each such circuit,
The time interval between strobes at the tap 40 is made uniform. These two steps are repeated until the proper result is obtained.

One approach to characterize the time delay of the time delay circuit 36 is to provide a sine wave of known parameter to the clock input terminal 42 and tap it for a relatively long time, ie, a relatively large period period of its waveform. 40 to capture the sine wave data. In this way, the digital configuration signal is preferably set so that the capacitive load of each circuit is in or near the intermediate range. Each tap 4 to fit at least the square curve
The phase angle between the samples obtained at 0 is calculated. From these phase angles and based on knowledge of the sinusoidal frequency, the time delay associated with each time delay circuit 36 is determined. Moreover, since the relevant dimensions and their biases are known, the capacitance characteristics of each of the capacitors 20 can be inferred.

By determining the actual time delay, the capacitors 20 associated with each time delay circuit 36 are changed to
The time delay of each such circuit can be modified to improve the non-uniformity between the time delays. The time delay can be substantially equal to a predetermined value, for example a value derived from the frequency of the desired analog signal to be sampled.

The time delay of each time delay circuit 46 of the delay line can be achieved with other approaches without departing from the spirit of the invention. For example, characterizing the time delay circuit 36 can characterize and approximate a single time delay circuit.
This characterization allows the incremental delay (unit delay amount) associated with each combination of the digital configuration signal and the bias voltage supplied to the circuit to be determined. The incremental delay of this characterized time delay circuit is generally not equivalent to the incremental delay of other time delay circuits, but this delay is generally the delay line, especially when using an iterative process. Is sufficiently equivalent to the possible configuration of. Therefore, by characterizing one time delay circuit, it becomes the basis for configuring all the time delay circuits 36. These construction approaches can be used when adapting the delay line to a phase-locked loop that brings the total delay to a predetermined value.

The foregoing has been described with respect to a preferred embodiment of the present invention with respect to a time delay circuit and a method of constructing the same. However, without departing from the scope of the present invention, a circuit or method,
It will be appreciated that many modifications and variations are possible in both or both. Therefore, the above terms and descriptions are merely for the purpose of illustrating the invention and do not exclude equivalents to the functions illustrated and illustrated.

[0045]

As described above, the time delay circuit of the present invention has various remarkable effects. For example, the delay time of the circuit according to the invention can be configured (set) digitally, thus overcoming the difficulties associated with analog adjustment of capacitance. Furthermore, the circuit is capable of high speed operation and is itself configured to use binary techniques. These and other important effects will be apparent to those of skill in the art.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a time delay circuit including a plurality of digitally configured capacitors according to the present invention.

FIG. 2 is a block diagram of a conventional delay line composed of a plurality of serially coupled time delay circuits.

FIG. 3 is a circuit diagram of a conventional time delay circuit.

FIG. 4 is a waveform diagram illustrating an operation of the conventional time delay circuit shown in FIG.

FIG. 5 is a circuit diagram of another conventional time delay circuit including a voltage control capacitor realized by using a field effect transistor.

FIG. 6 is a circuit diagram of still another conventional time delay circuit including a plurality of switchably connected capacitors realized by using field effect transistors.

FIG. 7 is a circuit diagram of a first embodiment of the digitally configured capacitor of FIG.

FIG. 8 is a circuit diagram of a second embodiment of the digitally configured capacitor of FIG.

9 is a diagram showing a high capacity characteristic of a capacitor realized by using the field effect transistor shown in FIG.

10 is a diagram showing a low capacitance characteristic of a capacitor realized by using the field effect transistor shown in FIG.

11 is a diagram showing low capacitance characteristics of a capacitor realized by using the field effect transistor shown in FIG.

12 is a diagram showing a high capacity characteristic of a capacitor realized using the field effect transistor shown in FIG.

FIG. 13 is a diagram showing increments in delaying edges of a clock signal using a capacitor realized as shown in FIG. 7.

FIG. 14 illustrates details of the incremental delay shown in FIG.

FIG. 15 is a diagram showing increments in delaying edges of a clock signal using a capacitor realized as shown in FIG.

16 is a diagram showing details of the incremental delay shown in FIG. 15. FIG.

FIG. 17 is a block diagram of a tapped delay line using a plurality of time delay circuits according to the present invention.

[Explanation of symbols]

 10 First Gate Device 12 Second Gate Device 14 Input Terminal 16 Output Terminal 18 Common Node 20 Capacitor 22 Storage Device (Selection Circuit) 24 Configuration Line 26 Control Bus

Front Page Continuation (72) Inventor Benjamin J. McCarroll Oregon, USA 97229 Portland North West Andrew Place 1736

Claims (3)

[Claims] 1. A first gate device having an input end and an output end, and at least one first gate device having a first terminal and a second terminal, respectively, the first terminal being connected to the output end of the first gate device. A digitally settable capacitor, and a selection circuit coupled to the second terminal of the capacitor for supplying at least one digital configuration signal to the capacitor to set the capacitance characteristic of the capacitor. A time delay circuit characterized by delaying and propagating a signal supplied to an end. 2. A method of delaying a signal by a predetermined amount, the signal being supplied to an input of a first gate device, and a plurality of digitally settable capacitors being provided to an output of the first gate device. A time delay method characterized in that the capacitors are connected to each other so that the total capacitance characteristic is changed, and the respective capacitance characteristics are set to change the delay. 3. A plurality of first gate devices each having an input terminal and an output terminal, a plurality of second gate devices each having an input terminal and an output terminal, a first terminal and a second terminal respectively, and a digital circuit. And a plurality of common nodes connected to one output terminal of the first gate device, one input terminal of the second gate device, and a first terminal of the capacitor, respectively. And a selection circuit coupled to at least one second terminal of the capacitor for providing at least one digital configuration signal to at least one of the capacitors so as to set at least one capacitance characteristic of the capacitor. Data acquisition device equipped with.