JPH084168B2 - Optical semiconductor element drive circuit - Google Patents

Description

The present invention relates to an optical semiconductor element drive circuit for driving an optical semiconductor light emitting element such as a light emitting diode or a semiconductor laser by using a field effect transistor, and a field effect transistor or the like has a characteristic variation. For the purpose of stabilizing the temperature characteristic of the voltage amplitude change of the input signal for keeping the optical output of the optical semiconductor element constant, the bias voltage on the input side of the field effect transistor is The temperature compensation circuit is configured to change so as to follow the temperature characteristic of the pinch-off voltage of the field effect transistor.

Further, the temperature compensation circuit is configured to also perform compensation for the temperature characteristic of the bias voltage setting circuit that sets the bias voltage.

[Industrial applications]

The present invention relates to an optical semiconductor element drive circuit that drives an optical semiconductor light emitting element such as a light emitting diode or a semiconductor laser using a field effect transistor.

[Conventional technology]

The seventh field-effect transistor (FET, the same applies hereinafter) made of gallium arsenide (GaAs) is used as a circuit for driving optical semiconductor devices that require ultra high-speed optical communication or large currents.
A drive circuit as shown in the figure has been conventionally proposed.

In FIG. 7, on the drain (D in the figure) side of FET2,
For example, one end of a semiconductor laser (LD, the same applies hereinafter) that outputs an optical output 16 is connected and the other end is grounded. A coil 8 for flowing a bias current I _B to LD1 is connected to the drain side.

The input signal v _i is input from the terminal 10 to the gate (G in the figure) side of the FET2 via the capacitor 4 for AC coupling, and
The clamp circuit 3 is connected. The clamp circuit 3 is composed of a diode 5, a capacitor 6 and a resistor 7. The cathode side of the diode 5 is connected to the gate side of the FET 2 and the anode side is connected to the capacitor 6 whose other end is grounded. The clamp voltage V _c (negative voltage) is input to the connection portion of the diode 5 and the capacitor 6 via the terminal 11. One end of resistor 7 is FE
It is connected to the gate side of T2 and has a voltage V _EE (negative voltage) at the other end.
Is applied. By the clamp circuit 3, the gate bias voltage V _G of the FET 2 is clamped to a negative voltage slightly lower than the clamp voltage V _C.

On the other hand, on the source (S in the figure) side of the FET 2, the source bias voltage Vs is input from the terminal 12 and the capacitor 9 whose other end is grounded is connected.

FIG. 8 shows characteristics of optical power with respect to the current of the LD1 driven by the driving circuit shown in FIG. 7 (generally called IL characteristics). Now, for example, when the temperature is 25 ℃
Focusing on 14, there is almost no optical power until the current reaches a predetermined threshold value, and the optical power sharply and linearly increases from the region where the current value is large beyond that. Therefore, keep flowing (I _B at 25 ° C.) in particular the bias current I _B25 as shown in FIG. 8 by a not-shown circuit coil 8 of FIG. 7, then further in a current i _P25 (25 ° C. to LD1 The light output 16 shown in FIG. 8 can be obtained by flowing i _P ).
Is obtained.

Next, when the temperature is 5 ° C., as shown in FIG.
The bias current I _B5 needs to be smaller than the bias current I _B25 for the characteristic 14 at 25 ° C. The slope of the characteristic 13 is steeper than that of the characteristic 14, so the optical output of FIG.
It is necessary to make the current i _P5 flowing through LD1 required to obtain 16 smaller than the current i _{P25 at} 25 ° C.

On the contrary, when the temperature is 50 ° C., as shown in FIG.
Bias current I _B50 must be greater than I _B25 . Since the slope of the characteristic 15 is gentler than the slope of the characteristic 14, the current i _P50 flowing through the LD1 required to obtain the optical output 16 in FIG. 8 needs to be larger than i _P25 .

As described above, in order to obtain the constant optical output 16 even when the temperature changes, both the bias current I _B and the current i _P controlled by the FET 2 need to be controlled according to the temperature change. Such control is called automatic light output control APC.

In order to control the bias current I _{B according} to the temperature change, a temperature compensating circuit (not shown) is connected to the coil 8 of FIG. 7 and the temperature changes, for example, 5 ° C., 25 ° C., 50 ° C. Accordingly, control may be performed so that the bias current I _B increases to I _B5 , I _B25 , and I _B50 .

On the other hand, since the current i _P is controlled by the FET2, it is necessary to study the input / output characteristics of the FET2 for each temperature. FIG. 9B is a static characteristic diagram showing the relationship between the gate-source voltage V _GS and the drain-source current I _DS of the FET 2 (FIG. 9A will be described later). As can be seen from the figure, as the temperature changes, for example, 5 ℃, 25 ℃, 50 ℃,
The slope of 0,21 (transconductance g _m ) becomes gentle.
Accordingly, the saturated drain currents I _DSS5 , I _DSS25 , I
_DSS50 (the maximum value of drain-source current I _DS when V _GS = 0) becomes small. Also, the pinch-off voltage V _P5 ,
V _P25 , V _P50 (Gate-source voltage V _GS when I _DS = 0
Value) increases in absolute value in the negative direction.

From the above characteristics, in order to obtain the current i _P5 <i _P25 <i _P50 flowing in LD1 in order to keep the optical output 16 of LD1 constant at each temperature, the characteristics at each temperature in FIG. The input signals v _i as shown in v _i5 , v _i25 , v _i50 in the figure may be given from the terminal 10 (FIG. 8) by tracing 19, 20, 21. here,
V _{Q in} the figure is a gate-source bias voltage given as the difference between the source bias voltage V _{S in} FIG. 8 and the gate bias voltage V _G set by the clamp circuit 3, and is close to the pinch-off voltage at each temperature. It is fixedly set.

From the relationship in FIG. 9 (b), the current flowing in LD1 i _P5 <i _P25 <
To obtain i _P50 , the input signals v _i5 <v _i25 <v _i50 may be given. Therefore, if a temperature compensation circuit (not shown) in which the voltage value of the input signal v _i increases as the temperature increases is connected to the terminal 10 in FIG.
Can be constant.

[Problems to be Solved by the Invention]

However, in the conventional drive circuit as shown in FIG.
The static characteristics of T2 vary greatly, and there is a FET2 having the characteristics shown in FIG. 9 (a) instead of the characteristics shown in FIG. 9 (b). In this case, as the temperature changes to 5 ° C., 25 ° C., and 50 ° C., the slopes of the characteristics 16, 17, and 18 become gentle as in FIG. 9 (b). However, each saturation drain current I _DSS5 , I
_DSS25 and I _DSS50 are larger than in the case of FIG. 9 (b), and the absolute values of the pinch-off voltages V _P5 , V _P25 , and V _P50 are smaller than those in the case of FIG. 9 (b). Therefore, at each temperature LD1
The magnitude relation of the input signals v _i for obtaining the currents i _P5 , i _P25 , i _P50 flowing in (Fig. 8) is v _i5 > v as shown in Fig. 9 (a).
_i25 > v _i50 , which is the reverse of the case of FIG. 9 (b). The gate-source bias voltage V _Q is
Both the figures (a) and (b) have a fixed value.

As shown above, the saturated drain current in FET2
Due to variations in I _DSS and pinch-off voltage V _P , the temperature characteristics of the input signal v _i to be input to the terminal 10 in FIG. 8 may be reversed in order to keep the optical output 16 of the LD1 constant. And, conventionally, it is impossible to configure a temperature compensation circuit to be connected to the terminal 10 capable of coping with such a reversal of the temperature characteristic, and it becomes impossible to perform automatic optical output control APC in LD1. It had a problem that it would end up.

In addition to this, the diode 5 of the clamp circuit 3 of FIG.
Also has temperature characteristics, the gate bias voltage V _G ,
That is, the gate-source bias voltage V _Q (see Fig. 9)
There were variations in itself, and there were problems similar to the above.

An object of the present invention is to stabilize the temperature characteristic of the voltage amplitude change of the input signal for keeping the optical output of the optical semiconductor element constant even if the characteristic variation exists in the field effect transistor or the like.

[Means for solving the problem]

The present invention uses a field effect transistor (FET, hereinafter the same) that changes an output current in accordance with a change in voltage amplitude of an input signal, and controls the optical output of an optical semiconductor element such as a semiconductor laser by the output current. It is applied to an optical semiconductor element drive circuit for performing.

The FET has a temperature compensating circuit that changes a bias voltage on the input side of the FET (for example, a gate-source bias voltage) so as to follow the temperature characteristic of the pinch-off voltage of the FET according to a temperature change. The circuit also performs compensation for the temperature characteristic of a bias voltage setting circuit such as a clamp circuit.

In order to realize each of the above operations, the temperature compensation circuit is configured by, for example, a diode having at least one temperature characteristic that drops the power supply voltage at a voltage value according to a temperature change and supplies the voltage to the bias voltage setting circuit.

[Action]

Even if the temperature characteristics of the pinch-off voltage vary from FET to FET due to variations in the characteristics of the FETs due to the above means, in the temperature compensation circuit, the bias voltage on the input side of the FETs in accordance with temperature changes causes The temperature characteristic of the voltage amplitude change of the input signal for keeping the optical output of the optical semiconductor element constant can be always kept constant by setting so as to follow.

As a result, it becomes possible to connect an automatic light output control circuit having a certain characteristic to the input side, and a stable light output can be obtained.

The temperature compensating circuit can also perform more stable temperature compensation by compensating for the temperature characteristic of the bias voltage setting circuit itself.

〔Example〕

 Hereinafter, examples of the present invention will be described in detail.

FIG. 1 is a block diagram of the first embodiment of the present invention. The basic part of the figure is the same as that of the conventional example of FIG. 7, and in addition to the terminals 31 of the clamp circuit 3, the resistors 31, 35 and the three diodes 32, 33, 34, which are the features of this example, are used. And a circuit for setting the clamp voltage V _c .

Although omitted in FIG. 7, the terminal 12 has a low voltage circuit 22 for setting the source bias voltage V _s . In the circuit 22, the terminal 12 is connected to the emitter side of the transistor 24 and one end of the resistor 23, and the other end of the resistor 23 is connected to the inverting input terminal of the operational amplifier 25 and one end of the resistor 26. The other end of the resistor 26 is connected to the output of the operational amplifier 25 and one end of the resistor 27. The other end of the resistor 27 is connected to the base side of the transistor 24. The negative voltage V _EE is applied to the collector side of the transistor 24. Further, the output of the operational amplifier 25 is connected to the capacitor 28 whose other end is grounded. On the other hand, the non-inverting input terminal of the operational amplifier 25 is connected to the ground potential and the negative voltage via the resistor 29.
The output of variable resistor 30 that divides V _EE is connected.

The operation of the first embodiment having the above configuration will be described below.

First, the characteristic of the optical power with respect to the current of LD1 is the same as that of FIG. 8 described in the section of the conventional example. Therefore, in order to obtain a constant light output 16 even if the temperature changes in LD1,
As shown in FIG. 8, the temperature, for example 5 ° C., 25 ° C., according to as high as 50 ° C., both current i _P which is controlled by the bias current I _B and FET2 to flow in LD1 via the coil 8, I
_It is necessary to control so that _B5 <I _B25 <I _B50 and i _P5 <i _P25 <i _P50 .

In order to control the bias current I _{B according} to the temperature change, the coil 8 shown in FIG. 1 is used as in the case of the conventional example shown in FIG.
In particular, a temperature compensation circuit (not shown) may be connected.

On the other hand, since the current i _P is controlled by the FET 2, the static characteristic diagram of the gate-source voltage V _GS and the gate-source current I _DS in the FET 2 in the conventional example of FIG. Add the same examination as the examination using Fig.).

FIG. 2 is the same characteristic diagram as FIG. 9, and FIGS. 2 (a) and 2 (b) show individual differences when the FET 2 in FIG. 1 has variations. Then, by using FIG. 2 (a) or (b), the input signal corresponding to the above i _P5 , i _P25 , i _P50
Although v _i5 , v _i25 , and v _i50 are _obtained , the source bias voltage V _s set by the constant voltage circuit 22 and the gate bias voltage V set by the clamp circuit 3 are different from the conventional example of FIG. 7 in this embodiment. _{In order} to make the gate-source bias voltage V _Q given as a difference from _G follow the pinch-off voltages V _P5 , V _P25 , and V _P50 at each temperature in FIG. 2A or 2B, V _Q5 , V _Q25 , V
_It is changed to _Q50 , which is a major feature of this embodiment.

As described above, by changing the gate-source bias voltage V _{Q according} to the temperature change, the pinch-off voltage V _P5 , V _P25 , V _{P50 for} each temperature, or the saturated drain current I _DSS5 , I _{Even if the DSS25} and I _DSS50 have variations as shown in FIGS. 2 (a) and 2 (b) due to individual differences in FET2 (FIG. 1), the optical output 16 in LD1 (FIG. 1) is kept constant. For the purpose of obtaining the current i _P5 <i _P25 <i _P50 flowing in LD1 for this reason, the magnitude relationship of the input signals v _i is shown in FIGS. 2 (a) and 2 (b).
We can always have v _i5 <v _i25 <v _i50 as shown in. As a result, the optical output 16 of the LD1 is controlled to be constant by connecting to the terminal 10 of FIG. 1 a temperature compensating circuit (not shown) such that the voltage value of the input signal v _i increases as the temperature increases. However, unlike the case of the conventional example of FIG. 7, the magnitude relation of the input signal v _i is not influenced by the individual difference of the FET2.

The operation of FIG. 1 for changing the gate-source bias voltage V _Q according to the temperature change as described above will be described below.

The gate-source bias voltage V _Q is given as the difference between the source bias voltage V _S and the gate bias voltage V _G as described above. Therefore, in the first embodiment of FIG. 1, the source bias voltage V _S is always a constant voltage, and the gate bias voltage V _G is changed according to the temperature change.
The gate-source bias voltage V _Q has temperature characteristics.

That is, first, in order to make the source bias voltage V _S constant, the constant voltage circuit 22 is connected to the terminal 12. Since this circuit is a general constant voltage circuit, only the outline operation will be described.

First, by adjusting the variable resistor 30, the potential of the non-inverting input of the operational amplifier 25 is determined, which causes the resistor 23
The source bias voltage V _S of the terminal 12 is determined via.

Next, if the source bias voltage V _S tries to change for some reason during operation, it is transmitted to the inverting input terminal of the operational amplifier 25, and the transistor 24 suppresses the change of V _S via the output of the operational amplifier 25. To work. As a result, the source bias voltage V _S is maintained at a constant voltage.

The capacitor 28 is an element for making the source bias voltage V _s of the FET 2 rise later than the gate bias voltage V _G when the power is turned on. That is, if there is no capacity 28,
Immediately after the power is turned on, there is a moment when both V _G and V _S become 0 V, and when the gate-source bias voltage V _Q becomes 0 V, the static characteristic diagram of Fig. 2 (a) or (b) shows that , The saturated drain current I _DSS, which is the maximum current value, flows through the FET2, and the FET2 may be destroyed. Therefore, in order to prevent this, the capacitor 28 is inserted so that V _G and V _S do not have the same potential.

By the above operation, the source bias voltage of constant potential
V _S is set.

Next, the gate bias voltage V _G is set by the clamp circuit 3 as described in the conventional example of FIG.
At this time, V _G becomes a negative voltage slightly lower than the clamp voltage V _C applied to the terminal 11. Therefore, the temperature characteristic is given to V _G by giving the temperature characteristic to the clamp voltage V _C.

That is, the ground potential and a constant negative voltage V _EE are divided by resistors 31 and 35, and three diodes 32, 33, 34 are inserted between them to obtain V _C. At this time, the diodes 32, 33, and 34 each have a temperature gradient of, for example, 1.5 mV / ° C., so that the clamp voltage V _C eventually has a temperature characteristic of 4.5 mV / ° C.

With the above operation, the gate bias voltage V _G , and consequently the gate-source bias voltage V _Q, has a temperature characteristic of 4.5 mV / ° C.

On the other hand, the temperature characteristics (gradient) of the pinch-off voltages V _P5 , V _P25 , V _P50, etc. of the FET 2 shown in FIG. 2 (a) or (b) are, for example, 3 mV / ° C. The diode 5 itself also has a temperature characteristic of, for example, 1.5 mV / ° C.

Therefore, the temperature characteristic of 4.5 mV / ° C, which is the sum of these,
As shown in FIG. 2 (a) or (b), which can be compensated by the temperature characteristics of the three diodes 32, 33, 34, the gates that follow each pinch-off voltage V _P5 , V _P25 , V _P50 well. Source-to-source bias voltages V _Q5 , V _Q25 , and V _Q50 can be obtained.

The above relationship is shown in FIG. For example, each temperature is 5 ℃, 25 ℃,
The gate bias voltage V _G is changed to V _G5 , V _C5 , V _C25 , and V _C50 by changing the clamp voltage V _C at every 50 ° C.
The gate-source bias voltage V _Q , which changes as V _G25 and V _G50, and is given as a difference from the constant source bias voltage V _S , can be changed to V _Q5 , V _Q25 , and V _Q50. . Then, each gate bias voltage V _G5 , V _G25 , V
By giving each input signal V _i5 <V _i25 <V _i50 with reference to _G50 , the current i _P5 <i _P25 <i _P50 is obtained as the output of the FET2 as shown in FIG. 2 (a) or (b). From the relationship shown in FIG. 8, a constant light output can be obtained as the light output 16 of LD1 (FIG. 1).

Since the temperature characteristics of the FET 2 and the diode 5 vary, the number of the diodes 32, 33, 34 may be increased or decreased accordingly.

Next, FIG. 4 is a configuration diagram of a second embodiment of the present invention. Also in this embodiment, as in the first embodiment of FIG. 1, it is given as the difference between the source bias voltage V _S set by the constant voltage circuit 22 and the gate bias voltage V _G set by the clamp circuit 3. Bias voltage between gate and source V
_Q is changed to V _Q5 , V _Q25 , V _Q50 by following the pinch-off voltages V _P5 , V _P25 , V _P50 for each temperature in FIG. 2 (a) or (b).

However, in the first embodiment of FIG. 1, the source-bias voltage V _S is kept constant, and the gate-bias voltage V _G is given a temperature characteristic, so that the gate-source bias voltage
Although V _Q has a temperature characteristic, in the second embodiment shown in FIG. 4, conversely, V _G has a temperature characteristic and V _S has a temperature characteristic so that V _Q has a temperature characteristic. There is.

Therefore, the clamp voltage applied to terminal 11 in FIG.
V _C is set to a constant voltage as in the conventional example of FIG. 7, and in the constant voltage circuit 22, diodes 36, 37, 38 are connected in series to a variable resistor 30 that divides the ground potential and the constant negative voltage V _EE. There is. This diode has exactly the same function as the diodes 32, 33 and 34 of FIG. Therefore, the potential of the non-inverting input of the operational amplifier 25 has the temperature characteristic of 4.5 mV / ° C. as described above, and correspondingly, the source bias voltage V _S also has the same temperature characteristic.

The above relationship is shown in FIG. For example, each temperature is 5 ℃, 25 ℃,
By changing the source bias voltage V _S to V _S5 , V _S25 V _S50 every 50 ° _C , the gate-source is given as the difference from the constant gate bias voltage V _G determined by the constant clamp voltage V _C. Bias voltage V _Q between V _Q5 , V _Q25 , V _Q50
You can change it. Then, with reference to the gate bias voltage V _G , each input signal V _i5 <V _i25 <V
_By giving _i50 , the current i _P5 <i _P25 <i _P50 is obtained as the output of FET2 as shown in FIG. 2 (a) or (b), and from the relationship of FIG. A constant light output can be obtained.

The number of the diodes 36, 37, 38 may be determined according to the temperature characteristics of the FET 2 and the diode 5 as in the case of FIG.

 FIG. 6 is a block diagram of the third embodiment of the present invention.

In this embodiment, similarly to the second embodiment of FIG. 4, the gate bias voltage V _G is made constant, and the source bias voltage V _S is given a temperature characteristic, so that the gate-source bias voltage V _{Q becomes} 2, the operation shown in FIG. 2 is realized, and in this case, as a means for giving the temperature characteristic to the source bias voltage V _S , a constant voltage given from the terminal 41 is applied.
A Zener diode having a temperature characteristic is inserted via a resistor 40 between V _S and the source side of the FET2. This is,
By performing the same function as the diodes 36, 37, 38 of FIG. 4, the same operation as the first and second embodiments of FIGS. 1 and 4 is performed. The constant voltage V _S applied to the terminal 41 is
Although not shown in particular, it is supplied from a circuit similar to the constant voltage circuit 22 of FIG.

〔The invention's effect〕

According to the present invention, by providing the temperature characteristic to the bias voltage of the FET by the temperature compensating circuit, the temperature characteristic of the voltage amplitude change of the input signal for making the optical output of the optical semiconductor element constant can be obtained. It is possible to maintain a constant tendency regardless of the difference. As a result, it becomes possible to connect an automatic light control circuit having a certain characteristic to the input side, and a stable light output can be obtained.

Further, the temperature compensation circuit also compensates the temperature characteristic in the bias voltage setting circuit such as the clamp circuit (for example, the temperature characteristic of the diode), which enables more stable temperature compensation.

In this case, the temperature compensating circuit can be easily configured with a few diodes or the like having temperature characteristics, and can be realized at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of the first embodiment, FIGS. 2 (a) and 2 (b) are operation characteristic diagrams of the first and second embodiments, and FIG. 3 is an operation explanatory diagram of the first embodiment. FIG. 4 is a configuration diagram of the second embodiment, FIG. 5 is an operation explanatory diagram of the second embodiment, FIG. 6 is a configuration diagram of the third embodiment, and FIG. 7 is a configuration diagram of a conventional example. FIG. 8 is a characteristic diagram of an optical semiconductor device, and FIGS. 9 (a) and 9 (b) are operating characteristic diagrams of a conventional example. 1 ... Semiconductor laser (LD), 2 ... Field effect transistor (FET), 3 ... Clamp circuit, 22 ... Constant voltage circuit, 32-38 ... Diode, 39 ... Zener diode.

Front page continued (72) Inventor Yuji Miyaki 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Shun Adachi 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference Reference JP 62-2580 (JP, A)

Claims (3)

[Claims] 1. An optical semiconductor element drive circuit having a field effect transistor for controlling driving of an optical output of an optical semiconductor element by changing an output current according to a change in voltage amplitude of an input signal. An optical semiconductor element drive circuit having a temperature compensation circuit that changes a bias voltage on the input side so as to follow the temperature characteristics of the pinch-off voltage of the field effect transistor according to temperature changes. 2. The optical semiconductor element drive circuit according to claim 1, wherein the temperature compensation circuit also performs compensation for the temperature characteristic of the bias voltage setting circuit that sets the bias voltage. 3. The temperature compensating circuit is composed of a diode having at least one temperature characteristic that drops a power supply voltage by a voltage value according to a temperature change and supplies the voltage to a bias voltage setting circuit for setting the bias voltage. The optical semiconductor element drive circuit according to claim 1 or 2, wherein