JPH0837546A - Base band processor for personal digital portable telephone(pdc) and demodulation of phase-modulated signal - Google Patents

Abstract

PURPOSE: To provide a space-saving low-power base band processor to be used in a personal digital portable telephone(PDC). CONSTITUTION: This processor is provided with an integrated circuit (ASIC) 12 for a special use for at least alternately converting digitally modulated signals and analog modulated signals and the integrated circuit (DSP) 10 for a digital signal processing for digitally modulating and demodulating the digitally modulated signals and digitally demodulated signals, digitally processing the demodulated signals to voice signals and control channel signals and digitally processing the voice signals and the control channel signals to the demodulated signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a movable telecommunications unit, and more particularly to a personal digital portable telephone (PD).
Regarding C).

[0002]

2. Description of the Related Art With the increasing demand for mobile phones, new standards for mobile phones have been established. Standards such as the European Digital Standard (DSM), the United States Digital Cellular (USDC) in North America and the Personal Digital Cellular (PDC) in Japan combine digital voice signals with time division multiple access (TDMA) protocols. , This time division multiple access protocol is
The communication capacity can be increased compared to existing analog systems.

These standards are realized by both hardware and software, and software is a digital signal processing integrated circuit (digital signal pro).
processing chip (DSP), and the hardware runs on an application specific integrated circuit (ASISC). At the transmitting end, software compresses the audio signal received from a coder-decoder (CODEC), and hardware adds an error correction code and a control channel signal to the compressed audio signal, modulates this signal and compresses it. The audio signal is ready to be transmitted. At the receiving end, the hardware demodulates the received signal and separates this demodulated signal into a compressed voice signal and a control channel signal. Software then decompresses the audio signal and conveys the decompressed audio signal to the coder-decoder.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a space saving and low power baseband processor for use in a personal digital portable telephone (PDC).

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention, as set forth above, to provide a baseband processor for a personal digital mobile phone (PDC), which includes a digitally modulated signal and an analogly modulated signal. -Specific integrated circuit (ASIC) for alternately at least converting, and digitally modulating and demodulating the digitally modulated signal and the digitally demodulated signal, and the demodulated signal A digital signal processing integrated circuit (DSP) for digitally processing the audio signal and the control channel signal, and digitally processing the audio signal and the control channel signal into the demodulated signal. And a baseband processor for a personal digital mobile phone.

[0006]

In accordance with the preferred embodiment of the present invention, an effective device for use in a personal digital portable telephone (PDC) is provided. This device is a specialized integrated circuit (ASIC)
And a digital signal processing integrated circuit (DSP). This digital signal processing integrated circuit (DSP)
At least demodulates the modulated digital signal or modulates the demodulated digital signal, separates the demodulated signal into a voice signal and a control channel signal, and synthesizes the voice signal and the control channel signal for demodulation. Form a signal that has been processed.

In accordance with a preferred embodiment of the present invention, the modulated signal is phase modulated and an application specific integrated circuit (ASIC) converts the modulated digital signal into a modulated analog signal by a DA converter. And a phase discriminator (p that identifies the phase of the modulated analog signal digitally
has identifier). Preferably, the digital signal processing integrated circuit comprises at least one demodulator for demodulating the phase signal. In addition, the phase discriminator has a local oscillator that produces a signal at the operating frequency, which operating frequency is user programmable.

Further in accordance with a preferred embodiment of the present invention, an integrated circuit for digital signal processing is digitally parameterized (p
Included are control channel encoders and decoders.

Further in accordance with the preferred embodiment of the present invention,
An integrated circuit for digital signal processing is a Viterbi decoding method.
e) and per-bit projection metric
It includes an audio signal channel decoder that implements c).

In addition, according to the preferred embodiment of the present invention,
An integrated circuit for digital signal processing digitally modulates a transmitted signal and ramps the modulated signal.
ping) digital modulator.

Further in accordance with a preferred embodiment of the present invention, an integrated circuit for digital signal processing comprises a device for performing post-detection / selection, a device for performing antenna selection, and a device for selecting the two devices. Have.

According to a preferred embodiment of the invention, a device for receiving a pair of user-selected pole values arranged on the circumference of the unit circle and a sine of at least one predetermined frequency. A marginally stable filter that uses the values of the pair of poles to generate a wave.
and a display tone generator including table filters).

According to a preferred embodiment of the invention, a demodulator formed by a hard limiter, a reference binary signal generator and a digital phase determining unit is provided. The hard limiter converts the analog phase-modulated input signal into a binary signal. The reference binary signal generator outputs a reference binary signal having a frequency substantially equal to the frequency of the input signal. Since the input signal is converted into a binary signal in the same way as the reference signal, the phase determination unit operates digitally and
The phase difference between the phase-modulated input signal and the reference binary signal is obtained during the sampling period.

In addition, according to the preferred embodiment of the present invention,
The digital phase determination unit comprises: a) an XOR gate indicating a time when the phase-modulated input signal and the reference binary signal have equal values; and b) a generator of a clock signal having a frequency higher than said input signal. , C) with first and second counters. The first counter has a first counter and a second counter.
The ST-COUNT signal having the edge of
Of the first counter, wherein the output of the XOR gate is positive.
The number N1 of clock pulses between the second edge and the second edge is counted.

Furthermore, according to a preferred embodiment of the present invention, the phase determination unit also includes a phase shift calculator for determining the phase difference from the number N1 of clock pulses.

Further in accordance with a preferred embodiment of the present invention, the demodulator also includes a phase shifting unit for shifting the phase of the binary signal to generate a phase shifted reference binary signal. The phase shift unit may be formed by an inverter, and the output of this inverter is connected to a divider for dividing the frequency of the binary reference signal into two.

In another preferred embodiment of the invention, the digital phase determining unit comprises a second XOR which indicates when the phase modulated binary signal and the phase shifted binary reference signal have the same value. And a third counter for counting the number N2 of clock pulses between the first edge and the second edge where the output of the second XOR gate is positive. In this embodiment, the phase shift calculator determines the phase difference from the number N1 of clock pulses,
The sign of the phase difference is determined from the number N2 of clock pulses.

According to a preferred embodiment of the present invention, a method of demodulating a phase modulated signal is provided. This method
The steps carried out by the demodulator components described above.

[0019]

The present invention will be more fully understood and appreciated from the detailed description set forth below with reference to the accompanying drawings.

FIG. 1 illustrates a block diagram of a movable telecommunications unit. 2 and 3 illustrate block diagrams of a baseband processor forming part of the telecommunications unit of FIG. Here, the baseband processor is constructed and operates according to the preferred embodiment of the present invention.

The movable telecommunications unit includes a speaker 2 for inputting a voice signal, a microphone 3 for outputting a voice signal, a coder / decoder (CODEC) 4, and an audio input signal received from the coder / decoder. A baseband processor 5 for processing audio output signals and for performing baseband modem processing, and a radio frequency / intermediate frequency (R) connected to at least one antenna 7 for transmitting and receiving processed audio signals.
F / IF) module 6 and baseband processor 5
And a host processor 8 for controlling the operation of.

The baseband processor 5 is formed of a digital signal processing integrated circuit (DSP) 10 and an application specific integrated circuit (ASIC) 12, and most of the operation of the block diagram of FIG. The digital signal processing integrated circuit (DSP) 10 is executed based on the above.

The baseband processor 5 has at least two operation paths, namely, a transmission path 14 for outputting a signal,
A reception path 16 for inputting a signal. The present invention is
It is described as part of a specific example of the SC standard RCR STD-27B, which RCR STD-27B is hereby incorporated by reference. It will be understood from the following description that the principles of the present invention are well suited to other standards.

Digital signal processing integrated circuit (DSP) 1
Within 0, the transmission path 14 is provided with μ
Low linear converter (μ-law liner
converter) 20 and a VOX switch (voi)
ce operated switch (VSELP) 23 and related VSELP (vector sum exited)
linear prediction) compressor 22
An audio channel encoder 24, a control channel encoder 26, and a formatter.
r) 28 and a scrambler 30
And a modulator 32. Application specific integrated circuit 12
Inside, the transmission path 14 has two DA converters 34.

If the compandor compresses or compands the audio signal from the microphone 2, μ low
The linear converter 20 converts the compressed or expanded audio signal into a linear audio signal. The VSELP compressor 22 compresses the audio signal and, when specified by the VOX 23, removes the non-noise part from the audio channel encoder 2
Communicate to 4. Audio channel encoder 24 encodes the compressed audio signal and control channel encoder 26 encodes the control signal received from the host processor (not shown). Formatter 28
Receives the encoded signals transmitted from the encoders 24 and 26 and provides the encoded signals with synchronization words, color codes, pre-amble words, and post-codes.
Amble Word (post-amble word)
Format information 28 such as s) is added. A scrambler 30 scrambles the formatted signal so that it will not be easily disturbed by the transmitted signal having a balanced spectrum. Modulator 32 digitally modulates the scrambled signal based on phase modulation used in generally mobile telecommunications systems.

The DA converter 34 of the ASIC 12 converts the modulated signal into an analog signal, and the analog signal is converted into an RF / IF (radio frequency / intermediate frequency) module 6
To communicate.

Within the ASIC 12, the receive path 16 includes at least one phase sensor 40, a signal selector 42 to which a timing control unit 43 is connected, and a signal indication (RSSI) signal indicating the strength of the received signal. And an AD converter 44 that outputs a digital value for. The ASIC 12 includes a portion 46 of an automatic frequency control (AFC) unit, as described in more detail below,
It also has a DA converter 47 associated therewith.

As will be described in more detail below with reference to FIGS. 8-15, the phase sensor 40 outputs a phase for sampling the input phase modulated signal and forms part of the demodulator. When designated by the timing unit 43, the selector 42 has two input RSs.
One of the SI signals is selected, and the selected signal is converted into a digital signal by the AD converter 44.

In the DSP 10, the reception path 16 has an AF
A second part 49 of the C unit, at least one demodulator 50, an RSSI comparator 51 and a descrambler 52.
, Deformatter 54 and audio channel decoder 5
6, a control channel decoder 58, a VSELP expander 60, a display tone generator 62, and a .mu.-low linear converter 64 provided as desired.

Demodulator 50 includes a second demodulator 50, as will be described in more detail below with reference to FIGS.
Forming part. The demodulator 50 demodulates the phase value into a symbol signal represented by the phase value. Descrambler 5
4 descrambles the symbol signal. The deformatter 54 extracts the format information from the descrambled signal, processes the format information, and transmits the result to the host processor 8. The deformatter 54 further separates the descrambled signal into an audio channel and a control channel, which are decoded by a decoder 56 and a decoder 58, respectively. The control signal is transmitted to the host processor 8, and the VSELP-compressed voice signal is VSE.
It is transmitted to the LP stretcher 60. The expanded audio signal is
If desired, it is transmitted to the μ-low linear converter 64, and the audio signal converted by the converter 64 is transmitted to the coder / decoder (CODEC) 4. If, instead of or in addition to voice, a display tone is desired, the tone generator 62 outputs the desired tone, which is added to the expanded signal by the VSELP expander 60, followed by a μ low. Converted as desired by the linear converter 64.

The modulation of the voice signal and the control signal is performed by the DSP 10.
It can be seen that most of the demodulation of the audio signal and the control signal is performed by the DSP 10. In addition, the DSP 10 will display the tones generated.

VOX 23 comprises any suitable voice detector. The VSELP compressor 22 performs VSELP compression, and performs a codebook search using a plurality of codebooks based on the RCR / STD-27B standard. The encoded signal is then transmitted to the search channel encoder 24.

The VSELP decompressor 60 decompresses the compressed audio signal using a codebook equal to that of the VSELP compressor 22 when the compressed audio signal is input, and outputs the audio signal.

The display tone generator 62 includes a marginally stable digital filter.
digital filter) is provided. The user selects a desired pair of poles arranged on the circumference of the unit circle. This marginally stable digital filter produces a sine wave of the required frequency. A marginally stable digital filter and two poles can produce the most audible tones, and a marginally stable digital filter can combine the two tones (dual tone multi-frequency).
ncy: DTMF) tones can be generated).

The audio channel encoder 24 is a VSE
The signal compressed by the LP compressor 22 is encoded. The audio channel decoder 56 performs the reverse operation of the audio channel encoder. The operation of the audio channel encoder and audio channel decoder is illustrated in FIGS. 4 and 5, respectively. VSELP as known to those skilled in the art and as defined in standard RCR-27B.
The data is divided into class 1 and class 2 data formats.

To encode the audio, first, V
A cyclic redundancy code (CRC) for the most important part of the SELP data is calculated (step 80), and this cyclic redundancy code is class 1 of the VSELP data.
Concatenated to the bits of. In step 82, convolutional encoding is performed.
coding, the bits of class 1 and the cyclic redundancy code are encoded, and then the convolutionally encoded data and the bits of class 2 of the VSELP data are interleaved (step 8).
4). The operation principle of steps 80 to 84 is as follows.
The outline is described in the standard RCR STD-27B, and 1
McGraw Hill in 979 (McGraw Hill)
"P by Andrew J. Viterbi and Jim Kay Omura", published by
rinciples Digital Communi
"Cation and Coding", which is hereby incorporated by reference.

For decoding, each segment of data is first deinterleaved (step 8).
6) Then, error correction is performed only on the bits of class 1 by the decoding method of Viterbi (step 88). The decoding method of Viterbi is based on the above-mentioned "Principles of Digital Co".
This decoding method is implemented on the DSP 10, thus eliminating the prior art hardware limitations on word length and decoder memory length.

The Viterbi decoding method is based on the soft metric calculation.
This soft metric calculation is performed on a bit-by-bit basis according to the invention, rather than on a symbol-by-symbol basis as in the prior art. In the present invention, the near maximum likelihood metric (nearlyma) is used.
ximum likelihood metric) is used for each bit.

In step 90, the CRC code concatenated with the class 1 bits is retrieved and stored to provide the CRC code.
Step 8: Decoding the code by Viterbi
It is calculated from 8 output values. In step 92, the new CRC code calculated in step 90 is compared with the stored CRC code. RCR / STD-27
If the two codes match, the segment is output to the VSELP decompressor 60, as defined in the B standard. If the two codes do not match, the segment is replaced with the attenuated value of the previous segment or the signal is muted.

In accordance with the present invention, the control channel encoder 26 and decoder 58 are parameterized and operate in response to variables transmitted from the host processor 8. These operations are equivalent to those of the audio channel encoder and decoder and are illustrated in Figures 6 and 7, respectively.

The encoder 26 receives a segment of control data from the host processor 8 and first performs a CRC calculation on this segment (step 9 in FIG. 6).
0). In step 90, the CRC seed, the CRC generator, and the vector length are given as variables. That is, the plurality of CRC codes used in the PDC unit are formed by one unit.

A CRC code is added to the segment of control data, and the resulting combined segment is divided into words of variable length and divided into rows having a variable number of words. (Step 92).

In step 94, BCH encoding is performed on each row to determine the value of the parity bit added to the row. Step 94 is given the word length, the number of words, and the type of code generator. B
CH encoding is based on R.E. Blahu, published in 1983 by Addison-Wesley.
t) "Theory and Practice"
of Error Control Codes ”, which is hereby incorporated by reference.

In step 96, interleaving is performed and the data of a plurality of rows are read as columns. In step 96, the number of words in each column and the word length are given as variables.

The channel decoder 58 performs the reverse operation of the channel encoder 26. That is, the data is reordered from rows to segments (step 104) and the CRC code is removed. CRC calculation is performed on the remaining data. Each of steps 100-106 is performed using the variables used in the encoding.

In step 108, the CRC code formed in step 106 is compared with the CRC code removed in step 104. If the two CRC codes are equal, the decoded message is transmitted to the host processor 8. If the two CRC codes do not match, the message is discarded.

Please refer to FIG. 2 and FIG. Scrambler 3
0 and descrambler 52 operate on each received signal. Scrambler 30 and descrambler 5
2 performs a bitwise logical XOR operation with the received signal and the pseudorandom bitstream as inputs.

The modulator 32 uses a DQPSK (π / 4-sh
if differential quadra
Performs true phase shift keying modulation and shaping, and in a preferred embodiment of the present invention, two FIRs (finite).
An impulse response) filter is provided. The modulator 32 outputs two modulated signals. The RF / IF modulator 6 includes a digital smoothing low-pass filter for smoothing the output signal of the modulator 32.

In accordance with the present invention, the modulator 32 also includes a digital ramp of the modulated signal.
ping). This digital lamp performs more accurately than if it were implemented as part of the radio subsystem. Further, by executing the digital lamp in the digital signal processing integrated circuit 10, the ASIC 12
The RF circuit can be simplified as well as the interface between the RF and IF modulator 6.

The ramped signal is then sent to the DA converter 3
It is converted into an analog signal by 4 and transmitted to the RF / IF module 6.

Demodulation is performed by the demodulator 50 and the phase sensor 40. In accordance with the present invention and as described below, the input phase modulated signal is hard limited and the phase sensor 40 is
Determine the phase difference between the input signal and the signal generated by a local oscillator of known intermediate frequency and phase. Next, the demodulator 50 calculates the phase difference between adjacent samples and determines the symbol representing the phase difference from this phase difference. According to the invention, the intermediate frequency of the signal generated by the local oscillator can be defined by the user.

The interface between the audio signal and channel signal encoding and decoding functions and the modulating and demodulating functions is simpler than the prior art interface since all four functions are implemented within the DSP 10. Has been converted. As a result, the present invention does not use the synchronization signals (eg, clock and frame synchronization signals) that were standard in the prior art.

Only one of the two received input signals should be available at any given moment, and the choice of this signal is
It is performed based on the energy of each signal. The energy of each received Signal Strength Indication (RSSI) signal within a given time period is determined by the timing unit 43 and calculated digitally by the RSSI comparator 51 to determine the selection signal for the signal with the highest energy. The signal is transmitted to the signal selection switch 120.

The AFC unit comprising the parts 49 and 46 operates to synchronize the operating frequency with the frequency of the input signal and to compensate for the frequency error of the RF / IF modulator 6. The first portion 49 is the switch 1
It receives the modulated signal selected by 20, and determines the frequency of this modulated signal. Then the second part 46
Refines the output from the first portion 49,
The calculation result is transmitted to the RF / IF modulator 6 through the DA converter 47.

To improve the performance of channel fading, the RCR STD-27B standard specifies the use of spatial diversity. The baseband processor of the present invention has two types of diversity: post-detection / selection and antenna selection, and the user can select post-detection / selection and antenna selection. The circuits illustrated in the block diagrams of FIGS. 2 and 3 can operate for post-detection / selection. For antenna selection,
Only one RF / IF path is needed. In the antenna selection mode, only one phase sensor 40 and demodulator 50 is used. The RSSI comparator 51 seeks the antenna with the highest energy and outputs a control signal to an antenna control switch (not shown) to select the antenna with the highest energy.

It is appreciated that the DSP 10 processes the audio and control signals from the CODEC 4 and delivers them to the modulation and demodulation stage, thus simplifying the interface between the functional units.

8 and 9, a modulator formed of the phase sensor 40 and a modulator 50 are illustrated respectively. FIG. 9 illustrates another embodiment for coherent demodulation of 2PSK.

The demodulator generally comprises a reference signal generator 208,
Phase sensing unit 2 (formed from phase sensor 40)
10 and a phase shift determination unit 212. The reference signal generator 208 outputs a reference signal of the fundamental frequency of the phase-modulated analog input signal IF. The phase sensing unit 210 digitally senses the phase of the input signal IF with respect to the reference signal, and the phase shift determining unit 212.
Determines the magnitude of the phase shift and quantizes the magnitude of this phase shift to the level required for the modulation method.

That is, the M-term differential phase shift key (M-ar
y differential phase shift
With t keying (MDPSK), the phase shift between consecutive symbols is determined by subtracting two consecutive phase measurements. When coherent demodulation of the M-term differential phase shift key (MPSK) is performed, the phase shift is quantized to the L level and L = M if hard decision coding is required.

The input signal IF has two phase shift keys 2
When produced with PSK, the phase shift is quantized to two levels, 0 ° and 180 °, for hard decision output.

The reference signal generator 208 generates two (binary) square waves LO.I and LO.Q with a frequency F.IF of the input signal IF. These two signals L
The phase difference between O · I and LO · Q is 90 °.

The reference signal generator 208 includes the local oscillator 21.
6, a NOT gate 218, and two one-stage counters 220 and 222. Local oscillator 216
Generates a square wave SQ having F.LO which is twice the frequency F.IF. The one-stage counter 220 generates the reference signal LO · I by dividing the frequency of the square wave SQ by 2. Signal SQ (NO
Invert (through T-gate 218), then (counter 2
By dividing the frequency by 2 (through 22), a phase-shifted reference signal LO.Q is generated.

It is noted that if coherent modulation is applied to the input signal IF, the reference signal LO.I must be locked in phase with the signal IF.

The phase sensing unit 210 comprises a hard limiter 2 (located outside the baseband processor 5).
14 and two XOR gates 224 and 226. The hard limiter 214 limits the analog input signal IF to two values and thus produces a binary signal. A typical hard limiter consists of a comparator.

Reference signal LO · I and hard limit IF
The signal is subjected to a logical XOR operation by the XOR gate 224 to obtain the reference signal LO · Q and the hard limit IF.
The signal is subjected to a logical XOR operation by the XOR gate 226. The output signals of XOR gates 224 and 226 are transmitted to phase determination unit 212. The output signals of XOR gates 224 and 226 are respectively hard limit I
It indicates when the F signal has a binary value equal to the reference signal LO · A and when the hard limit IF signal has a binary value equal to the reference signal LO · Q.

The phase determination unit 212 includes three counters 230, 232 and 234 and a phase shift calculator 23.
6 and. The counters 230 to 234 have frequency F ·
It operates in synchronization with a clock having a frequency F · CL that is N times as high as IF.

The first counter 230 is a sampling counter that outputs an ST.COUNT signal indicating that counting should be performed. First counter 230
Reaches the count value of N, the first counter 23
0 stops the output of the signal ST.COUNT, and at this time point, sampling of data by the counters 232 and 234 is started.

When the ST COUNT signal is active, the second counter 232 counts the number N1 of clock cycles, during which the local oscillator signal has the same sign as the hard limit IF signal. N1 is IF
ST · C in which the signal and the reference signal LO · I have the same sign
Displays the percentage of time the OUNT is active. Therefore, the magnitude ab of the phase difference between the LO · I signal and the IF signal is
s (phase) is defined by the following formula.

[0069]

[Equation 1]

N1 indicates only the magnitude of the phase difference and does not indicate whether the input IF signal is the lead phase or the lag phase with respect to the reference signal LO · I. The output of the third counter 234 gives the sign of the phase difference as shown below.

The third counter 234 uses ST.COUNT.
While the T signal is active, the hard limit IF signal
The number N2 of clock cycles having a sign equal to the reference signal LO · Q is counted. For example, if the input IF signal is not phase shifted from the reference signal LO · I, N1 = N,
N2 = N / 2. When the input IF signal has a leading phase of 10%, N1 becomes 0.9N and N2 becomes 0.6N.
When the input IF signal has a delay phase of 10%, N1 is 0.9N
However, N2 becomes 0.4N. Therefore, the sign of the phase sign (phase) is defined as follows.

[0072]

[Equation 2]

By using the equations (1) and (2), the phase shift calculator 36 determines the magnitude of the phase difference between the IF signal and the reference signal from the local oscillator 216 and the sign of the phase difference. decide. The sign of the phase defined by (Equation 2) is obtained by a simple method as follows.

When N = 2 ^q , the bit Dq-1 of the counter 234 becomes the sign bit.

When N <2 ^q or N> 2 ^q-1 , the value 2 ^q-1
-N / 2 is input to the counter and bit Dq-1 of the counter 234 represents the sign bit.

The demodulator must also determine the phase shift between successive samples of the IF signal. This phase shift is calculated by the phase shift calculator 236 as follows.

[0077]

(Equation 3)

Here, τ represents the time between consecutive samples, and the meaning of “modπ” is expressed by the following (formula 4).

[0079]

[Equation 4]

When different phase shift key modulations are performed, the phase difference is calculated sample by sample rather than symbol by symbol as described below.

When it is necessary to obtain an accurate value from the demodulator, the phase shift calculator 236 quantizes the output value for the phase shift based on the desired quantization level. When obtaining a rough value from the demodulator, the value of the phase difference calculated by (Equation 1) is output.

Hard limiter 214 and local oscillator 21
Since 6 produces a binary signal, it can be seen that the other parts of the demodulator components consist of digital circuits.

In order to maximize performance and minimize power consumption, the ratio of modulation bandwidth, frequency of IF and N must be optimized. Generally, the IF frequency F · I
F must be at least 5 times the modulation bandwidth. To reduce the effects of aliasing, N × F · IF should be sufficiently larger than F · IF. In order to reduce the decrease in efficiency, N is 100
Must be greater than.

It is possible to implement the invention with a low power clock operating at a clock frequency F.CL equal to N.times.F.IF / K, where K represents a positive integer greater than one. ing. In this example, the resolution of the output is N, but it requires K × IF cycles rather than one cycle to produce each sample.

If the frequency of the local oscillator is not exactly F.IF, the phase shift calculator 236 is compensated for the error resulting from the frequency mismatch and this error
a · psi) is given by the following equation.

[0086]

(Equation 5)

Here, F.LO.I is the reference signal LO.
It represents the frequency of I.

The demodulator of the present invention has also been defined so that the envelope is constant during each sampling period,
Non-constant envelope modulation (non-constant)
It can also be used to demodulate the IF signal in the envelope modulation. Examples of non-constant envelope modulation include MPSK and raised cosine shaping filters.
MDPSK formed together with the ine shaping filter).

Demodulators are also used to demodulate frequency modulated signals by approximating the instantaneous frequency. This instantaneous frequency is calculated by the phase calculator 236 by subtracting two consecutive phase measurements and dividing the result by τ.

It is further evaluated that the constituent elements used in the demodulator of the present invention have a simple structure and consume less power than the conventional demodulator.

In a 2PSK demodulator that makes an exact decision, one has to decide whether the phase shift is either 0 ° or 180 °, only the first counter 230 and the second counter 232 are used, Local oscillator 24
0 outputs a signal of frequency F · IF locked to the IF signal. This situation is illustrated in FIG.

10 to 15 are circuit diagrams of the demodulator shown in FIG. Since the circuit diagrams of FIGS. 10 to 15 are considered to require no other explanation, the following description will be simplified for the sake of brevity.

FIG. 10 shows the main element, "DICV CL
K ”,“ IO ”,“ TIME BAS ”and“ PH M ”
ET ”and each of these main components is
This is illustrated in detail in FIGS. 11, 12, 13, 14 and 15. The input signal of the circuit of FIG. 10 is the hard limited signal RX.IF and the output signal is the values N1 and N2. That is, hard limit 214 and phase shift calculator 236 are not illustrated in FIGS. The integrated circuit for digital signal processing arranged outside the circuit of FIGS. 10 to 15 serves as the phase shift calculator 236.

The component "DIV.CLK" outputs the clock signal for the entire modulator. The component “IO” serves as the reference signal generator 208. Component "TIME
BAS "is equal to the first counter 230 and generates the signal SD.COUNT. Component" PH.ME ".
T ″ is the XOR gates 224 and 226 and the counter 2
Acts as 32 and 234.

It will be clear to the person skilled in the art that the present invention is not limited to the embodiments illustrated and described thus far. The technical aspects of the present invention are defined only by the appended claims.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a movable telecommunications unit.

2 is a block diagram of a baseband processor constructed and operative in accordance with a preferred embodiment of the present invention useful for use in the telecommunications unit of FIG.

3 is a block diagram of a baseband processor constructed and operative in accordance with a preferred embodiment of the present invention useful for use in the telecommunications unit of FIG.

FIG. 4 is a flowchart showing an operation of audio channel encoding.

FIG. 5 is a flowchart showing an operation of audio channel decoding.

FIG. 6 is a flowchart showing an operation of control channel encoding.

FIG. 7 is a flowchart showing an operation of control channel decoding.

FIG. 8 is a schematic diagram of a low power digital demodulator effective for use in the baseband processor of FIG.

9 is a schematic diagram of an embodiment of the demodulator of FIG. 8 useful for demodulating two PSK modulated signals.

FIG. 10 is a circuit diagram for implementing the digital demodulator of FIG.

FIG. 11 is a circuit diagram of components of the digital demodulator of FIG.

12 is a circuit diagram of components of the digital demodulator of FIG.

13 is a circuit diagram of components of the digital demodulator of FIG.

FIG. 14 is a circuit diagram of components of the digital demodulator of FIG.

FIG. 15 is a circuit diagram of components of the digital demodulator of FIG.

[Explanation of symbols]

2 speaker 3 microphone 4 coder / decoder (CODEC) 5 baseband processor 6 radio frequency / intermediate frequency (RF / IF) module 7 antenna 8 host processor 10 digital signal processing integrated circuit (DSP) 12 application-specific integrated circuit (ASIC) ) 14 transmission path 16 reception path 20 μ low linear converter 23 VOX switch 22 VSELP compressor 24 voice channel encoder 26 control channel encoder 28 formatter 30 scrambler 32 modulator 34 DA converter 40 phase sensor 42 signal selector 43 timing control unit 44 AD converter 46 Part of automatic frequency control (AFC) unit 47 DA converter 49 Second part of AFC unit 50 Demodulator 51 RSSI ratio 52 descrambler 54 deformatter 56 voice channel decoder 58 control channel decoder 60 VSELP expander 62 display tone generator 64 μ low linear converter 120 signal selection switch 208 reference signal generator 210 phase sensing unit 212 phase shift determination unit 216 Local oscillator 218 NOT gate 220, 222 one-stage counter 230, 232, 234 counter 236 phase shift calculator 240 local oscillator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Delon Rainish Tel Aviv Ushshkins Treat 64, Israel 64 (72) Inventor Over Elaza, Tel Aviv Kehirat Worthaw Street, Israel 36 (72) Inventor Jonah Lechetz Kiri, Israel Atheim Izzic Manger Street 17 (72) Inventor Omley Pais Tel Aviv Benshaprut Street 15 Israel

Claims (27)

[Claims] 1. A baseband processor for a personal digital mobile phone (PDC), which is an application specific integrated circuit for alternating at least conversion of a digitally modulated signal and an analogly modulated signal. (ASIC) for digitally modulating and demodulating the digitally modulated signal and the digitally demodulated signal, and digitally processing the demodulated signal into an audio signal and a control channel signal. And a digital signal processing integrated circuit (DSP) for digitally processing the voice signal and the control channel signal into the demodulated signal, a baseband processor for a personal digital mobile phone. 2. The digitally modulated signal comprises:
A phase-modulated signal, wherein the application-specific integrated circuit converts the digitally modulated signal into an analog signal, and a phase that digitally determines the phase of the analog modulated signal The baseband processor for personal digital mobile phones of claim 1, further comprising a determiner. 3. The integrated circuit for digital signal processing comprises:
The baseband processor for personal digital mobile phones of claim 2, comprising at least one demodulator for demodulating the phase signal. 4. The reference voltage generating means for outputting a binary reference signal having a first frequency, said at least one demodulator operating during a sampling period, and second during said sampling period. 4. A personal digital mobile phone as claimed in claim 3, characterized in that it comprises digital means for determining the phase difference between the hard-limited phase-modulated input signal with the frequency and the reference binary signal. Baseband processor. 5. The personal digital cellular phone of claim 2, wherein the phase determiner has a local oscillator with an operating frequency, the operating frequency being user programmable. Baseband processor. 6. The digital signal processing integrated circuit comprises:
The baseband processor for personal digital mobile phones of claim 1, further comprising a digitally parameterized control channel encoder and decoder. 7. The personal digital mobile phone of claim 1, wherein the integrated circuit for digital signal processing further comprises an audio channel decoder for implementing the Viterbi decoding method and the per-bit projection metric method. Baseband processor. 8. The integrated circuit for digital signal processing comprises:
The baseband processor for personal digital mobile phones of claim 1, further comprising a digital modulator for digitally modulating a signal to be transmitted and ramping the modulated signal. 9. The baseband processor for personal digital mobile phones of claim 8, wherein the digital modulator comprises a finite pulse response filter. 10. The digital signal processing integrated circuit has means for performing post-detection / selection, means for performing antenna selection, and means for selecting the two means. The baseband processor for personal digital mobile phones according to claim 1. 11. Means for receiving a set of user-selected pole values, arranged on the circumference of a unit circle, and generating at least one sine wave of a predetermined frequency, The baseband processor for personal digital mobile phones of claim 1, further comprising a display tone generator having a limit stable filter using the set of extreme values. 12. Means for receiving a pair of user-selected pole values, arranged on the circumference of a unit circle, for generating a sine wave of at least one predetermined frequency. And a limit stable filter using the pair of pole values. 13. A hard limiter for generating a phase-modulated binary signal from a phase-modulated analog input signal having a first frequency, and a second frequency substantially equal to the first frequency. Reference voltage generating means for outputting a reference binary signal, and a phase difference between the phase-modulated signal and the reference binary signal, which operates during the sampling period and during the sampling period. A digital means for operating the demodulator. 14. An XOR gate for indicating when the digital means has a binary value where the phase-modulated signal and the reference binary signal are equal to each other, and a third higher than the first frequency. A clock having a frequency of, a first counter and a second counter, the first counter outputting a signal ST COUNT having a first edge and a second edge, A second counter is connected to the first counter, where the output of the XOR gate is positive.
14. The demodulator according to claim 13, wherein the number N1 of clock pulses between the second edge and the second edge is counted. 15. The digital means further comprises a phase shift calculator for determining the phase difference from the number N1 of the clock pulses.
The demodulator described in. 16. A phase shift unit for phase-shifting the reference binary signal to generate a phase-shifted reference binary signal.
The demodulator described in. 17. The divider, wherein the reference binary signal has a frequency twice the first frequency, and the phase shift unit divides the second frequency of the reference binary signal into two. 17. The inverter is connected to the subsequent stage of the inverter.
The demodulator described in. 18. A second XOR gate for indicating when the digital means has a binary value where the phase modulated signal and the phase shifted reference binary signal have equal binary values, 3. A third counter for counting the number N2 of clock pulses between the first edge and the second edge where the output of the two XOR gates is positive. 16. The demodulator according to 16. 19. The digital means further comprises a phase shift calculator for determining a phase difference from the number N1 of clock pulses and a sign of the phase difference from the number N2 of clock pulses. The demodulator according to claim 18, characterized in that 20. The demodulator according to claim 19, wherein the phase shift calculator further comprises means for determining a phase shift between successive sampling periods of the input signal. 21. A method for demodulating a phase-modulated signal, the method comprising hard-limiting a phase-modulated analog input signal having a first frequency to generate a phase-modulated binary signal, 2 having a second frequency approximately equal to the first frequency
A step of generating a binary reference signal, and a step of digitally determining a phase difference between the phase-modulated binary signal and the reference binary signal during one sampling period. A method of demodulating a modulated signal. 22. The step of digitally determining includes adding X to the phase-modulated binary signal and the reference binary signal.
The output of the process of performing the OR operation and the process of performing the XOR operation is positive.
22. A method of demodulating a phase-modulated signal according to claim 21, comprising the step of counting the number N1 of clock pulses between the first edge and the second edge of the OUNT signal. 23. The method of claim 22, wherein the step of digitally determining further comprises the step of determining a phase difference from the number N1 of clock pulses. 24. The method of claim 21, further comprising the step of phase shifting the reference binary signal and generating a phase shifted reference binary signal. 25. The step of digitally presenting further comprises the step of performing an XOR operation on the phase-shifted binary signal and the phase-shifted reference binary signal, and the step of performing the XOR operation. 25. Phase-modulated according to claim 24, further comprising: counting the number N2 of clock pulses between the first edge and the first edge, the output of which is positive. A method of demodulating a signal. 26. The step of determining digitally further comprises the step of determining a phase difference from the number N1 of the clock pulses and the step of determining a sign of the phase difference from the number N2 of the clock pulses. A method for demodulating a phase-modulated signal according to claim 25. 27. The digitally determining step further comprises the step of determining a phase shift between successive sample periods of the input signal.
7. A method for demodulating a phase-modulated signal according to item 6.