JPH0836895A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit device in which a speed of read-out operation of a memory is increased, pulse generating timing deciding a read-out operation time shortened accompanied by increase of read-out operation speed is made easily adjustable, and stable read-out operation can be performed. CONSTITUTION:This device is constituted so that a gate potential of an N type MOS 10 being a switch for previously charging a sense amplifier 3 and a data line 2 falls to a fixed potential from a Vcc potential. And generation timing of a pulse generated at when read-out operation from a dummy memory section 17 and a dummy sense amplifier section 18 having the same circuit constitution as a memory section 1 and the sense amplifier section 3 is finished is made adjustable by making capacitor CM of a dummy data line 19 variable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular, it is effective when applied to a circuit for performing a read operation of a semiconductor memory device.

[0002]

A conventional ROM (R ead O nly M emory ) and,
RAM with (R andom A ccess M emory) semiconductor memory device or the like, using the fact that the voltage generated between the source and drain of the MOS transistor inserted in series in the path of the memory current changes according to the magnitude of the memory current Then, a sense amplifier of a system for discriminating "1" or "0" of data is used. FIG. 5 shows a circuit diagram of the sense amplifier, and FIG. 6 shows a timing chart showing its operating state. The initial value of the gate voltage of the N-type MOS 45 inserted in series in the memory current path is the ground potential. The N-type MOS 45 plays a role of a switch when the data line 36 is precharged. The gate electrode of the N-type MOS 45 is connected to the output of an inverter 38 including a P-type MOS 39 driven by a sense amplifier control signal 50 and an N-type MOS 40 having a data line 36 connected to the gate electrode. When the sense amplifier control signal 50 changes from “Hi” to “Lo”, the sense amplifier is activated and the P-type MOS 39 is turned on, so that the gate potential of the N-type MOS 45 starts rising from the ground potential and the data line 36. To start precharging. At the same time, the potential of the data line 36 also rises and becomes stable when the current driving capabilities of the P-type MOS 39 and the N-type MOS 40 of the inverter 38 become equal, and the current driving capability of the N-type MOS 45 becomes maximum. Soon after this time, the precharge of the data line 36 is completed, and the data can be read. When the current flowing through the data line 36 is small, the threshold voltage of the memory cell is high. In that case, the node B is a P-type M
Precharged by OS44 and the potential rises, V2
Reach the potential. When the current flowing through the data line 36 is large, it means that the threshold voltage of the memory cell is low. In that case, the node B becomes lower than the former and becomes the V1 potential. Based on this potential difference, "0" or "1" of the data is discriminated.

In the memory circuit, a dummy memory section 51 and a dummy sense amplifier section 55, a normal memory section 35,
When the read operation is completed by utilizing the fact that it is formed in the same manufacturing process as the sense amplifier section 37 at the same time and has the same operation characteristic, the pulse signal 59 indicating the completion of the read operation of the sense amplifier is generated. This pulse signal 59 terminates the sense amplifier operation when the read operation of the dummy memory section 51 and the dummy sense amplifier section 55 is completed, even if the sense amplifier control signal 50 is in the selected state, and suppresses power consumption. . FIG. 6 shows a timing chart of the operation of the conventional memory circuit. Dummy sense amplifier 5
The time from the start of precharging of No. 5 to the generation of a pulse is composed of the precharge time of the dummy data line 52 and the pulse generation delay time so as to match the preset read operation time t3 of the memory unit 35 and the sense amplifier unit 37. Is set to. The read operation time t3 is set including a fixed time margin in order to stabilize the read operation. Therefore, in order to earn a margin, for example, a P-type MO
The pulse generation delay time is set by, for example, reducing the current drive capability of S58.

Incidentally, the fact that the voltage generated between the source and drain of the MOS transistor inserted in series in the memory current path changes depending on the magnitude of the memory current is used to make the data "1""0". For the memory reading method for determining the memory, for example, "Introduction to VLSI Technology" (published by Tokyo Sales Office, Heibonsha Co., Ltd.), pages 212 to 2
It is disclosed on page 14 and the like.

[0005]

However, in the above method, the sense amplifier control signal 50 is the P-type MOS3.
Since the gate electrode of the N-type MOS 45 is raised from the ground potential after turning on 9 of the MOS transistor 9, it takes a relatively long time to complete the precharge of the data line 36. For this reason, shortening the precharge time is a major issue when increasing the read speed. Conventionally, in this circuit, in order to increase the reading speed, a method of increasing the current consumption of the inverter 38 and accelerating the rise of the gate potential of the N-type MOS 45 has been adopted. Therefore, there is a problem that the power consumption of the read operation increases.

On the other hand, the timing of the pulse generated from the dummy sense amplifier at the end of the read operation is designed to have a certain time margin so that the pulse is generated after the data output from the sense amplifier. There is. When the read operation is speeded up, the margin from data output to pulse generation is also shortened. Therefore, when an error occurs in the margin width between the design value and the actual chip, the error ratio becomes large with respect to the shortened margin. Therefore, the deviation of the timing of pulse generation has a great influence on the read operation. For example, when the pulse generation timing in the actual chip is earlier than the design value, the margin width becomes narrow, which may cause a problem of read failure. On the other hand, if the timing is later than the design value, the sense amplifier operates longer due to the wider margin width.
There is a problem that the power consumption of the read operation increases.

The present inventor has
That is, attention is paid to the fact that the time from the start of precharge of the dummy sense amplifier to the generation of a pulse consists of the precharge time of the dummy data line and the pulse generation delay time, and the precharge time is determined by the dummy data line capacitance CM and the resistance. I examined it earnestly.

Therefore, the present invention speeds up the read operation of the memory and makes it possible to easily adjust the pulse generation timing that determines the read operation time that is shortened as the read operation speeds up. It is an object of the present invention to provide a semiconductor integrated circuit device capable of achieving the above.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the sense amplifier has a circuit configuration in which the initial value of the gate potential of the N-type MOS, which serves as a switch for precharging the data line, is used as the power supply voltage, the potential is lowered to a stable potential at the start of the read operation, and the data line is precharged. The pulse generation circuit for terminating the read operation is composed of a dummy memory section and a dummy sense amplifier section having the same circuit configuration as the memory section and the sense amplifier section, and the timing for generating a pulse by increasing or decreasing the dummy data line capacitance. Is adjustable.

[0011]

The current of the MOS transistor, which becomes the precharge switch after the start of the precharge in the past, is lowered by lowering the gate potential of the MOS transistor which becomes the switch for precharging the data line of the memory section from the power supply potential to the stable potential. While the capacity increases quadratically, the maximum current capacity is obtained after the start, so that the precharge time of the data line can be shortened. Further, the pulse generation timing can be easily adjusted by increasing or decreasing the capacity of the dummy data line, so that a stable read operation can be achieved even at high speed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a ROM will be described below.

FIG. 1 is a circuit diagram showing the relationship between the memory section 1 of the ROM, the sense amplifier section 3, the dummy memory section 17 and the dummy sense amplifier section 18. The memory unit 1 is 1
The drain electrodes of a plurality of memory cells (not shown) are connected to the data line 2 of the book. Sense amplifier section 3
Is an inverter 4 connected to a power supply (Vcc) and having a P-type MOS 5 having a ground potential as a gate potential and an N-type MOS 6 having a data line 2 as a gate electrode; and a sense amplifier control signal 16 having a gate potential. P-type MOS9,
N-type MOS 1 whose output is the gate potential of the inverter 4
0, and an inverter 8 including an N-type MOS 12 having a gate potential of the sense amplifier control signal 16;
Of the N-type MOS 13 which is connected to the output part of the N-type MOS transistor 13 and has the sense amplifier control signal 16 as the gate potential. The dummy memory section 17 and the dummy sense amplifier section 18 terminate the sense amplifier operation by generating a pulse indicating the end of the read operation in the sense amplifier section 3. The generation of pulses from the dummy sense amplifier section 18 is delayed from the data output of the sense amplifier 3,
The drive capability of the P-type MOS 25 is lowered to gain a margin.

In this embodiment, the dummy memory unit 1 is provided in units of three data lines for one dummy sense amplifier unit 18.
7a, 17b, 17c are provided.

FIG. 2 is a timing chart showing the operation of the circuit diagram shown in FIG. The read operation of the sense amplifier unit 3 is started by the sense amplifier control signal 16 (φSAC). First, when the sense amplifier control signal 16 changes from "1" to "0", the P-type M of the inverter 8 is
At the same time when the OS 9 is turned on, the N-type MOS 12 and the N-type MOS 13 of the inverter 8 are turned off. On the other hand, the initial state of the P-type MOS 5 of the inverter 4 is ON, and the node A is at the power supply potential. Further, the N-type MOS 6 having the data line 2 as a gate electrode is
Is not precharged, no current flows immediately and the node A falls from the power supply potential. Therefore, N
Since the drive capability of the type MOS 10 is maximized before the P type MOS 9 is turned on, the data line 2 is immediately precharged. At this stage, the precharge of the data line 2 is completed (tp). When the current flowing through the data line 2 is small after the completion of precharge, it means that the threshold voltage of the memory cell is high. In that case, the node B is the P-type MOS 9
Is precharged by and the potential rises to reach the V2 potential. When the current flowing through the data line 2 is large, the threshold voltage of the memory cell is low. In that case, the node B
Becomes lower than the former and becomes V1 potential. Based on this potential difference, "0" or "1" of the data is discriminated.

As described above, by setting the initial potential of the node A to the power supply potential, the N-type MOS 10 serving as a switch for precharging the data line becomes the maximum immediately after the sense amplifier control signal 16 is changed. Since the drivability is obtained, the precharge time of the data line can be shortened without simply increasing the current consumption.

On the other hand, the dummy memory section 17 and the dummy sense amplifier section 18 also include the memory section 1 and the sense amplifier section 3.
The same operation is performed, but the drive capability of the P-type MOS 25 is lowered by, for example, increasing the channel length so that the pulse signal is generated with a slight margin from the data output timing of the sense amplifier unit 3. . However, since the precharge time of the sense amplifier unit 3 is shortened, the margin until the pulse generation is also shortened. Therefore,
Since the ratio of the timing deviation of the pulse generation to the shortened margin is large, it is necessary to correct the timing. In the present embodiment, in order to correct the timing deviation of pulse generation, one dummy sense amplifier 18
On the other hand, a plurality of columns, here three columns of dummy memory units 17 are provided.
a, 17b and 17c are provided. This is because the precharge time of the dummy memory unit 17 is determined by the dummy data line capacitance CM and the resistance RM, and the dummy memory units 17b and 17c of the three columns of dummy memory units are connected in the final wiring step. The pulse generation timing can be adjusted depending on whether or not the master slice unit 22 is connected to the dummy data line 19. The memory unit 1 shown in FIG.
A method of adjusting the pulse generation timing at the read time t1 (from the start of precharge to the pulse generation) will be described.
In this case, it is assumed that the dummy memory section 17b is connected to the dummy data line 19 at the design stage. The sum of the dummy data line precharge time (tdp) and the dummy sense amplifier delay time (tdl) is designed to be equal to the read time t1 of the memory section 1. However, due to, for example, the P-type MOS 25 whose driving capability is lowered in order to gain a margin until a pulse is generated, tdl
May become longer or shorter than the design value at the chip stage. In the present invention, the pulse generation timing is adjusted by increasing or decreasing the dummy data line capacitance CM by the master slice method. For example, tdl
Is longer than the designed value, in the final wiring step, the master slice section 22a of the dummy memory section 17b is changed to be insulated, and tdl is adjusted to be shorter than the designed value (ta). The generation timing can be made to substantially match the design value. On the contrary, when tdl is shorter than the design value, the final wiring step is changed to connect the master slice section 22a of the dummy memory section 17b and the master slice section 22b of the dummy memory section 17c, and tdl is changed.
By adjusting tdp to be longer by a value shorter than the design value (tb), the pulse generation timing can be made to substantially match the design value. As a result, the pulse can be generated at an appropriate timing in response to the shortening of the read time accompanying the shortening of the data line precharge time of the sense amplifier unit 3.

The operation and effect of this embodiment will be described below.

(1) At the start of reading, the gate potential of the N-type MOS that serves as a switch for precharging the data line is lowered from the power supply potential, so that the driving capability of the N-type MOS changes the sense amplifier control signal. Since it becomes high immediately after the start, the precharge time of the data line can be shortened.

(2) Since the precharge time of the data line can be shortened, the read operation time of the memory can be shortened.

(3) The pulse generation timing can be adjusted by increasing or decreasing the dummy data line capacitance of the dummy memory section and the dummy sense amplifier section that generate the pulse for ending the memory read operation.

(4) Since the pulse generation timing can be adjusted, a stable read operation can be achieved even if the memory read operation is speeded up.

(5) Since the dummy data line capacitance can be easily increased / decreased by the master slicing method or fuse cutting, TAT (turn around time) can be shortened.

(6) Since the precharge time is shortened and the pulse generation timing can be adjusted, the read time can be set almost according to the design value, and the speed and power consumption can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In the above-described embodiment, the pulse generation timing is adjusted by the master slice method, but as shown in FIG. 4, the dummy memory amplifier 27 has only one column for one dummy sense amplifier portion 291, and the dummy memory portion 27 is connected to the dummy data line 28. The dummy data line capacitance CM (drain-substrate capacitance) can be made variable by increasing / decreasing the impurity concentration of the drain region 32 of the dummy memory cell 31. In this case, the dummy memory unit 27
Since there is only one column, it is possible to adjust the pulse generation timing without increasing the area.

Of course, the pulse generation timing may be adjusted only by increasing or decreasing the dummy data line capacitance without lowering the driving capability of the dummy sense amplifier section.

The present invention can be applied to various semiconductor integrated circuit devices having a signal generating circuit as well as a ROM or RAM data reading circuit.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the precharge time of the data line can be shortened by lowering the gate potential of the MOS transistor, which serves as a switch for precharging the data line of the memory section, from the Vcc potential to a constant potential. Further, the pulse generation timing can be easily adjusted by increasing or decreasing the capacity of the dummy data line, so that a stable read operation can be achieved even at high speed.

[0030]

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a relationship between a memory unit 1 and a sense amplifier unit 3, a dummy memory unit 17 and a dummy sense amplifier unit 18 of a ROM which is an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a diagram showing a method of adjusting a pulse generation timing at a read time t1 of the memory unit 1 (from the start of precharge to the pulse generation).

FIG. 4A is a ROM showing another embodiment of the present invention.
Memory unit and sense amplifier unit, and dummy memory unit 27
And a circuit diagram showing the relationship between the dummy sense amplifier section 28,
FIG. 3B is an enlarged cross-sectional view of the dummy memory cell 31.

FIG. 5 is a circuit diagram showing a relationship between a memory section 35, a sense amplifier section 37, a dummy memory section 51, and a dummy sense amplifier section 55 of a conventional ROM.

6 is a timing chart showing the operation of the circuit of FIG.

[Explanation of symbols]

1 ... Memory part, 2 ... Data line, 3 ... Sense amplifier part, 4 ... Inverter, 5 ... P-type MOS, 6 ... N-type MOS, 7 ... Inverter output, 8 ... Inverter, 9
... P-type MOS, 10 ... N-type MOS, 11 ... Precharge output, 12 ... N-type MOS, 13 ... N-type MO
S, 14 ... Inverter, 15 ... Sense amplifier output,
16 sense amplifier control signals, 17a, 17b, 17c ...
… Dummy memory section, 18 …… Dummy sense amplifier section, 1
9a, 19b, 19c ... Dummy data line, 20 ... Dummy word line, 21 ... Dummy memory cell, 22a, 2
2b ... Master slice part, 23 ... P-type MOS, 2
4 ... N-type MOS, 25 ... N-type MOS, 26 ... Pulse signal, 27 ... Dummy memory section, 28 ... Dummy data line, 29 ... Dummy sense amplifier section, 30 ... Dummy word line, 31 ...... Dummy memory cell, 32 ...... Drain region, 33 ...... Pulse signal, 34 ...... Substrate, 35 ......
Memory part, 36 ... Data line, 37 ... Sense amplifier part, 38 ... Inverter, 39 ... P-type MOS, 40 ...
... N-type MOS, 41 ... Inverter output, 42 ... N-type MOS, 43 ... Inverter, 44 ... P-type MOS, 4
5 ... N-type MOS, 46 ... Precharge output, 47 ...
... N-type MOS, 48 ... Inverter, 49 ... Sense amplifier output, 50 ... Sense amplifier control signal, 51 ... Dummy memory section, 52 ... Dummy data line, 53 ... Dummy word line, 54 ... Dummy Memory cell, 55 ... Dummy sense amplifier section, 56 ... P-type MOS, 57 ... N-type MOS, 58 ... P-type MOS, 59 ... Pulse signal,

Claims (3)

[Claims] 1. A memory section comprising a plurality of memory cells, which stores information of "1" or "0", and a sense amplifier control signal is set to a selected state, whereby "1" or "0" is output from the memory section. By precharging the data line for transmitting the information of "" and generating a pulse after the read operation of the sense amplifier unit for reading out the information of "1" or "0" is completed, A semiconductor integrated circuit device having a pulse generation circuit for returning a sense amplifier control signal to a non-selected state, wherein the sense amplifier section is connected in series to the data line, and an initial value of a gate voltage is set to a power supply voltage. N-type MOS transistor,
A circuit system having an inverter connected to the N-type MOS transistor in series and comprising a P-type MOS transistor whose ON state and OFF state are controlled by the sense amplifier control signal, and connecting the output of the inverter to the sense amplifier output. The pulse generation circuit includes a dummy memory section and a dummy sense amplifier section having the same circuit configuration as the memory section and the sense amplifier section, and generates the pulse by increasing or decreasing the dummy data line capacitance. A semiconductor integrated circuit device characterized in that the timing of the operation is adjustable. 2. A plurality of the dummy memory units are provided for each dummy sense amplifier unit, and the dummy data line capacitance is changed by changing whether each dummy data line is connected in parallel or insulated in the manufacturing process. 2. The semiconductor integrated circuit device according to claim 1, wherein the timing of generating the pulse can be adjusted by increasing or decreasing. 3. In the dummy memory section, the drain regions of a plurality of memory cells each composed of a MOS transistor are connected to one data line connected to the dummy sense amplifier section, and the impurity in each drain region is connected. By changing the density, increase or decrease the dummy data line capacitance,
2. The semiconductor integrated circuit device according to claim 1, wherein the timing of generating the pulse is adjustable.