JPH0836883A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory being easy to use in which pre- charge timing does not disturb other commands. CONSTITUTION:When a mode set signal MS outputted from a mode set setting circuit 4 is a 'H' level, a pre-charge signal generating circuit 5 activates a pre-charge start signal for all banks other than the bank specified by a bank address signal out of pre-charge start signals P0-P7. Also, when a mode set signal MS is a 'L' level, a pre-charge signal generating circuit 5 activates only a pre-charge start signal corresponding to the bank specified by a bank address signal. Therefore, pre-charging only the prescribed bank or pre-chargeing simultaneously all other banks can be performed in accordance with the mode set signal MS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device having a plurality of banks.

[0002]

2. Description of the Related Art With the recent increase in speed of MPUs (microprocessors), DRAMs used as main memory devices
It is often said that the access time and the cycle time of (dynamic random access memory) become a bottleneck and degrade the performance of the entire system. As a countermeasure against this, in order to improve the system performance, a method of providing a high speed memory called SRAM (cache memory) between the DRAM and the MPU is adopted.
However, since SRAM is more expensive than DRAM, it is not suitable for relatively inexpensive devices such as personal computers. Therefore, it is required to improve the system performance while using an inexpensive DRAM.

As one answer to the above demand, D
There is proposed a so-called SDRAM (Synchronous Dynamic Random Access Memory) capable of high-speed access to several consecutive bits (for example, 8 bits) by synchronizing the RAM with a system clock.

The above-described SDRAM as a conventional semiconductor memory device will be described below with reference to the drawings. FIG.
0 is a block diagram showing a configuration of a main part of a conventional semiconductor memory device.

Referring to FIG. 10, the semiconductor memory device includes a precharge signal generation circuit 105, banks B10 and B11.
including. The bank B10 includes a row control circuit 106, a word driver 107, transistors Q101 to Q104,
It includes a capacitor C101, bit lines BL and / BL, a word line WL, and a sense amplifier 108. The bank B11 also has the same configuration as the bank B10.

When a precharge command is input, the banks B10 and B1 are supplied from the precharge signal generation circuit 105.
Precharge start signals P0 and P1 are output to 1. Precharge start signals P0 and P1 are banks B10 and B11
Is input to the row control circuits 106 and 116. At this time, the row related control circuits 106 and 116 send the word driver activation signals φ01 and φ11 to the word drivers 107 and 1 respectively.
17 in the inactive state, the sense amplifier activating signals φ02 and φ12 to the sense amplifiers 108 and 118 in the inactive state, and the bit line precharge signals φ03 and φ13 in the active state. . As a result, the potential of the word line WL falls and the bit lines BL and / BL are precharged to the precharge voltage Vbl level.

Next, a conventional semiconductor memory device having eight banks will be described. FIG. 11 is a block diagram showing a configuration of a main part of another conventional semiconductor memory device.

Referring to FIG. 11, the semiconductor memory device includes a precharge signal generation circuit 105a and banks B10 to B1.
Including 7. When the precharge command is input, the banks B10 to B are supplied from the precharge signal generation circuit 105a.
Precharge start signals P0 to P7 are output to 17 respectively. The banks B10 to B17 have the same configuration as the banks B10 and B11 shown in FIG. 10 and operate in the same manner, and therefore description thereof will be omitted below.

Next, the operation of the semiconductor memory device configured as described above will be described. FIG. 12 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG.

In the conventional DRAM, the row address strobe signal / RAS and the column address strobe signal / C are used.
Whereas the address signal and input data etc. were fetched and operated in synchronization with the control signal called AS,
In the SDRAM, the row address strobe signal / RA is generated in response to the rising edge of the system clock CLK.
S, column address strobe signal / CAS, address signal, data, etc. are taken in and a prescribed operation is performed. As an advantage of operating in synchronization with the system clock CLK which is an external clock as described above, it is not necessary to secure a data input / output margin due to a skew (timing deviation) of an address or the like, and the cycle time is shortened. What can be done is mentioned. Further, depending on the system, there are cases in which several consecutive bits are accessed frequently. By increasing the continuous access time in this case, the average access time can be made comparable to that of SRAM.

Referring to FIG. 12, at time T1, a control signal (row address strobe signal / RAS, column address strobe / CA) externally input in response to the rising edge of system clock signal CLK is received.
S, address signals A0 to A10, data D0 to D7, etc.)
Is taken in. The address signals A0 to A10 are provided by time-divisionally multiplexing a row address signal X and a column address signal Y. Row address strobe signal / RAS
Is in the active state of "L" at the rising edge of the clock signal CLK, the address signals A0 to A10
Are taken in as the row address signal X.

At time T4, when column address strobe signal / CAS is in the active state of "L" at the rising edge of clock signal CLK, address signals A0-A9 are taken in as column address signal Y. In response to the fetched row address signal X and column address signal Y, a row and column selecting operation in the SDRAM is performed. Row address strobe signal / RAS is "L"
After a predetermined clock period (6 clock cycles in FIG. 12) has elapsed after the falling edge, the first 8-bit data is output. After that, data is sequentially output in response to the rising of the clock signal CLK.

In the write operation, the row address signal X
Is taken in the same way as when reading data. At the rising edge of clock signal CLK, column address strobe signal / CAS and write enable signal / WE
When both are in the active state of "L", the column address signal Y is taken in, and the data D0 given at that time is taken in as the first write data. In response to the fall of the fetched row address strobe signal / RAS and column address strobe signal / CAS, SDR
Inside the AM, row and column select operations are performed. Further, the input data D1 to D7 are sequentially taken in in synchronization with the clock signal CLK, and the input data D0 to D7 are sequentially written to predetermined memory cells.

Next, the precharge operation will be described. At time T13, at the rising edge of clock signal CLK, row address strobe signal / RA
The precharge operation is started when S is "L", the column address strobe signal / CAS is "H", and the write enable signal / WE is "L". When the precharge command is input, when the address signal A10 is "L", the bank designated by the bank address signal BA is precharged, and when the address signal A10 is "H", all banks are precharged. Done. After the precharge period (2 clocks in FIG. 12), that is, at time T15, the next read / write cycle can be started.

Further, in the SDRAM, FIG. 10 and FIG.
As shown in FIG. 1, the concept of multiple banks has been introduced. This is to divide the internal memory array into a plurality of parts, activate each bank (start a word line and operate a sense amplifier), and perform precharging or the like almost independently. In the DRAM, the precharge must be performed before the access, but this operation causes the cycle time to be almost twice as long as the access time. By the way,
If the inside is divided into two banks as shown in, bank B1
If the bank B11 is precharged while 0 is being accessed, the bank B11 can be accessed without precharge time. In this way, bank B1
By alternately accessing / precharging 0 and B11, loss time due to precharging can be reduced.

Further, in the conventional SDRAM described above, a single bank precharge, which is a precharge of a predetermined bank, or a precharge of all banks is performed by setting a precharge command.

First, the single bank precharge will be described. With reference to FIG. 11, when bank B10 is in the active state, when the other banks B11 to B17 are precharged, for example, banks B11 → B12
The precharge command is input seven times individually in the order of → B13 → B14 → B15 → B16 → B17, and the precharge signal generation circuit 10 is input according to the input precharge command.
Precharge start signals P1 to P7 are output from 5a, respectively. As a result, the bank B1 in the active state
Banks B11 to B17 other than 0 are sequentially precharged. Therefore, as the number of banks increases, the number of cycles for inputting the precharge command increases correspondingly, and as will be described later, the timing at which other command input is disturbed appears.

Next, the case of precharging all banks will be described. The all-banks precharge command can be input only when the bank B10 in the active state does not start the precharge. Therefore, for all bank precharge,
When one bank is active, it loses the interleaving feature of precharging the other bank.

[0019]

As described above, the number of banks of the internal memory array of the conventional SDRAM is 4 or 8.
In the case of increasing the number above, there is a problem that the input of the precharge command interferes with the input of other commands in the precharge method of only the single bank precharge and the all bank precharge. The above problems will be described in more detail below.

13 and 14 are first and second timing charts for explaining the problems of the semiconductor memory device shown in FIG. In FIGS. 13 and 14,
This shows the timing when another bank is precharging by the conventional single precharge method while the bank B10 is in the write operation.

First, referring to FIG. 13, at time T11, input of a precharge command other than active is completed. As a result, in the bank B17 (the bank in which the precharge is performed last), the precharge period is 3
In the case of a cycle, it becomes active at time T14.

On the other hand, in the timing chart shown in FIG. 21, the write word mask command is input at times T7 and T10. What is a write word mask? D
It means that the input data of all I / Os at that time are masked (not input) by activating QM, that is, setting it to “H”. Due to the input of this write word mask command, the input of the precharge command of the banks other than the active bank takes until time T13, and the bank B17
The timing at which is activated becomes time T16. Therefore, it is delayed by two cycles as compared with the timing of FIG. As a result, in order to avoid delaying the active timing of the bank, if the priority is given to precharging the other bank during the write operation of the bank B10 (time T5 to T11), the command such as the write word mask command can be input. There was a problem of disappearing.

An object of the present invention is to solve the above problems, and an object thereof is to provide a semiconductor memory device which is easy to use and in which the precharge timing does not interfere with other command inputs.

[0024]

A semiconductor memory device according to claim 1 is provided with a plurality of banks for storing data and a plurality of banks provided corresponding to each of the plurality of banks and precharging the corresponding banks. And a control means for controlling the plurality of precharge means so as to simultaneously precharge a bank other than the bank being accessed among the plurality of banks.

According to a second aspect of the semiconductor memory device, in addition to the configuration of the semiconductor memory device according to the first aspect, the control means sets a bank other than the bank being accessed among the plurality of banks according to the mode set. A plurality of precharge means are controlled to precharge at the same time.

According to a third aspect of the present invention, in addition to the semiconductor memory device according to the second aspect, the control means decodes a bank address signal and outputs a bank designation signal, and a bank designation signal. Logic means for outputting the exclusive OR of the signal and the mode set signal designating the mode set.

According to another aspect of the semiconductor memory device of the present invention, a plurality of banks for storing data, and a plurality of precharge means provided corresponding to each of the plurality of banks and precharging the corresponding banks, And a control means for controlling the plurality of precharge means so as to precharge any of the plurality of banks at the same time in response to a bank designation signal input from the outside.

According to a fifth aspect of the semiconductor memory device of the present invention, in addition to the configuration of the fourth aspect of the semiconductor memory device, the bank designating signal includes a lower address signal input when a precharge command is input.

[0029]

In the semiconductor memory device according to any one of claims 1 to 3, the banks other than the bank being accessed can be precharged at the same time among the plurality of banks. Can be precharged.

In the semiconductor memory device according to the present invention, it is possible to precharge any one of the plurality of banks at the same time in response to the bank designation signal. Can be precharged.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An SDRAM which is a semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory device has a / R
AS, / CAS, / WE, / CS buffer 1, internal clock generation circuit 2, address buffer 3, mode set setting circuit 4, precharge signal generation circuit 5, banks B0 to B0
Including B7. Each of banks B0 to B7 includes a row control circuit 6, a word driver 7, bit lines BL and / BL, a word line WL, transistors Q1 to Q4, and a capacitor C1. Banks B0 to B7 shown in FIG. 1 and FIGS.
The banks B10 to B17 shown in (4) have the same configuration and operate in the same manner, and therefore detailed description will be omitted.

External clock signal CLK is externally input to internal clock generation circuit 2, and internal clock signal CLKI is supplied in response to external clock signal CLK input.
Output to RAS, / CAS, / WE, / CS buffer 1 and address buffer 3. / RAS, / CAS, /
The WE, / CS buffer 1 operates in synchronization with the input internal clock signal CLKI, and externally input external row address strobe / RAS, external column address strobe signal / CAS, external write enable signal / W.
E, buffer external chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / CS
WE and chip select signal / CS are output to mode set setting circuit 4 and precharge signal generation circuit 5. Address buffer 3 operates in synchronization with internal clock signal CLKI, buffers input external address signal A, outputs address signals A0-A10 to mode set setting circuit 4, and generates address signal A10 as a precharge signal. Output to the circuit 5. The mode set setting circuit 4 is
In response to the input row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, chip select signal / CS, and address signals AD0 to D10, mode set signal MS
Is output to the precharge signal generation circuit 5. The precharge signal generation circuit 5 receives the input mode set signal MS,
Precharge start signals P0 to P7 in response to the chip select signal / CS, the row address strobe signal / RAS, the write enable signal / WE, and the address signal A10.
Are output to the banks B0 to B7. When the mode set signal MS output from the mode set setting circuit 4 is activated by the above operation, the precharge signal generation circuit 5
Outputs a predetermined precharge start signal P0-P7 to each bank B0-B7, respectively, in order to control the number of banks that perform precharge at the same time.

Next, the internal clock generating circuit 2 shown in FIG.
Will be described in more detail. FIG. 2 is a diagram showing the configuration of the internal clock generation circuit.

Referring to FIG. 2, internal clock generation circuit 2
Includes a delay circuit D1, inverters G1 and G2, and a NAND gate G3. The external clock signal CLK is input to the delay circuit D1. The output of the delay circuit D1 is input to the NAND gate G3 via the inverter G1. Also,
The external clock signal CLK is input to the NAND gate G3. The output of the NAND gate G3 is the inverter G
2 is output as the internal clock signal CLKI.

With the above configuration, the external clock signal CL
The internal clock signal CLKI rises at the rise of K,
After being delayed for a predetermined time by delay circuit D1, internal clock signal CLKI falls. As a result, when the time when the external clock signal CLK becomes "H" is longer than the internal delay by the delay circuit D1, the external clock signal CLK becomes "H".
Irrespective of the time, the "H" time of the internal clock signal CLKI becomes constant.

Next, / RAS, / CAS, / shown in FIG.
The WE, / CS buffer and mode set setting circuit will be described in more detail. FIG. 3 shows / RA shown in FIG.
It is a figure which shows the structure of S, / CAS, / WE, / CS buffer and a mode set setting circuit.

Referring to FIG. 3, / RAS, / CAS, /
WE, / CS buffer 1 is a dynamic latch DL1
-Includes DL4. The internal clock signal CLKI is input to each of the dynamic latches DL1 to DL4. Further, the external row address strobe signal / RAS is input to the dynamic latch DL1, and the external column address strobe signal / CA is input to the dynamic latch DL2.
S is input, the external write enable signal / WE is input to the dynamic latch DL3, and the external chip select signal / CS is input to the dynamic latch DL4. The dynamic latches DL1 to DL4 latch each control signal input in synchronization with the internal clock signal CLKI and output it to the mode set setting circuit 4.

Next, the dynamic latch shown in FIG. 3 will be described in more detail. FIG. 4 is a diagram showing a configuration of the dynamic latch shown in FIG.

Referring to FIG. 4, dynamic latch DL
Includes PMOS transistors Q21 to Q24 and NMOS transistors Q25 to Q29.

Transistors Q21 and Q22, Q23
And Q24, Q25 and Q26, Q27 and Q2
8 are connected in parallel. One ends of transistors Q21 and Q22 receive power supply voltage V _CC . The other ends of transistors Q21 and Q22 are connected to one ends of transistors Q25 and Q26. The other ends of transistors Q25 and Q26 are connected to one end of transistor Q29. The other end of transistor Q29 is connected to the ground potential.

One ends of transistors Q23 and Q24 receive power supply voltage V _CC . Transistors Q23 and Q2
The other end of 4 is connected to transistors Q27 and Q28. Transistors Q27 and Q28 are transistor Q
It is connected with 29.

The latch signal φLE is input to the gates of the transistors Q21, Q24, Q29. The input signal Input is input to the gate of the transistor Q25. The reference voltage V _ref is input to the gate of the transistor Q28. The gates of the transistors Q22 and Q26 are the transistors Q23 and Q24 and the transistor Q2.
7 and the connection point with Q28. The gates of transistors Q23 and Q27 are connected to the connection point between transistors Q21 and Q22 and transistors Q25 and Q26. The output signal Out is output from the connection point between the transistors Q23 and Q24 and the transistors Q27 and Q28.
put is output. Transistors Q21 and Q22
An output signal / Output complementary to the output signal Output is output from a connection point between the transistors Q25 and Q26.

Next, the operation of the dynamic latch configured as described above will be described. FIG. 5 is a timing chart for explaining the operation of the dynamic latch shown in FIG. Referring to FIG. 5, when latch signal φLE rises to "H", input signal Input is latched, and output signals Output and / Output are output according to the state of input signal Input. That is, when the input signal Input is "L", the output signal Output is "L" and the output signal / Output is "H". Also, the input signal Input is "H"
In this state, the output signal Output is output at "H", and the output signal / Output is output at "L".

The mode set setting circuit will be described with reference to FIG. 3 again. Mode set setting circuit 4 is NO
R gate G11, transistor Q11, inverter G1
2, G13 and AND gate G14.

The NOR gate G11 is a control signal / RAS, / C output from the dynamic latches DL1 to DL4.
Upon receiving AS, / WE, and / CS, the NOR of these is output to the gate of the transistor Q11. Transistor Q
Address signals A0 to A10 are input to 11. The transistor Q11 is connected to the input side of the inverter G12 and the output side of the inverter G13. The output side of the inverter G12 is connected to the input side of the inverter G13. The inverter G13 uses the mode setting address signals MA0 to M
A10 is output, and the inverter G12 outputs mode setting address signals / MA0 to / MA10 complementary to the mode setting address signals MA0 to MA10. AND gate G14 is used for mode setting address signals MA7 to MA.
Upon receiving 10, the mode set signal MS is output.

With the above structure, when the external row address strobe signal / RAS, the external column address strobe signal / CAS, the external write enable signal / WE, and the external chip select signal / CS are activated (state of "L"). Address) AD by the inverters G12 and G13 that form the latch circuit.
0 to AD10 are latched, and in the case of this embodiment, when the address signals AD7 to AD10 are "H", the mode set signal MS is output at "H", and in other cases, the mode set signal MS is "L". Is output with. Mode setting is performed by the above operation, and precharge control is performed using the mode set signal MS output from the mode set setting circuit 4 as described later.

Next, the precharge signal generating circuit shown in FIG. 1 will be described in more detail. FIG. 6 is a diagram showing the configuration of the precharge signal generation circuit shown in FIG.

Referring to FIG. 6, precharge signal generating circuit 5 includes a bank address decoder BAD, EXOR gates G30 to G37, NAND gate G38, AND gates G40 to G48, and OR gates G50 to G57.

Bank address decoders BAD are supplied with bank address signals BA0-BA2 for designating a desired bank from a plurality of banks. The bank address decoder BAD receives the input bank address signal B
Decodes A0 to BA2 and outputs bank designation signal bank0
~ Bank7 is output to the EXOR gates G30 to G37. The mode set signal MS is input to the EXOR gates G30 to G37. The NAND gate G38 has a chip select signal / CS and a row address strobe signal / R.
AS and write enable signal / WE are input respectively. The output signal of the NAND gate G38 is the AND gate G
40 to G48. EXOR gates G30 to G
The output signals of 37 correspond to the corresponding AND gate G40.
Is input to G47. Address signal A10 is input to AND gate G48. AND gates G40 to G47
Output signals of the corresponding OR gates G50 to G5.
Input to 7. AND gate G4 for G50 to G57
8 output signals are input. OR gates G50 to G57
Is a precharge start signal P corresponding to each bank
Outputs 0 to P7.

With the above configuration, the mode set signal MS
Is "H", all precharge start signals of banks other than the banks designated by the bank address signals BA0 to BA2 are activated. On the other hand, the mode set signal M
Bank address signal BA input when S is "L"
Only the precharge start signal of the bank designated by 0 to BA2 is activated. When the address signal A10 is "H" at the time of inputting the precharge command, the precharge start signals P0 to P7 of all the banks are activated.

Next, the operation of the semiconductor memory device configured as described above will be described. FIG. 7 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG.

Referring to FIG. 7, at time T1, mode setting is performed. As described above, the mode set is to activate the external chip select signal / CS, the external row address strobe signal / RAS, and the external write enable signal / WE at the rising edge of the external clock signal CLK, and at that time, That is, the mode such as burst length is switched by the applied address signal A. In this embodiment, the mode set is used to set the mode in which the precharge of a plurality of banks is started at one time.

Next, at time T2, bank B0 is activated, at time T3 a write command is input to bank B0, and data is written with a burst length of 8. Next, at time T4, a precharge command is input. At the time of inputting the precharge command, bank address signals BA0-BA2 designate bank B0.
Due to the above mode set, the precharge command in this case is not the bank B0, that is, the bank B1.
Precharge of 7 banks B7 is started at the same time. Therefore, after the precharge period elapses, that is, after time T5, banks B1 to B7 can be activated.

As described above, in the present embodiment, of the plurality of banks, the banks other than the bank being accessed are simultaneously precharged. Therefore, the precharge command input can be performed in only one cycle, and the precharge of a specific plurality of banks can be started at once in one clock. Further, the interleave operation of the bank in the active state and another bank can be performed. As a result, the precharge command eliminates the problem that other commands such as a data mask cannot be input. As a result, it is possible to obtain an easy-to-use semiconductor memory device that does not interfere with the precharge command type command.

Next, an SDRAM which is a semiconductor memory device of another embodiment of the present invention will be described. In the semiconductor memory device described below, only the precharge signal generating circuit 5 of the semiconductor memory device shown in FIG. 1 is changed, and the other configuration is the same as that of the semiconductor memory device shown in FIG. Omit it. Therefore, only the precharge signal generating circuit which is a different portion will be described in detail below. FIG. 8 is a diagram showing the configuration of a precharge signal generation circuit of a semiconductor memory device according to another embodiment of the present invention.

Referring to FIG. 8, precharge signal generating circuit 5a includes AND gates G60 to G67 and NAND gate G68. Address signals A0 to A7 are input to the AND gates G60 to G67, respectively. The NAND gate G68 has a chip select signal / CS, a row address strobe signal / RAS, and a write enable signal / W.
E is input respectively, and the output signal is AND gate G
60 to G67 are input. AND gates G60 to G6
7 outputs precharge start signals P0 to P7, respectively.

With the above configuration, the chip select signal /
When the precharge command in which CS, the row address strobe signal / RAS, and the write enable signal / WE each become "L" is input, the input address signal A
The bank precharge start signals corresponding to n (n = 0 to 7) = “H” are simultaneously activated.

Next, the operation of the semiconductor memory device using the precharge signal generating circuit shown in FIG. 8 will be described. FIG. 9 is a timing chart for explaining the operation of the semiconductor memory device using the precharge signal generation circuit shown in FIG.

Referring to FIG. 9, bank B6 and bank B0 are activated at timings T1 and T2, respectively, and a precharge command is input at time T4. When the precharge command is input at time T4, the lower address signals A0 to A7 are simultaneously input. The lower address signals A0 to A7 are signals for designating a bank to start precharging. The lower address signals A0 to A7 are respectively bank B0 to bank B.
7 corresponding to, for example, (A0, A1, A2, A
3, A4, A5, A6, A7) = (0, 1, 1, 1,
1, 1, 0, 1), precharge of bank B1, bank B2, bank B3, bank B4, bank B5, and bank 7 is started. That is, the precharge of a plurality of banks designated by the lower address signals A0 to A7 at the time of inputting the precharge command can be started at the same time.

As a result, a plurality of banks (bank B in FIG. 9)
0 and bank B6) are waiting for a read / write command or in an active state during the cycle, other banks (banks B1 to B5, B7 in FIG. 9) can be precharged at the same time. Therefore, it is possible to start precharging of specific banks at one clock. As a result, the precharge command eliminates the problem that other commands such as a data mask cannot be input. Therefore, it is possible to obtain an easy-to-use semiconductor memory device in which the precharge timing does not interfere with other commands.

In each of the above embodiments, the SDRAM of 8 banks is used.
, But SDRA with 3 or more banks
The same applies to M.

[0063]

In the semiconductor memory device according to any one of claims 1 to 3, the banks other than the bank being accessed can be precharged at the same time among the plurality of banks, so that the precharge timing is a failure of another command. It is possible to obtain an easy-to-use semiconductor memory device that does not become a problem.

In the semiconductor memory device according to the fourth and fifth aspects, any bank of the plurality of banks can be precharged at the same time, so that the precharge timing is not an obstacle to other commands and is easy to use. A storage device can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an internal clock generation circuit shown in FIG.

FIG. 3 shows / RAS, / CAS, / WE, / shown in FIG.
It is a figure which shows the structure of a CS buffer and a mode set setting circuit.

FIG. 4 is a diagram showing a configuration of a dynamic latch shown in FIG.

5 is a timing chart for explaining the operation of the dynamic latch shown in FIG.

FIG. 6 is a diagram showing a configuration of a precharge signal generation circuit shown in FIG. 1.

7 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG.

FIG. 8 is a diagram showing a configuration of a precharge signal generation circuit of a semiconductor memory device according to another embodiment of the present invention.

9 is a timing chart for explaining the operation of the semiconductor memory device using the precharge signal generation circuit shown in FIG.

FIG. 10 is a block diagram showing a configuration of a main part of a conventional semiconductor memory device.

FIG. 11 is a block diagram showing a configuration of a main part of another conventional semiconductor memory device.

12 is a timing chart for explaining the operation of the semiconductor memory device shown in FIG.

FIG. 13 is a first timing chart for explaining a problem of the semiconductor memory device shown in FIG.

FIG. 14 is a second timing chart for explaining a problem of the semiconductor memory device shown in FIG.

[Explanation of symbols]

1 / RAS, / CAS, / WE, / CS buffer, 2
Internal clock generator, 3 address buffers, 4
Mode set setting circuit, 5 precharge signal generation circuit, B0 to B7 banks.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisashi Iwamoto 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation ULS Development Research Center

Claims (5)

[Claims] 1. A plurality of banks for storing data, a plurality of precharge means provided corresponding to each of the plurality of banks and precharging a corresponding bank, and an access among the plurality of banks. A semiconductor memory device including a control unit that controls the plurality of precharge units so as to simultaneously precharge banks other than the inner bank. 2. The control means controls the plurality of precharge means so as to simultaneously precharge banks other than the bank being accessed among the plurality of banks according to a mode set. Semiconductor memory device. 3. The control means decodes a bank address signal and outputs a bank designating signal, and outputs an exclusive OR of the bank designating signal and a mode set signal designating the mode set. 3. The semiconductor memory device according to claim 2, including logic means. 4. A plurality of banks for storing data, a plurality of precharge means provided corresponding to each of the plurality of banks and precharging the corresponding banks, and a bank designation inputted from the outside. A semiconductor memory device comprising: a control unit that controls the plurality of precharge units so as to simultaneously precharge an arbitrary bank of the plurality of banks according to a signal. 5. The semiconductor memory device according to claim 4, wherein the bank designation signal includes a lower address signal input when a precharge command is input.