JPH0836594A - Automatic circuit generating device - Google Patents

Abstract

PURPOSE:To provide an automatic circuit generating device which generates automatically a circuit to process the data of desired bit length. CONSTITUTION:The bit length B inputted from an input part 11 is stored in a bit length storage part 12 as a parameter N. A module selecting part 13 selects a circuit module on the basis of this parameter N, and a fundamental module (1) generating part 14 or a fundamental module (2) generating part 15 generates the circuit module on the basis of a selected result. The generated circuit module is connected and stored successively by a generated circuit storage part 16. Simultaneously with the generation of the module, a subtracting part 17 updates the parameter N stored in the bit length storage part 12 by subtracting one at a time successively from it. When this subtracted result becomes '0', circuit information stored in the generated circuit storage part 16 is outputted from an output part 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic circuit generation device preferably used as a device for designing a circuit used in, for example, LSI development.

[0002]

2. Description of the Related Art Circuit design using a CAD device is rapidly spreading. In particular, for circuit design / circuit input of a logic circuit of an LSI as an application-specific IC (ASIC) such as a gate array, the designed circuit information can be directly converted into a netlist or layout data, which enables efficient simulation and layout. Therefore, it is usually performed using a CAD device. In circuit design by a CAD device, a designer first reads out desired arithmetic elements from a library prepared in advance and sequentially arranges them at arbitrary positions in the circuit diagram displayed on the screen. Then, the input and output terminals of these arithmetic elements are sequentially connected using a mouse or the like to perform circuit input. The library includes an inverter
Basic operation elements such as AND / OR / NAND / NOR and functional operation elements such as an adder / counter / comparator / multiplexer are stored. In addition, an arithmetic circuit that can be configured at a higher speed or lower power consumption than that configured by a designer combining basic arithmetic elements is also stored as one module.

Further, in such a designed circuit, the bit length of the processed data handled by a circuit formed on an ordinary substrate is a power of 2 such as 8 bits, 16 bits or 32 bits. There are many. However, the circuits inside the LSI are often designed with a bit length necessary and sufficient for the data to be handled due to restrictions such as the number of gates and power consumption. For example, data such as 9 bits and 17 bits in consideration of carry, and processing with bit lengths of 15 bits and 31 bits are frequently performed due to the limitation of the maximum value. Also, when determining the bit length,
In many cases, a circuit in which the bit length is changed is input, a simulation is performed, the characteristics of the circuit are evaluated, and the bit length is finally determined. Therefore, especially L
When designing the circuit inside the SI, changes to increase or decrease the bit length of the processed data are frequently made.

[0004]

However, as described above, C
Even when a circuit is designed using the AD device, the actual input work is a repeated manual work, and thus there is a problem that it takes a very long time. In particular, changing the bit length of the data to be processed as described above, which is frequently performed when designing the circuit inside the LSI, is often time-consuming and time-consuming, which is an obstacle to improving the efficiency of circuit design. It was Also,
When a circuit is configured using a module that processes data of a plurality of bit lengths, for example, the change of the bit length of 1-bit data is not limited to the modification of the circuit corresponding to the 1-bit data, In many cases, the entire department must be reviewed. In such a case, the circuit must be modified significantly, and the efficiency of the circuit design is greatly reduced.

Therefore, an object of the present invention is to automatically generate a circuit for processing data of a desired bit length,
Therefore, it is an object of the present invention to provide an automatic circuit generation device capable of easily redesigning a circuit according to a change in bit length. Another object of the present invention is to provide a CAD device capable of remarkably shortening the design time by facilitating the redesign of the circuit according to the change of the bit length.

[0006]

The change of the bit length of the processed data is originally a simple and regular change. Therefore, for example, if the processing circuits for 1 bit are stored so that they can be connected to each other, it should be possible to regularly generate circuits that are connected in series or parallel in a certain degree. Therefore, the invention has invented an automatic circuit generation device that automatically generates a circuit capable of processing data of an arbitrary bit length by storing the data of such a circuit module and inputting the bit length from the outside. Further, differences in circuits based on bit positions and regular differences can be dealt with by storing a plurality of modules and appropriately selecting and connecting them.
Further, a module for processing data of a plurality of bits such as 2 bits or 4 bits is used, and by combining them, a circuit for processing data of a desired bit length can be generated.

Therefore, the circuit automatic generation device of the present invention includes a circuit module storage means for storing circuit information of a plurality of types of circuit modules and information for connecting these circuit modules to each other, and a bit length of input processing data. Circuit module selecting means for sequentially selecting a plurality of types of circuit modules stored in the circuit module storing means, and a circuit module selected by the circuit module selecting means based on the connection information of the circuit module. Circuit connecting means for sequentially connecting with each other, and output means for outputting the circuit connected by the circuit connecting means.

Specifically, the circuit module storage means stores the respective pieces of information of a plurality of different types of circuit modules corresponding to the bit positions of the processed data, and the circuit module selection means selects the order of selection. Based on this, a predetermined circuit module is sequentially selected from a plurality of types of circuit modules stored in the circuit module storage means. Further, specifically, the circuit module storage unit stores each piece of information of a plurality of circuit modules which have different bit lengths of data to be processed and operate in the same manner, and the circuit module selection unit stores the different bit lengths. The appropriate circuit modules are sequentially selected from the plurality of types of circuit modules stored in the circuit module storage means so that the input process data has the bit length by combining the circuit modules of the above.

Preferably, the circuit module selection means sets a bit length storage means for storing the bit length of the input processing data, and a selection parameter based on the bit length stored in the bit length storage means. Parameter calculating means for calculating, selecting means for sequentially selecting a circuit module from a plurality of types of circuit modules stored in the circuit module storing means based on the selection parameter calculated by the parameter calculating means, and the parameter A bit length updating means for updating the bit length stored in the bit length storing means based on the selection parameter calculated by the calculating means, and a case where the bit length updated by the bit length updating means is other than 0 Control means for repeatedly interlocking the respective means, and the output means has the bit length. Bit length, which is updated by the new means outputs a circuit connected by the circuit connecting means in the case of zero.

Specifically, the circuit automatic generator is an automatic generator of a carry look ahead circuit.
In the circuit module storage means, a first circuit module which is a 1-bit carry look ahead circuit which outputs two 1-bit inputs and a carry to the upper part based on a carry from the lower part, and the first circuit module. Each of the information of the second circuit module in which an output buffer is further added to the circuit module of No. 1 is stored, and the circuit module selection unit is the number of the first circuit module that is one less than the bit length of the input processing data. Are successively selected, and one of the second circuit modules is further selected.

More specifically, this circuit automatic generation device is an automatic generation device for a carry look ahead circuit, wherein the circuit module storage means has a plurality of types of carry look ahead with different bit lengths. Each of the information of the circuit module is stored, and the circuit module selection means is configured to combine the different bit lengths to obtain a bit length of the input processing data from the plurality of carry-look-ahead circuit modules. , Select appropriate circuit modules sequentially.

Further, the circuit automatic generation apparatus of the present invention comprises an input means for inputting a circuit operation and a bit length of processed data,
The circuit module storage means stores a plurality of circuit automatic generation devices in which connection information with circuits of different operations is further stored, and information indicating a plurality of circuits output by the plurality of circuit automatic generation devices, It has a circuit synthesizing means for synthesizing based on connection information with circuits of different operations, and automatically combines circuits of a plurality of operations to perform predetermined processing on data of arbitrary bit length. Generate

[0013]

The circuit automatic generation device of the present invention stores circuit information and connection information for a circuit module that performs a predetermined operation. Therefore, based on the number of input bits,
By connecting an arbitrary number of circuit modules, it is possible to generate a circuit in which data having a desired bit number is processed. Also,
Since a plurality of types of circuit modules are stored, and the circuit modules are appropriately selected and connected according to the order of selection and the like, it is possible to appropriately generate a circuit having a slightly different configuration depending on the bit position. In addition, since the parameter is obtained by calculation based on the input number of bits and the circuit module is selected based on the parameter,
A circuit can be configured by connecting circuit modules having different bit lengths of data to be processed to each other.
Therefore, it is possible to appropriately generate a circuit for processing data of a desired bit length by using a circuit module that cannot be separated bit by bit.

[0014]

For EXAMPLES circuit automatic generation apparatus of the first embodiment of the first embodiment the present invention, FIG. 1
~ It demonstrates with reference to FIG. First, the configuration of the circuit automatic generation device of the first embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the circuit automatic generation device of the first embodiment. The circuit automatic generation device 10 includes an input unit 11, a bit length storage unit 12, a module selection unit 13, a basic module a generation unit 14, a basic module b generation unit 15, a generation circuit storage unit 16, a subtraction unit 17, and an output unit. It is composed of 18. The circuit automatic generation device 10 of the present embodiment is incorporated in a CAD device used when designing a logic circuit or the like.

The operation of each unit will be described below. The input unit 11 is an input device such as a keyboard, and the operator inputs the bit length B, which is the data width of the circuit, from the input unit 11. The input bit length B is stored in the bit length storage unit 12 as a parameter N for selecting a module.
Is stored as Since this bit length B is the bit width of data, an integer of 2 or more is normally input.
The bit length storage unit 12 is a data storage circuit including a memory, and is used for selecting a module based on the bit length B input from the input unit 11 and the parameter Nnew updated by the subtraction unit 17 described later. Store as parameter N. The parameter N stored in the bit length storage unit 12 can be read by the module selection unit 13 and the subtraction unit 17.

The module selection unit 13 is a selection unit for selecting a basic module based on the parameter N stored in the bit length storage unit 12. Module selection unit 13
When the parameter N is 2 or more, the basic module a outputs a selection signal S1 indicating that fact via a predetermined selection line.
It is applied to the generation unit 14 and the subtraction unit 17. Further, when the parameter N is 1, the basic module b generation unit 1 outputs the selection signal S2 indicating the fact via a predetermined selection line.
5 and to the output unit 18.

When the selection signal S1 is applied from the module selection unit 13, the basic module a generation unit 14 generates the basic module a stored in the basic module a generation unit 14 as actual circuit information, and the generation circuit Output to the storage unit 16. The basic module a generation unit 14 stores arithmetic elements forming the basic module a, connection information thereof, connection information with other elements, and circuit characteristic information such as element delay. Therefore, the basic module generation unit 14 reads the information and adds identification information such as a signal name to generate actual circuit information that can be connected to other elements and can be arranged in a circuit drawing or the like. When the selection signal S2 is applied from the module selection unit 13, the basic module b generation unit 15 generates the basic module b stored in the basic module b generation unit 15 as actual circuit information, and the generation circuit storage unit 16 Output to. The stored information and the generation of the actual circuit information are the same as those of the basic module a generation unit 14 described above.

The generation circuit storage unit 16 includes the basic module a.
This is a storage unit for sequentially connecting and storing the basic modules sequentially generated by the generation unit 14 and the basic module b generation unit 15 in the order of input. The information on the connection method is described in the information of each basic module stored in the basic module a generation unit 14 and the basic module b generation unit 15 in advance. The subtraction unit 17
When the selection signal S1 is applied from the module selection unit 13, 1 is subtracted from the bit length parameter N stored in the bit length storage unit 12, and a new parameter Nnew as a result of this subtraction is input to the bit length storage unit 12. To do. That is, every time the basic module a is selected as the generation module by the module selection unit 13, the bit length storage unit 1
1 is subtracted from the bit length parameter N stored in 2, and the parameters are sequentially updated.

When the selection signal S2 is applied from the module selection unit 13, the output unit 18 is generated by the basic module a generation unit 14 and the basic module b generation unit 15 until then, and is sequentially connected by the generation circuit storage unit 16. The stored circuit information is read and output. The output information is arranged at a designated position on the circuit diagram, and is displayed on an output device such as a display in a state in which it can be viewed by an operator.

Next, the operation of automatic circuit generation by the circuit generator 10 will be specifically described with reference to FIGS. 2 and 3. In this embodiment, the circuit automatic generation device 1
0 is a carry look, which is often used in adders.
It is an automatic circuit generation device that generates a CLA circuit having a desired number of bits for an ahead circuit (carry look-ahead signal, hereinafter referred to as CLA circuit). FIG. 2 is a diagram showing basic modules stored in the basic module a generation unit 14 and the basic module b generation unit 15, where (A) is CLA.
FIG. 1B is a diagram showing a basic module a corresponding to a 1-bit logic circuit of the circuit, and FIG. 6B is a diagram showing a basic module b having a configuration in which an output buffer is added to the 1-bit logic circuit of the CLA circuit. .

FIG. 3 is a diagram showing a circuit generated by the circuit automatic generation device 10, which is a 4-bit CLA circuit. As shown in FIG. 3, in the 4-bit CLA circuit, 4-bit carry check circuits are connected in series, and an output buffer is added to the output section of the final circuit. . Therefore, if the basic module shown in FIG. 2 is used, three basic modules a shown in FIG. 2A and one basic module b shown in FIG.
One is a state in which they are sequentially connected.

The operation of the automatic circuit generation device 10 when generating a 4-bit CLA circuit will be described below.
First, 4 is input as the input value of the bit length from the input unit 11, and is stored as the parameter N in the bit length storage unit 12. In the module selection unit 13, the parameter N is referred to, and since N ≠ 1, the selection signal S1 is selected. As a result, the basic module a is selected, and the circuit shown in FIG. 2A generated by the basic module a generation unit 14 is stored in the generation circuit storage unit 16. On the other hand, in the subtraction unit 17 to which the selection signal S1 is applied, 1 is subtracted from the parameter N stored in the bit length storage unit 12, and a new parameter Nnew is set as the bit length storage unit 12
Is set to

Thereafter, the circuit generation process is repeated based on the updated parameters. When selecting the basic module for the second time, the parameter N is 3 and N ≠ 1, so
As in the case of the first time described above, again the basic module a
Is generated. Furthermore, N = 2 when the circuit is generated for the third time.
Therefore, the basic module a is similarly generated. The generated three basic modules a are sequentially connected and stored in the generation circuit storage unit 16.

After generating the three basic modules a, the parameter N stored in the bit length storage unit 12 is 1. Therefore, at the time of the fourth circuit generation, since the parameter N = 1, the module selection unit 13 selects the selection signal S2. As a result, the basic module b is selected, and the circuit shown in FIG. 2B generated by the basic module b generation unit 15 is input to the generation circuit storage unit 16 and connected to and stored in the circuits up to that point. . As a result, the 4-bit CLA circuit as shown in FIG. 3 is generated in the generation circuit storage unit 16. Then, the selection signal S2 is simultaneously applied to the output unit 18, and the output unit 18 reads out and outputs the CLA circuit from the generation circuit storage unit 16.

The circuit automatic generation device 10 can also be realized by a CAD tool mounted on a workstation or the like. Processing when the circuit automatic generation device 10 of the first embodiment is applied to such a computer device will be described with reference to FIG. FIG. 4 is a diagram showing a flow chart when the circuit automatic generation device 10 is realized by a computer device.

First, in step 11, the bit length input from the input device is set in a variable N. Next, step 1
It is checked in step 2 whether N = 1, and if N ≠ 1, step 1
In 3, the circuit of the basic module a stored in the memory is generated. Then, in step 14, 1 is subtracted from N, and the process is repeated from step 12. When N = 1 in step 12, the circuit of the basic module b is generated in step 15. Then, in step 16, the basic modules generated and stored so far are sequentially connected and output.

As described above, according to the circuit automatic generation device of the first embodiment, the CLA circuit having the input bit length can be generated. Further, since the circuit modules can be selected in accordance with the order of generation, even when the circuit configuration is slightly different depending on the bit position, such as an output buffer added only to the output of the final stage, it is appropriate. A circuit can be created.

Second Embodiment FIG. 5 shows an automatic circuit generator according to a second embodiment of the present invention.
This will be described with reference to FIGS. First, the configuration of the circuit automatic generation device of the second embodiment will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the circuit automatic generation device according to the second embodiment. The circuit automatic generation device 20 includes an input unit 21, a bit length storage unit 22, a remainder calculation unit 23, a module selection unit 24, a 4-bit module generation unit 25, a 3-bit module generation unit 26, a 2-bit module generation unit 27, and a generation circuit. The storage unit 28, the subtraction value determination unit 29, the subtraction unit 30, the determination unit 31, and the output unit 32 are included. Like the circuit automatic generation device 10 of the first embodiment, the circuit automatic generation device 20 of the present embodiment is also incorporated in a CAD device used when designing a logic circuit or the like.

The operation of each unit will be described below. The input unit 21 is an input device such as a keyboard, and an operator inputs the bit length B, which is the data width of the circuit, from the input unit 21. The input bit length B is stored in the bit length storage unit 22. Since this bit length B is the bit width of data, an integer of 2 or more is normally input. The bit length storage unit 22 is a data storage unit configured by a memory, receives data from the input unit 21, and sequentially updates the data by the determination unit 31 described later. The data stored in the bit length storage unit 22 is the parameter N representing the bit length for circuit generation. The parameter N stored in the bit length storage unit 22 is the remainder calculation unit 2
3 and the subtraction unit 30 can read.

The remainder calculation unit 23 divides the parameter N stored in the bit length storage unit 22 by a predetermined number, obtains the remainder, and sets the module selection unit 24 as a parameter M for selecting a module and the subtraction value determination. It is output to the unit 29. The predetermined divisor is a numerical value determined by the maximum bit length of the basic module generated by the module generation unit described later, and is 4 in this embodiment. Therefore, the remainder, the parameter M, takes a value of 0 to 3.

The module selection unit 24 includes a remainder calculation unit 23.
It is a selection unit for selecting a basic module based on the parameter M input by the operator. The module selection unit 24 decodes the parameter M, generates a selection signal according to the value of the parameter M, and applies the signal to the corresponding module generation unit. In the present embodiment, since the parameter M takes four values of 0 to 3, the module selection unit 24 generates any of the four selection signals S0 to S3, and the four output signal lines corresponding to each selection signal. A signal is applied to each module generation unit via. Specifically, when the parameter M is 0, the selection signal S0 is sent to the 4-bit module generation unit 25.
Is applied and the parameter M is 1, the selection signal S1 is applied to the 3-bit module generation unit 26 and the 2-bit module generation unit 27, and when the parameter M is 2, the 2-bit module generation unit 27 is applied. When the selection signal S2 is applied and the parameter M is 3, the selection signal S3 is applied to the 3-bit module generation unit 26.

When the selection signal S0 is applied from the module selection unit 24, the 4-bit module generation unit 25 generates the 4-bit module stored in the 4-bit module generation unit 25 as actual circuit information, and the generation circuit Storage unit 2
Output to 8. The stored information and the generation of the actual circuit information are the same as in the first embodiment described above. The 3-bit module generation unit 26 selects the selection signal S2 and the selection signal S applied from the module selection unit 24.
Based on 3, the 3-bit module is generated similarly to the 4-bit module generation unit 25. The 2-bit module generation unit 27 generates a 2-bit module based on the selection signal S1 and the selection signal S2 applied from the module selection unit 24.

The generation circuit storage unit 28 sequentially connects the basic modules sequentially generated by the 4-bit module generation unit 25, the 3-bit module generation unit 26, and the 2-bit module generation unit 27 in the order of input. It is a storage unit for storing. The information on the connection method is described in the information of each basic module stored in advance in each module generation unit.

The subtraction value determination unit 29 calculates the bit length of the circuit module selected by the module selection unit 24 based on the parameter M calculated by the remainder calculation unit 23, and outputs it to the subtraction unit 30 as the subtraction value P. To do. The bit length is obtained by referring to a table stored in advance in the subtraction value determination unit 29 corresponding to each circuit module when storing each circuit module. In the present embodiment, when the parameter M = 0, the subtraction value P = 4 and the parameter M = 1.
In the case of, the subtraction value P = 5, in the case of the parameter M = 2, the subtraction value P = 2, and in the case of the parameter M = 3, the subtraction value P = 3 is obtained and output. The subtraction value determination unit 29 of the present embodiment
In the above, the subtraction value P is obtained based on the parameter M calculated by the remainder calculating unit 23. Similarly, the selection signals S0 to S3 output from the module selecting unit 24 generated based on the parameter M are used. You may ask for it.

The subtraction unit 30 subtracts the subtraction value P selected by the subtraction value determination unit 29 from the bit length parameter N stored in the bit length storage unit 22 to obtain the subtraction result Nnew.
Is calculated and output to the determination unit 31. That is, every time a circuit module is sequentially selected, a value corresponding to the bit length of the selected circuit module is set to the bit length parameter N.
Further, the bit length Nnew awaiting circuit generation is obtained.

Based on the subtraction result Nnew input from the subtraction unit 30, the determination unit 31 determines whether to repeat the module generation process or to terminate the process and output the generated circuit. Since the subtraction result Nnew is a value indicating the bit length of the circuit to be generated, the determination unit 31 terminates the process if the subtraction result Nnew is 0 or less, and continues to generate the circuit if the subtraction result Nnew is greater than 0. Perform processing. Therefore, when the subtraction result Nnew is 0 or less, the output unit 32 outputs a signal that outputs the circuit data generated and stored so far. Also, the subtraction result N
If new is greater than 0, the subtraction result Nnew is input to the bit length storage unit 22, and the parameter stored in the bit length storage unit 22 is updated with this subtraction result Nnew.

When the output signal is applied from the determination unit 31, the output unit 32 has the 4-bit module generation unit 2 until then.
The circuit information generated by the 5- and 3-bit module generation unit 26 and the 2-bit module generation unit 27 and sequentially connected and stored in the generation circuit storage unit 28 is read and output. The output information is arranged at a designated position on the circuit diagram, and is displayed on an output device such as a display in a state in which it can be viewed by an operator.

Next, the operation of the circuit automatic generation by the circuit automatic generation device 20 will be specifically described with reference to FIGS. 6 and 7. In this embodiment, the circuit automatic generation device 20 is a circuit automatic generation device for generating a CLA circuit having a desired bit number for the CLA circuit, as in the first embodiment. In the second embodiment, a CLA circuit having an optimal configuration for each of 4 bits, 3 bits, and 2 bits is prepared in advance as a library, and these are used as a basic circuit module to generate an arbitrary bit length. It is an automatic path generation device that generates a CLA circuit. Figure 6
Is a 4-bit module generation unit 25, a 3-bit module generation unit 26, and a 2-bit module generation unit 27.
It is a diagram showing a circuit module stored in
(A) is a diagram showing a module of a 4-bit CLA circuit,
(B) is a diagram showing a module of a 3-bit CLA circuit,
(C) is a diagram showing a module of a 2-bit CLA circuit.

FIG. 7 is a diagram showing a circuit generated by the circuit automatic generation device 20, which is a 9-bit CLA circuit. As shown in FIG. 7, the 9-bit CLA circuit has a configuration in which a 2-bit CLA circuit, a 3-bit CLA circuit, and a 4-bit CLA circuit are connected in series. The operation of the circuit automatic generation device 20 when generating a 9-bit CLA circuit will be described below.

First, 9 is input as an input value of the bit length from the input unit 21, and the parameter N is stored in the bit length storage unit 22.
Is stored as The remainder calculator 23 calculates the remainder 1 by dividing the parameter N by 4. The value 1 of the calculation result is used as the parameter M by the module selection unit 24.
And the selection signal S2 is selected. As a result, the 2-bit module shown in FIG. 6A and the 3-bit module shown in FIG. 6B are generated, and the generation circuit storage unit 28 is generated.
Is stored. On the other hand, the subtraction value determination unit 29 obtains the subtraction value P = 5 based on the parameter M = 1, and the subtraction unit 30 performs the subtraction with the parameter N = 9 to obtain the result 4. Since the result of the subtraction is 4, the determination unit 31 inputs the result of the subtraction into the bit length storage unit 22 as a new bit length parameter.

The module is generated again based on the parameter N updated in this way. Since the parameter N = 4 this time, the parameter M = 0, which is the remainder, is generated, and the 4-bit module shown in FIG. 6C is generated.
It is input to the generation circuit storage unit 28, connected to the circuits up to that point, and stored. Further, the subtraction value determination unit 29 obtains 4 as the subtraction value P, and as a result, the subtraction result Nnew in the subtraction unit 30 becomes zero. Therefore, the determination unit 31
The output signal is applied to the output section 32 from the output section 32, and the circuit diagram of the 9-bit CLA circuit shown in FIG.

The circuit automatic generator 20 is also the first
C mounted on a workstation or the like as in the embodiment
It can be realized with an AD tool. Processing when the circuit automatic generation device 20 of the second embodiment is applied to such a computer device will be described with reference to FIG. FIG. 8 is a diagram showing a flowchart when the circuit automatic generation device 20 is realized by a computer device.

First, in step 21, the bit length input from the input device is set in the variable N. Next, step 2
The remainder obtained by dividing N by 4 by 2 is calculated and set to the variable M. Then, based on this variable M, it is determined in step 23 whether or not M = 0. If M = 0, a 4-bit module is generated in step 24, and a variable P is set to 4 in step 25. In step 23, M ≠
If 0, it is checked in step 26 whether M = 1 or 2. If M = 1 or M = 2, then in step 27 a 2-bit module is generated. Then, in step 28, it is determined whether M = 1 or M = 2. When M = 1, the variable P is set to 2 in step 29, and when M = 2, step 30 is set.
Then, the variable P is set to 5.

On the other hand, in step 26, M is 1 or 2
If not, that is, if M = 3,
In step 31, variable P is set to 3 prior to circuit generation. Then, along with the case of M = 1 in which a 2-bit module has already been generated in steps 26 to 30, a 3-bit module is generated in step 32. In this way, step 23 to step 3
When the generation of the module and the setting of the subtraction value to the variable P are completed in 2, the subtraction of N−P is performed in step 33, and the variable N is updated with this subtraction result. And
In step 34, the value of the variable N is checked, and if the variable N is larger than 0, the process is repeated from step 22 again. In step 34, when the variable N is 0 or less, in step 35, the circuit modules generated and stored up to that point are sequentially connected and output.

As described above, according to the circuit automatic generator 20 of the second embodiment, it is possible to generate the CLA circuit having the input bit length as in the first embodiment. In particular, even if the stored circuit module is a circuit for processing a plurality of bits of data, it is possible to appropriately combine them to generate a CLA circuit having a desired bit length.

Third Embodiment FIG. 9 shows an automatic circuit generator according to a third embodiment of the present invention.
Will be described with reference to. The circuit automatic generation device according to the third embodiment has a plurality of circuit automatic generation devices according to the first or second embodiment, synthesizes a plurality of types of circuit modules having different operations, and generates a circuit having a more complicated configuration. It is an automatic circuit generation device that has been made possible. The circuit automatic generation device 50 of the third embodiment includes an input unit 51, first to fourth circuit automatic generation devices 52 to 55, and a synthesis unit 56.

In the input section 51, a signal for selecting the type of module forming the circuit is input together with the bit length of the processed data, and the bit length and the circuit are generated in the circuit module generation device corresponding to the selected signal. Send the signal to instruct. A plurality of types of modules may be selected as the modules forming this circuit. Note that the selection order is selected in accordance with the combining rule by the combining unit 56.

The first to fourth circuit automatic generators 52 to 55
Is a generation means for automatically generating a circuit module that performs a predetermined operation for data of an arbitrary bit length that performs a predetermined operation. These circuit automatic generators, for example,
It is a generation unit such as a CLA circuit, an addition circuit, a selection circuit, and a shift register circuit. Each circuit automatic generation unit, for example,
Although the circuit automatic generation device shown in the first and second embodiments is used, the connection information stored in the circuit module storage means of each circuit automatic generation unit includes a plurality of connection information in each circuit automatic generation unit. In addition to the connection information between the circuit modules, these first to fourth circuit automatic generation sections 5
The connection information between the circuits generated in 2 to 55 is also stored. The bit length of the processed data of the circuit to be generated is input from the input unit 57.

The synthesis unit 56 further synthesizes the circuit modules generated by the first to fourth circuit automatic generation units 52 to 55 to generate one circuit and outputs it. The combining unit 56
Each circuit is synthesized based on the circuit connection information output from each circuit automatic generation unit and the connection information of each terminal of the circuit.
This combining is performed based on a predetermined rule such as connecting the output terminal of the generated circuit module to the input terminal of the next selected circuit in the order selected by the input unit 51.

According to the circuit automatic generation device of the third embodiment having such a configuration, in addition to automatically generating a circuit for processing data of an arbitrary bit length, a basic circuit module is further combined. It is possible to automatically generate a somewhat complicated circuit, and it is possible to further improve the efficiency of circuit design.

The present invention is not limited to the above-described first and second embodiments, and various modifications can be made. For example, the present embodiment has been specifically described as a circuit automatic generation device that generates a CLA circuit, but the present invention is not limited to this. The present invention can be applied to any circuit as long as it is a circuit that can be configured by sequentially and regularly connecting a plurality of basic circuits for data of arbitrary bits in series or in parallel. For example, it can be applied to a shift register, a multiplexer, an adder, and the like.

Further, in the configuration of the circuit module generation unit of the present embodiment, each circuit module generation unit generates and outputs a predetermined circuit module based on the applied signal. However, for example, one control unit may be configured to include a control unit and a storage unit such that the circuit module is appropriately selected and output from the circuit modules stored in the storage unit based on the selection signal. Further, the present invention does not limit the method of describing the circuit module and the generated circuit. For example, a circuit written in the form of a netlist using basic elements and connection states,
Circuits written using hardware description language (HDL), circuits whose operations are described functionally and logically,
Any description / format circuit can be applied.

[0053]

According to the automatic circuit generating apparatus of the present invention, a predetermined number of circuit modules can be connected based on the number of input bits, and data having a desired bit length can be processed. The circuit that does this can be generated automatically. Also, a circuit having a slightly different configuration depending on the bit position could be appropriately generated. Further, it is possible to generate a circuit for processing data of a desired bit length by combining basic circuit modules corresponding to a plurality of bits. Therefore, it is possible to provide an automatic circuit generation device that can easily redesign a circuit according to a change in bit length. Further, as a result, it is possible to provide a CAD device capable of significantly reducing the design time and efficiently designing a circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a circuit automatic generation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit module generated by a basic module generation unit of the circuit automatic generation device shown in FIG.
(A) is a figure which shows the basic module a, (B) is a figure which shows the basic module b.

FIG. 3 is a diagram showing a circuit generated by the circuit automatic generation device shown in FIG.

FIG. 4 is a diagram showing a flow chart when the circuit automatic generation device shown in FIG. 1 is realized by a computer device.

FIG. 5 is a block diagram showing a configuration of an automatic circuit generation device according to a second embodiment of the present invention.

6 is a diagram showing a circuit module generated by a module generation unit of the circuit automatic generation device shown in FIG.
(A) is a diagram showing a 2-bit module, (B) is a diagram showing a 3-bit module, and (C) is a diagram showing a 4-bit module.

7 is a diagram showing a circuit generated by the circuit automatic generation device shown in FIG.

8 is a diagram showing a flowchart in the case where the automatic circuit generation device shown in FIG. 5 is realized by a computer device.

FIG. 9 is a block diagram showing the configuration of an automatic circuit generation device according to a third embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Automatic circuit generation device 11 ... Input unit 12 ... Bit length storage unit 13 ... Module selection unit 14 ... Basic module a generation unit 15 ... Basic module b generation unit 16 ... Generation circuit storage unit 17 ... Subtraction unit 18 ... Output unit 20 Circuit automatic generation device 22 Bit length storage unit 23 Residue calculation unit 24 Module selection unit 25 4-bit module generation unit 26 3-bit module generation unit 27 2-bit module generation unit 28 Generation circuit storage unit 29 Subtraction value determination unit 30 ... Subtraction unit 31 ... Judgment unit 32 ... Output unit 50 ... Circuit automatic generation device 51 ... Input unit 52 ... First circuit automatic generation unit 53 ... Second circuit automatic generation unit 54 ... Third circuit Automatic generation unit 55 ... Fourth circuit automatic generation unit 56 ... Synthesis unit

Claims (7)

[Claims] 1. A circuit module storage means in which circuit information of a plurality of types of circuit modules that operate in the same manner and connection information between the circuit modules are stored, and based on a bit length of input process data, A circuit module selection unit that sequentially selects a plurality of types of circuit modules stored in the circuit module storage unit, and a circuit that sequentially connects the circuit modules selected by the circuit module selection unit based on the connection information of the circuit module. An automatic circuit generation device having a connecting means and an output means for outputting information representing a circuit connected by the circuit connecting means. 2. The circuit module storage means stores the respective pieces of information of a plurality of different types of circuit modules corresponding to bit positions of processed data, and the circuit module selection means, based on an order of selection, The automatic circuit generation device according to claim 1, wherein a predetermined circuit module is sequentially selected from a plurality of types of circuit modules stored in the circuit module storage means. 3. The circuit module storage means stores the respective pieces of information of a plurality of types of circuit modules having different bit lengths of processed data, and the circuit module selection means combines the circuit modules having different bit lengths with each other. 2. The circuit automatic generation device according to claim 1, wherein an appropriate circuit module is sequentially selected from a plurality of types of circuit modules stored in the circuit module storage means so that the input process data has a bit length. 4. The circuit module selection means calculates a selection parameter based on a bit length storage means for storing a bit length of the input processing data and a bit length stored in the bit length storage means. Parameter calculation means, selection means for sequentially selecting circuit modules from a plurality of types of circuit modules stored in the circuit module storage means based on the selection parameters calculated by the parameter calculation means, and the parameter calculation A bit length updating means for updating the bit length stored in the bit length storing means on the basis of the selection parameter calculated by the means; and if the bit length updated by the bit length updating means is other than 0, then Control means for repeatedly interlocking each means, and the output means updates the bit length. 4. The circuit automatic generation device according to claim 1, wherein when the bit length updated by the means is 0, the circuits sequentially connected by the circuit connecting means are output. 5. The automatic circuit generation device is an automatic generation device for a carry-look-ahead circuit, wherein the circuit module storage means has two 1-bit inputs and a higher-order carry input from the lower order. Each information of a first circuit module which is a 1-bit carry look-ahead circuit that outputs a carry to the second circuit module and a second circuit module in which an output buffer is further added to the first circuit module is stored. , The circuit module selection means continuously selects the first circuit modules whose number is smaller than the bit length of the input processing data by one, and further selects one of the second circuit modules. 2. The circuit automatic generation device according to any one of 2 and 4. 6. The automatic circuit generation device is an automatic generation device for a carry look ahead circuit, wherein the circuit module storage means stores a plurality of types of carry look ahead circuit modules having different bit lengths. Each piece of information is stored, and the circuit module selection means selects a suitable circuit from the plurality of types of carry-look-ahead circuit modules so that the different bit lengths are combined to obtain the bit length of the input processing data. 5. The circuit automatic generation device according to claim 1, wherein modules are sequentially selected. 7. A plurality of input means for inputting a circuit operation and a bit length of processed data, and a plurality of connection information between circuits having different operations are further stored in the circuit module storage means. Or a circuit automatic generation device, and information representing a plurality of circuits output by the plurality of circuit automatic generation device, a circuit synthesizing means for synthesizing based on connection information with the circuit of the different operation, An automatic circuit generation device for automatically generating a circuit that performs a predetermined process on data of an arbitrary bit length by appropriately combining a plurality of circuits of operation.