JPH0834450B2 - Data transmission equipment - Google Patents

Data transmission equipment

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Publication number
JPH0834450B2
JPH0834450B2 JP63093738A JP9373888A JPH0834450B2 JP H0834450 B2 JPH0834450 B2 JP H0834450B2 JP 63093738 A JP63093738 A JP 63093738A JP 9373888 A JP9373888 A JP 9373888A JP H0834450 B2 JPH0834450 B2 JP H0834450B2
Authority
JP
Japan
Prior art keywords
coefficient
signal
error rate
decision feedback
data transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63093738A
Other languages
Japanese (ja)
Other versions
JPH01264418A (en
Inventor
光一 本間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63093738A priority Critical patent/JPH0834450B2/en
Publication of JPH01264418A publication Critical patent/JPH01264418A/en
Publication of JPH0834450B2 publication Critical patent/JPH0834450B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ディジタル移動通信等に利用するデータ伝
送装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device used for digital mobile communication and the like.

従来の技術 従来、この種のデータ伝送装置は、第2図に示すよう
に、送信形Tにおいては、第3図(1)に示すような送
信データS1が入力端子1から入力すると例えばASK(Amp
litudeShift Keying)変換器(MOD)2を用いた場合、
第3図(2)に示すような変調信号S2に変調され、増幅
器(Amp)3により増幅後、送信アンテナ4を介して送
信される。
2. Description of the Related Art Conventionally, as shown in FIG. 2, in the data transmission apparatus of this type, in the transmission type T, when transmission data S 1 as shown in FIG. (Amp
When using the litudeShift Keying) converter (MOD) 2,
The modulated signal S 2 as shown in FIG. 3 (2) is modulated, amplified by the amplifier (Amp) 3, and then transmitted via the transmission antenna 4.

他方、受信側R0が受信アンテナ5を介して、この信号
を直接受信するとともにビルB等により反射、遅延した
信号を受信して、増幅器(Amp)6により増幅すると、
この受信信号S3は第3図(3)に示すような歪(マルチ
パス歪)を有する波形となり、次いで復調器(DEM)7
により復調されると、その復調信号S4は第3図(4)に
示すように、マルチパルス歪を有する波形となる。
On the other hand, when the receiving side R 0 receives this signal directly via the receiving antenna 5, receives the signal reflected and delayed by the building B, etc., and amplifies it by the amplifier (Amp) 6,
The received signal S 3 has a waveform having distortion (multipath distortion) as shown in FIG. 3C, and then the demodulator (DEM) 7
When demodulated by, the demodulated signal S 4 has a waveform having multi-pulse distortion as shown in FIG. 3 (4).

尚、このマルチパルス歪は、種々の障害物により反射
した電波が遅延差をもって互いに打ち消し合ったり、増
強されたりする(遅延差が歪の主要因になって歪が生じ
る状況を特に周波数選択性フェージングと呼ぶ。)ため
に生じる。
In addition, this multi-pulse distortion is such that radio waves reflected by various obstacles cancel each other with a delay difference or are strengthened (especially in a situation where the delay difference is a main factor of distortion and causes distortion, frequency selective fading It occurs because of.

このマルチパルス歪を有する復調信号S4はマルチパル
スによる遅延時間の分散がデータ伝送間隔より長い場合
には遅延器(D)8,9,10,乗算器11,12,13と14の加算器
よりなる線形等化器と、遅延器16,17,18、乗算器19,20,
21と加算器14より成る判定帰還形等化器と、比較器15及
び係数更新器23により第3図(5)に示すようにマルチ
パルス歪のない信号S5となる。
The demodulated signal S 4 having this multi-pulse distortion is an adder of delay devices (D) 8, 9, 10 and multipliers 11, 12, 13 and 14 when the dispersion of the delay time due to the multi-pulse is longer than the data transmission interval. Linear equalizer consisting of, delay device 16,17,18, multiplier 19,20,
A decision feedback equalizer composed of 21 and an adder 14, a comparator 15 and a coefficient updater 23 produce a signal S 5 without multipulse distortion as shown in FIG. 3 (5).

次いで、この信号S5は比較器15により「0」又は
「1」に判定され、受信データが復元される。
Then, the signal S 5 is judged to be “0” or “1” by the comparator 15, and the received data is restored.

上記従来例における誤り率は、第4図に示すように、
マルチパルス歪によって静特性C1が動特性C2に劣化して
も特性C3に改善され、S/Nを大きくすることによって誤
り率をいくらでも小さくできるようになる。
The error rate in the above conventional example is, as shown in FIG.
Even if the static characteristic C 1 is deteriorated to the dynamic characteristic C 2 by the multi-pulse distortion, the characteristic C 3 is improved, and the error rate can be reduced as much as possible by increasing the S / N.

発明が解決しようとする課題 しかしながら、上記従来のデータ伝送装置では、SN比
が小さくなり誤り率がある値より大きくなると判定帰還
形等化器が発散し、誤り率を急激に劣化させるという問
題があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-mentioned conventional data transmission apparatus, when the SN ratio becomes smaller and the error rate becomes larger than a certain value, the decision feedback equalizer diverges, which causes a problem that the error rate is rapidly deteriorated. there were.

課題を解決するための手段 本発明は上記目的を達成するために、誤り率を検出す
る手段を設け、誤り率が所定値以上のときに、判定帰還
形等化器の係数更新を停止するようにしたものである。
Means for Solving the Problems In order to achieve the above object, the present invention is provided with a means for detecting an error rate, and when the error rate is equal to or more than a predetermined value, the coefficient updating of a decision feedback equalizer is stopped. It is the one.

作用 したがって、本発明によれば、誤りがある値より悪化
した場合、判定帰還形等化器の係数更新を止めることに
よりその発散を防止できるので、誤りがある値より多い
場合の誤り特性を改善することができる。
Effect According to the present invention, therefore, when the error becomes worse than a certain value, the divergence can be prevented by stopping the coefficient update of the decision feedback equalizer, so that the error characteristic when there are more errors than the value is improved. can do.

実施例 第1図は本発明の一実施例を示すものであり、図示左
方は送信側Tを示し、図示右方は受信側Rを示す。
Embodiment FIG. 1 shows an embodiment of the present invention, in which the left side of the drawing shows a transmitting side T and the right side of the drawing shows a receiving side R.

第1図の送信側Tにおいて、25は、送信データS1の入
力端子、26は、この送信データS1を変調する変調器(MO
D)、27は、変換器26により変調された送信データS2
増幅する増幅器(Amp)、28は増幅器27からの送信デー
タを送信する送信アンテナである。
In the transmission side T of FIG. 1, 25 is an input terminal for the transmission data S 1 , and 26 is a modulator (MO that modulates the transmission data S 1).
D), 27 are amplifiers (Amps) for amplifying the transmission data S 2 modulated by the converter 26, and 28 is a transmission antenna for transmitting the transmission data from the amplifier 27.

第1図の受信側Rにおいて、29は、送信側T等からの
データを受信する受信アンテナ、30は、受信アンテナ29
を介して受信した変調信号を増幅する増幅器(Amp)、3
1は、増幅器30からの変調信号S3を復調する復調器(DE
M)、32は、復調器31からの復調信号S4をサンプル毎に
遅延する遅延器、33は遅延器32からのサンプルnの出力
信号r1 (n)をサンプル毎に遅延する遅延器、34は、遅延
器33からの出力信号r2 (n)をサンプル毎に遅延して信号r
3 (n)を出力する遅延器である。
In the receiving side R of FIG. 1, 29 is a receiving antenna for receiving data from the transmitting side T, and 30 is a receiving antenna 29.
Amplifier (Amp), which amplifies the modulated signal received via
1 is a demodulator (DE that demodulates the modulated signal S 3 from the amplifier 30).
M), 32 is a delay device that delays the demodulated signal S 4 from the demodulator 31 for each sample, 33 is a delay device that delays the output signal r 1 (n) of the sample n from the delay device 32 for each sample, 34 delays the output signal r 2 (n) from the delay unit 33 for each sample and
This is a delay device that outputs 3 (n) .

また、35は、遅延器32の出力信号r1 (n)に係数γ1 (n)
を乗算する乗算器、36は、遅延器33の出力信号r2 (n)
係数γ2 (n)を乗算する乗算器、37は、遅延器34の出力信
号γ3 (n)に係数γ3 (n)を乗算する乗算器であり、それぞ
れの出力信号は加算器38に入力される。これら遅延通話
32,33,34,乗算器,35,36,37,加算器38は、線形等化器(3
2〜38)を構成している。
Further, 35 is a coefficient γ 1 (n) in the output signal r 1 (n) of the delay device 32.
Is a multiplier for multiplying the output signal r 2 (n) of the delay unit 33 by a coefficient γ 2 (n) , and 37 is a multiplier for multiplying the output signal γ 3 (n) of the delay unit 34 by a coefficient γ 3 (n). It is a multiplier that multiplies 3 (n) , and each output signal is input to the adder 38. These delayed calls
32, 33, 34, multiplier, 35, 36, 37, adder 38 are linear equalizers (3
2 to 38).

39は、加算器38の出力信号を判定して「0」又は
「1」の受信データに復元する比較器、40は、比較器39
の出力信号をサンプル毎に遅延する遅延器、41は、遅延
器40の出力信号S1 (n)をサンプル毎に遅延する遅延器、4
2は、遅延器41の出力信号S2 (n)をサンプル毎に遅延して
信号S3 (n)を出力する遅延器、43は、遅延器40の出力信
号S1 (n)に係数b1 (n)を乗算する乗算器、44は、遅延器41
の出力信号S2 (n)に係数b2 (n)を乗算する乗算器、45は遅
延器42の出力信号S3 (n)に係数b3 (n)を乗算する乗算器で
あり、それぞれの出力信号は加算器38に入力される。
39 is a comparator that determines the output signal of the adder 38 and restores the received data of "0" or "1", and 40 is a comparator 39
A delay device that delays the output signal of the sample for each sample, 41 is a delay device that delays the output signal S 1 (n) of the delay device 40 for each sample, 4
2 is a delay device that delays the output signal S 2 (n) of the delay device 41 for each sample to output a signal S 3 (n) , and 43 is a coefficient b to the output signal S 1 (n) of the delay device 40. Multiplier for multiplying 1 (n) , 44 is a delay unit 41
Is a multiplier that multiplies the output signal S 2 (n) of the delay b by the coefficient b 2 (n) , and 45 is a multiplier that multiplies the output signal S 3 (n) of the delay device 42 by the coefficient b 3 (n). Is output to the adder 38.

尚、これら遅延器40,41,42、乗算器43,44,45、加算器
38は判定帰還形等化器(38,40〜45)を構成している。
In addition, these delay devices 40, 41, 42, multipliers 43, 44, 45, adder
The reference numeral 38 constitutes a decision feedback equalizer (38, 40 to 45).

また、46は、加算器38の出力信号と比較通話39の出力
の逆極性信号を加算して信号e(n)を出力する加算器、47
は加算器46の出力信号e(n)と次式 γ1 (n+1)=γ1 (n)+αr1 (n)e(n) γ2 (n+1)=γ2 (n)+αr2 (n)e(n) γ3 (n+1)=γ3 (n)+αr3 (n)e(n) b1 (n+1)=b1 (n)+βS1 (n)e(n) b2 (n+1)=b2 (n)+βS2 (n)e(n) b3 (n+1)=b3 (n)+βS3 (n)e(n) により、それぞれ乗算器35,36,37の次のサンプルの係数
γ1 (n+1),γ2 (n+1),γ3 (n+1)と、係数選択器49に出力
する係数b10 (n+1),b20 (n+1),b30 (n+1)を更新する係数
更新器である。49は、増幅器30で検出した入力信号レベ
ルに対応する信号により係数b1,0 (n+1),b2,0 (n+1),b
3,0 (n+1)を係数b1 (n+1),b2 (n+1),b3 (n+1)として用い
るか、又は元の係数b1 (n),b2 (n),b3 (n)をそのまま用
いるかを決定し、乗算器43,44、45の係数端子に出力す
る係数選択器(SEL)、48は、比較器39からの等化、復
元された受信データの出力端子である。
Also, 46 is an adder for adding the output signal of the adder 38 and the reverse polarity signal of the output of the comparison call 39 to output a signal e (n) , 47
Is the output signal e (n) of the adder 46 and the following equation γ 1 (n + 1) = γ 1 (n) + αr 1 (n) e (n) γ 2 (n + 1) = γ 2 (n) + αr 2 (n) e (n) γ 3 (n + 1) = γ 3 (n) + αr 3 (n) e (n) b 1 (n + 1) = b 1 (n) + βS 1 (n) e ( n) b 2 (n + 1) = b 2 (n) + βS 2 (n) e (n) b 3 (n + 1) = b 3 (n) + βS 3 (n) e (n) The coefficients γ 1 (n + 1) , γ 2 (n + 1) and γ 3 (n + 1) of the next sample of the converters 35, 36 and 37 and the coefficient b 10 (n + ) output to the coefficient selector 49. This is a coefficient updater that updates 1) , b 20 (n + 1) , and b 30 (n + 1) . 49 indicates coefficients b 1,0 (n + 1) , b 2,0 (n + 1) , b depending on the signal corresponding to the input signal level detected by the amplifier 30.
Use 3,0 (n + 1) as the coefficients b 1 (n + 1) , b 2 (n + 1) and b 3 (n + 1) , or use the original coefficients b 1 (n) and b 2 ( n) and b 3 (n) are used as they are, and the coefficient selectors (SEL) and 48 for outputting to the coefficient terminals of the multipliers 43, 44 and 45 are equalized and restored from the comparator 39. This is an output terminal for receiving data.

次に、上記構成に係る実施例の動作を説明する。 Next, the operation of the embodiment having the above configuration will be described.

第1図に送信側Tにおいて、送信データS1が入力端子
25に入力すると、変調器26により変調の後その変調信号
S2が増幅器30で増幅され、送信アンテナ28を介して送出
される。
In FIG. 1, on the transmitting side T, the transmission data S 1 is input terminal
Input to 25 and then modulated by modulator 26
S 2 is amplified by the amplifier 30 and sent out via the transmitting antenna 28.

他方、受信側Rが受信アンテナ29を介し、この信号を
直接受信するとともにビルB等による反射信号を受信す
る。この場合、この遅延差はデータ伝送間隔より長いも
のとする。
On the other hand, the receiving side R directly receives this signal via the receiving antenna 29 and also receives a reflected signal from the building B or the like. In this case, this delay difference is longer than the data transmission interval.

受信アンテナ29を介して入力した信号は増幅器30によ
り増幅され、復調器31により復調され線形等化器(32〜
38)、判定帰還形等化器(38,40〜45)、比較器39、加
算器46、係数更新器47、係数選択器49により受信データ
に復号され、出力端子48に出力される。
The signal input via the receiving antenna 29 is amplified by the amplifier 30, demodulated by the demodulator 31 and linearly equalized (32 to
38), a decision feedback equalizer (38, 40 to 45), a comparator 39, an adder 46, a coefficient updater 47, and a coefficient selector 49, which decode the received data and output it to an output terminal 48.

この場合、係数選択器49は、増幅器30で得られた信号
入力レベルに対応する信号(この信号で誤り率を推定)
をもとにその値がある設定値より小さい(誤り率が所定
の値以上)時、係数更新器47からの判定帰還形等化器へ
係数b1,0 (n+1)〜b3,0 (n+1)の代りに、元のある設定値よ
り大きい時の値に置き換え、判定帰還形等化器(38,40
〜45)の発散を防止する。
In this case, the coefficient selector 49 outputs a signal corresponding to the signal input level obtained by the amplifier 30 (the error rate is estimated by this signal).
When the value is smaller than a certain set value (error rate is a predetermined value or more) based on, the coefficient b 1,0 (n + 1) to b 3, from the coefficient updater 47 to the decision feedback equalizer. Instead of 0 (n + 1) , it is replaced with a value when it is larger than a certain set value, and the decision feedback equalizer (38,40
~ 45) to prevent divergence.

第4図に示すようにマルチパルス歪がない場合の静特
性C1は、その歪があると動特性C2のようにS/Nが改善さ
れても誤り率がある値より良くならず、これに線形及び
判定帰還形等化器(32〜38,40〜45)を付加しマルチパ
ス歪を補償すると特性C3まで改善できる。しかしS/Nが
ある程度よく、誤り率がある値より良い場合には良好な
誤り率特性を得ることができるが、S/Nがそれ以下にな
ると判定帰還形等化器(38,40〜45)が発散してしま
い、誤り率特性が急激に劣化する。本発明はこの劣化を
防ぐものであり、誤り率がある設定値より悪くなると判
定帰還形等化器(38,40〜45)の係数の更新を止めるこ
とによって発散を止め、特性C4に示すように、全てのS/
N値につき良好な誤り特性を得ることができる。
As shown in FIG. 4, the static characteristic C 1 when there is no multi-pulse distortion does not become better than the value with an error rate even if the S / N is improved like the dynamic characteristic C 2 when the distortion exists. If linear and decision feedback equalizers (32 to 38, 40 to 45) are added to this and multipath distortion is compensated for, characteristic C 3 can be improved. However, if the S / N is good to some extent and the error rate is better than a certain value, a good error rate characteristic can be obtained, but if the S / N becomes less than that, the decision feedback equalizer (38, 40 ~ 45 ) Is diverged, and the error rate characteristic deteriorates rapidly. The present invention prevents this deterioration, and stops the divergence by stopping the update of the coefficient of the decision feedback equalizer (38, 40 to 45) when the error rate becomes worse than a certain set value, and the characteristic C 4 is shown. Like all S /
A good error characteristic can be obtained for each N value.

発明の効果 本発明は上記実施例より明らかなように、誤り率があ
る設定値より悪化した時判定帰還形等化器の係数更新を
停止させてその発散を防止し、全てのS/Nに渡って良好
な誤り率特性を得ることができるという利点を有する。
EFFECTS OF THE INVENTION The present invention, as is clear from the above embodiment, prevents the divergence by stopping the coefficient update of the decision feedback type equalizer when the error rate becomes worse than a certain set value, and all S / N There is an advantage that a good error rate characteristic can be obtained throughout.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本発明に係るデータ伝送装置の一実施例を示
すブロック図、第2図は、従来例のデータ伝送装置を示
すブロック図、第3図は、第1図及び第2図の装置の主
要信号を示す波形図、第4図は、受信信号のSN比対誤り
率特性図である。 25…送信データの入力端子、26…変調器、27…増幅器
(Amp)、28…送信アンテナ、29…受信アンテナ、30…
増幅器、31…復調器(DEM)、32,33,34…遅延器、35,3
6,37…乗算器、38…加算器、39…比較器、40,41,42…遅
延器、43,44,45…乗算器、46…加算器、47…係数更新
器、48…受信データ出力端子、49…係数選択器(SE
L)。
FIG. 1 is a block diagram showing an embodiment of a data transmission device according to the present invention, FIG. 2 is a block diagram showing a conventional data transmission device, and FIG. 3 is a block diagram of FIG. 1 and FIG. FIG. 4 is a waveform diagram showing a main signal of the apparatus, and FIG. 4 is an SN ratio versus error rate characteristic diagram of a received signal. 25 ... Transmission data input terminal, 26 ... Modulator, 27 ... Amplifier (Amp), 28 ... Transmission antenna, 29 ... Reception antenna, 30 ...
Amplifier, 31 ... Demodulator (DEM), 32, 33, 34 ... Delay device, 35, 3
6, 37 ... Multiplier, 38 ... Adder, 39 ... Comparator, 40, 41, 42 ... Delay device, 43, 44, 45 ... Multiplier, 46 ... Adder, 47 ... Coefficient updater, 48 ... Received data Output terminal, 49 ... Coefficient selector (SE
L).

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】受信変調信号を復調する復調器と、前記復
調器により復調された信号を係数によりそれぞれ等化す
る線形等化器及び判定帰還形等化器と、前記係数を更新
する係数更新器と、受信変調信号の誤り率が所定値以上
か否かを検出し、所定値以上の場合に前記判定帰還形等
化器の係数更新を停止するように前記係数更新器を制御
する手段とを有するデータ伝送装置。
1. A demodulator for demodulating a received modulated signal, a linear equalizer and a decision feedback equalizer for equalizing the signal demodulated by the demodulator with a coefficient, and a coefficient updating for updating the coefficient. And a means for controlling the coefficient updater so as to detect whether the error rate of the received modulated signal is a predetermined value or more and stop the coefficient update of the decision feedback equalizer when the error rate is a predetermined value or more. Data transmission device having a.
JP63093738A 1988-04-15 1988-04-15 Data transmission equipment Expired - Fee Related JPH0834450B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63093738A JPH0834450B2 (en) 1988-04-15 1988-04-15 Data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63093738A JPH0834450B2 (en) 1988-04-15 1988-04-15 Data transmission equipment

Publications (2)

Publication Number Publication Date
JPH01264418A JPH01264418A (en) 1989-10-20
JPH0834450B2 true JPH0834450B2 (en) 1996-03-29

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Application Number Title Priority Date Filing Date
JP63093738A Expired - Fee Related JPH0834450B2 (en) 1988-04-15 1988-04-15 Data transmission equipment

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Country Link
JP (1) JPH0834450B2 (en)

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JP5232677B2 (en) * 2009-02-02 2013-07-10 日本放送協会 Digital transmission decoder and receiver
JP5256073B2 (en) * 2009-02-19 2013-08-07 日本放送協会 Digital transmission system transmitter, receiver, and transmitter / receiver

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JPS573242A (en) * 1980-06-03 1982-01-08 Victor Co Of Japan Ltd Reel motor driving circuit for high-speed playback
JPS6016129A (en) * 1983-07-08 1985-01-26 日本電気株式会社 Power source resetting circuit
JPH0630460B2 (en) * 1984-09-27 1994-04-20 株式会社東芝 Automatic equalizer
JPS61116432A (en) * 1984-10-18 1986-06-03 Fujitsu Ltd Automatic equalizer
JPS62284511A (en) * 1986-06-02 1987-12-10 Hitachi Denshi Ltd Adaptive digital filter

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