JPH0834215B2 - Semiconductor device - Google Patents

Description

The present invention relates to a structure of a semiconductor device, and more particularly to a structure that is fine and suitable for high speed operation.

[Conventional technology]

An example of a conventional semiconductor device is described in JP-A-58-73156. The bipolar transistor disclosed here has a sectional structure as shown in FIG. That is, the electrode of the base region 4 is taken out by the polycrystalline semiconductor layer 6 sandwiched by the insulating films 7, 8 and 9. Since this transistor structure has no external base region, the parasitic capacitance is small, so that it has a merit at high speed, and the active region can be determined by one photo-process.

[Problems to be solved by the invention]

However, in the above-mentioned conventional technique, the polycrystalline semiconductor layer 6 previously doped with the p-type impurity is in contact with the side surface of the convex semiconductor, and the p + type region 14 is isotropically diffused from the side surface of the n-type epitaxial layer 3 so that n + Since it is close to the mold burying layer 2, the breakdown voltage between the base and the collector is lowered, and the junction capacitance thereof is increased to prevent the speedup. This problem becomes more remarkable as the thickness of the n-type epitaxial layer 3 is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device such as a bipolar transistor which can improve the above-mentioned problems of the conventional semiconductor device, can operate at a high speed, have a high breakdown voltage, and can reduce the vertical dimension of the device.

[Means for solving problems]

Therefore, in the present invention, in order to achieve the above object, a semiconductor substrate of a first conductivity type, and a third region of a second conductivity type opposite to the first conductivity type provided in a surface region of the substrate,
A first insulating film provided on the surface of the substrate and having an opening on the third region, a first region of the first single crystal semiconductor layer provided on the opening, and the first region. A second insulating film provided on a side surface, a second insulating film provided on the first insulating film and adjacent to the second insulating film, and on the surface of the first region with a constant inner surface of the second insulating film. A second single crystal or polycrystalline semiconductor layer which is in contact only with the region, an insulator layer provided adjacent to the second single crystal or polycrystalline semiconductor layer, and a first layer provided in the first region The fifth region of conductivity type and the fifth region
A sixth region of the second conductivity type provided in the region;
And a second region of the first conductivity type provided in the single crystal or polycrystalline semiconductor.

In other words, since there is an insulating film on the side surface of the convex single crystal semiconductor layer, there is no first conductivity type region, and only the peripheral portion of the convex single crystal semiconductor layer surface is electrically connected to the single crystal or polycrystalline semiconductor layer. A structure is provided in which a first conductivity type region to be connected is provided.

[Action]

With this structure, the first-conductivity type region connected to the single crystal or polycrystalline semiconductor layer and the high-concentration second-conductivity type buried layer (the third
It is possible to increase the distance between the regions, the capacitance between the base and collector of the bipolar transistor can be reduced, and the speed can be increased. Further, the breakdown voltage can be improved. Further, the present invention is effective for high integration of the device because the active region and the isolation region can be determined by one photo process.

〔Example〕

 Hereinafter, a detailed description will be given with reference to embodiments of the present invention.

Embodiment 1 FIG. 1 shows a sectional structure of a semiconductor device according to a first embodiment of the present invention.

This embodiment shows an example of a bipolar transistor, an insulating film 77 is provided on the side surface of the convex single crystal semiconductor layer 3, and the polycrystalline semiconductor 6 is connected only at the peripheral portion of the surface of the convex single crystal semiconductor layer 3. It is a structure that does. Therefore, the p + type region 14 diffused from the polycrystalline semiconductor layer 6 previously doped with impurities can be formed only in the vicinity of the surface, and since it does not approach the n + type buried layer 2, parasitic capacitance can be reduced and high speed can be obtained. To be It is also possible to improve the breakdown voltage. The side surface of the p + type region 14 is an insulating film.
Since it is in contact with 77, the junction is only on the bottom surface and the capacity is reduced. Furthermore, this structure is effective in reducing the element area because the diffusion layers 4, 5 and 14 inside the active region, the electrodes 12 and the like are determined by a single photo step for determining the convex single crystal semiconductor layer 3.

FIGS. 3A to 3E are cross-sectional views showing the manufacturing process of the bipolar transistor of the first embodiment shown in FIG. The manufacturing process will be described below with reference to the drawing numbers.

FIG. 3 (a): An n + type buried diffusion layer 2 is formed on a p type Si substrate 1, an n type Si epitaxial layer 3 having a thickness of 1 μm and a specific resistance of about 1 Ω · cm is grown, and silicon is formed on the entire surface. The oxide film 101, an insulating film other than the silicon oxide film, for example, a silicon nitride film (Si
₃ N ₄ ) 102 and silicon oxide film 103 are deposited and patterned to leave three layers 101, 102 and 103 only in the active portion A and the collector electrode extraction portion B of the transistor.

FIG. 3 (b): The silicon epitaxial layer is etched to a depth of about 0.5 μm using the three-layer insulating films 101, 102 and 103 as masks so that the active portion and the collector electrode extraction portion are convex. After that, thermal oxidation is performed to form a silicon oxide film 77, a silicon nitride film (Si ₃ N ₄ ) is deposited on the entire surface, and the silicon nitride film 104 is left only on the side surface of the convex silicon layer by selective etching. Where oxide film 7
The film 7 is formed to be about 2-3 times thicker than the oxide film 101.

FIG. 3C: Thermal oxidation is performed to form an oxide film 7. After that, the silicon nitride film 104 is removed. At this time, the silicon nitride film 102 is side-etched so that the silicon nitride film 102 is located inside the surface end of the convex silicon layer. Next, an oxide film etching is performed by a thickness corresponding to the oxide film 101 to form a silicon opening 200 only at the surface end of the convex silicon layer. Here, the oxide film 101 is left at the collector electrode extraction portion using a mask, but it is not necessary to perform patterning for etching.

FIG. 3D: A polycrystalline silicon layer is formed on the entire surface and patterned so that only the end face 200 of the convex portion of the epitaxial layer is in contact with the polycrystalline silicon layer 50.

FIG. 3E: A silicon oxide film 100 and a silicon nitride film 111 are formed on the entire surface and patterned. Next, using the patterned two-layer insulating films 110 and 111 as masks, a part of the polycrystalline silicon is made into the oxide film 8 by thermal oxidation. After that, an n + type high concentration impurity is added to the collector electrode extraction semiconductor layer 38.

After that, the silicon oxide film 110 and the silicon nitride film 111 are removed, p-type impurities are diffused into the polycrystalline silicon layer 50 to form a p-type diffusion layer 14, and then thermal oxidation is performed to form an oxide film 9. . Then, the base region 4 and the emitter region 5 of the transistor are formed by a usual method, contact holes are formed in the oxide film, and the electrodes 11, 12, and 13 are vapor-deposited to form the device shown in FIG.

The above is the first embodiment of the present invention and the manufacturing method thereof. According to this manufacturing method, it is possible to perform self-alignment from the isolation region of the element to the formation of the emitter electrode by one photo process. The width of the external base region is determined by the amount of side etching of the silicon nitride film, and can be a minute region of 0.2 μm or less.

Although the above is the main part of the present invention, another method of manufacturing the structure of the present invention is shown in FIGS. 4 (a) to 4 (c).

FIG. 4 (a): By the same process as that shown in FIG. 3 (a), a three-layer film 301, 302, 303 is formed only in the active portion A and the collector electrode extraction portion B of the transistor and thermally oxidized to form a silicon oxide film 304. . Here, the thickness of the oxide film 304 is set to 1/2 to 1/3 of that of the oxide film 301.

FIG. 4B: A silicon nitride film is deposited on the entire surface, and the silicon nitride film 310 is left only on the side surfaces of the three-layer films 301, 302 and 303 by selective etching. The oxide film 304 is removed by etching so that the oxide film 304 remains only under the silicon nitride film 310 around the three-layer films 301, 302 and 303. Using the three-layer films 301, 302, 303 and the silicon nitride film 310 as a mask, the silicon epitaxial layer is etched to a depth of about 0.5 μm so that the active portion and the collector electrode extraction portion are convex. Then, thermal oxidation is performed to form a silicon oxide film 305, a silicon nitride film is deposited on the entire surface, and selective etching is used to form the silicon nitride film 311 only on the side surface of the convex silicon layer.
Leave. Here, the oxide film 305 has a thickness equivalent to that of the oxide film 301 and is formed to be about 2 to 3 times thicker than the oxide film 304.

FIG. 4C: Thermal oxidation is performed to form an oxide film 307, and the silicon nitride films 310 and 311 are removed. After that, etching of an oxide film is performed by a thickness corresponding to the oxide film 304 to form a silicon opening 200 only at the surface end of the convex silicon layer.

If this manufacturing method is used, the width of the opening 200 becomes smaller than that of the silicon nitride film 3.
Since it is determined by the thickness of 10, it can be controlled with high precision.

After FIG. 4 (c), the element shown in FIG. 1 can be formed by the same steps as shown in FIG. 3 (d) (e).

Embodiment 2 FIG. 5 shows a cross-sectional structure when the present invention is applied to a lateral bipolar transistor, in which the electrodes of the emitter / collector region 14 are sandwiched by insulating films 77, 7, 8 and 9 to form another crystal. The portions of the polycrystalline semiconductor layer 6 that are taken out and connected to the single crystal silicon are the end portions of the convex silicon surface. As a result, the junction capacitance between the emitter and the collector can be reduced, the single crystal semiconductor layer can be thinned, and a high speed and fine transistor can be formed. Although the base electrode 33 is taken out through the n + type buried layer 2 in this figure, the base electrode may be formed by forming the n type diffusion layer 5 on the surface of the convex silicon layer as shown in FIG. . This is n
The + buried layer may be provided only under the convex silicon layer, and the n + buried amount and the junction capacitance with the substrate can be reduced, and the transistor can be miniaturized.

Embodiment 3 FIG. 6 shows a sectional structure when the present invention is applied to a MOS, and the source / drain regions 14 can be realized with a minute width and by self-alignment. In this figure, the n-type Si substrate 1000
Although the n-type epitaxial layer 3 is provided on the n-type epitaxial layer 3, the n-type epitaxial layer 3 is not particularly necessary and can be formed only by the n-type Si substrate 1000.

Further, as shown in FIG. 1, the n + type buried layer 2 may be provided on the p type Si substrate 1.

Embodiment 4 In FIG. 7, a high speed, low power consumption transistor is formed by forming a metal or a metal compound (WSi ₂ etc.) on a polycrystalline silicon layer and reducing the wiring resistance.

Fifth Embodiment FIG. 8 shows that in the device structure according to the present invention, a polycrystalline silicon layer 70 is provided on the emitter to prevent metal atoms in the electrode 12 from penetrating into the base region 4, thereby making the emitter region 5 shallow ( 0.1-0.2 μm). high speed,
Fine transistors are possible.

In each of the above-described first to fifth embodiments, any some or all of them can be used. Further, the device of the present invention can be realized by using another semiconductor such as GaAs as a semiconductor. Further, it goes without saying that the p-type and n-type conductivity types in each embodiment can be used in reverse.

〔The invention's effect〕

According to the present invention, it is possible to provide a transistor and an integrated circuit with high-speed operation, high integration, and high breakdown voltage.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a bipolar transistor which is an embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view showing the structure of a conventional bipolar transistor, FIGS. 3 (a) to 3 (e) and 4 (a) to 4 (c) are sectional views showing the manufacturing process of the bipolar transistor according to the present invention.
5, 6, 7, and 8 are sectional views showing another embodiment of the semiconductor device of the present invention. 1 ... p-type Si substrate, 2 ... n + type buried layer, 3 ... n-type Si substrate
Epitaxy layer, 4,14 …… p-type diffusion layer, 5,10,33 ……
n-type diffusion layer, 6,50,70 ... Polycrystalline Si layer, 7,8,9,30,40,77,
101,103,110,301,303,304,305,307 …… Oxide film, 11,12,1
3,31,22,33,41,42,43,51,52,53 …… electrode, 60 …… metal or metal compound, 102,104,111,302,310,311 …… silicon nitride film, 200 …… opening, 1000 …… n type Si substrate.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 29/78 H01L 29/20 29/78 9055-4M 652 L (72) Inventor Katsunada Horiuchi Tokyo 1-280, Higashi Koigakubo, Kokubunji City, Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Tetsuya Hayashida 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi Ltd.

Claims (13)

[Claims] 1. A semiconductor substrate, a first insulating film having an opening provided on the surface of the substrate, a first region of a first single crystal semiconductor layer provided on the opening, and A second insulating film provided on a side surface of the first region, a second insulating film provided on the first insulating film and adjacent to the second insulating film, and a second insulating film provided on the surface of the first region. A second single crystal or polycrystalline semiconductor layer that is in contact only with a certain region inside, and the second
7. A semiconductor device having an insulating layer provided adjacent to the single crystal or polycrystalline semiconductor layer. 2. The semiconductor substrate and the first single crystal semiconductor layer have a first conductivity type, and a second conductivity type provided in the second single crystal or polycrystalline semiconductor layer and having an opposite conductivity type to the first conductivity type. The semiconductor device according to claim 1, wherein a second region of two conductivity type is provided. 3. The semiconductor substrate having a first conductivity type, the semiconductor substrate having a third region of a second conductivity type opposite to the first conductivity type provided on the surface of the substrate, the first insulation The film opening is located on the third region, and the first single crystal semiconductor layer is located on the second region.
The semiconductor device according to claim 1, wherein the semiconductor device is of a conductivity type. 4. The semiconductor device according to claim 3, further comprising a second region of the first conductivity type provided in the second single crystal or polycrystalline semiconductor layer. 5. An insulating film provided on the surface of the first single crystal semiconductor layer and an electrode provided on the insulating film, wherein the second region serves as a source and a drain region, and the electrode is a gate. The semiconductor device according to claim 2 or 4, wherein the region is formed by a MOS transistor. 6. A semiconductor device according to claim 2, wherein the second region serves as a collector and an emitter region, and the semiconductor substrate serves as a base region to form a bipolar transistor. 7. A semiconductor device according to claim 4, wherein the second region is a collector and an emitter region, and the third region is a base region to form a bipolar transistor. 8. A fourth region of the second conductivity type provided on the surface portion in the first region, wherein the second region is a collector and an emitter region, and the first region is formed by the first region. 5. The semiconductor device according to claim 4, wherein the region base region is taken out to form a bipolar transistor. 9. A fifth region of the first conductivity type provided in the first region, and a sixth region of the second conductivity type provided in the fifth region. 5. The semiconductor device according to item 4 above. 10. A bipolar transistor is formed by using the third region as a collector region, the second region as an external base region, the fifth region as an internal base region, and the sixth region as an emitter region. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device. 11. The first insulating film has a second opening in another portion on the third region, and a second conductivity type third single crystal semiconductor layer is provided on the opening. The semiconductor device according to claim 7, wherein the base region is taken out by the second conductivity type single crystal semiconductor layer. 12. A bipolar transistor comprising the third region as an emitter region, the second region as an external base region, the fifth region as an internal base region, and the sixth region as a collector region. The semiconductor device according to claim 9, wherein the semiconductor device is a semiconductor device. 13. A method according to claim 5, wherein a metal or a metal compound is provided on the surface of the second single crystal or polycrystalline semiconductor layer. Semiconductor device.