JPH08340240A - Distributed amplifier retiming reproducing circuit - Google Patents

Abstract

PURPOSE: To provide a very high-speed retiming reproducing circuit whose maximum operation speed is higher than heretofore. CONSTITUTION: A unit circuit is constituted of a 1st series transistor(TR) group Q11 and Q14 and a 2nd series TR group Q21 to Q24 in which two TRs are connected in cascade to each other. A 1st data signal is inputted to one terminal of a 1st transmission line X1 and a 2nd data signal with a prescribed time difference from the 1st data signal is inputted to one terminal of a 3rd transmission line X3. In addition, a 1st clock signal is inputted to one terminal of a 2nd transmission line X2 and a 2nd clock signal inverted from the 1st clock signal is inputted to one terminal of a 4th transmission line X4. One terminal of a 5th transmission line X5 is used as an output terminal Dout for a retiming- reproduced data signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a distributed amplification type retiming reproducing circuit for retiming and reproducing an ultra high speed data signal.

[0002]

2. Description of the Related Art A retiming reproduction circuit (identification circuit) is
This circuit is widely used in receiving devices such as optical transmission communication, and is a circuit that removes synchronization deviation and noise of a signal transmitted over a long distance and reproduces a noise-free signal with the same pulse pattern as received data.

FIG. 8 is a diagram showing a configuration of a typical conventional retiming reproducing circuit (identification circuit) 300.

The retiming reproducing circuit 300 uses a D-type flip-flop using a transistor, which is suitable for integration and is therefore widely used as an IC.

[0005]

However, the retiming reproduction circuit 300 has a problem that the upper limit of the speed of the data signal that can be retimed is greatly limited by the performance of the transistor used.

For example, the relation between the maximum operating speed of a conventional IC and the transistor performance is described in the 1995 OFC International Conference.
(E.Sano, Y.IMAI, and H.Ichino, "Lighwave Communica
tionICs for 10 Gb / s and beyond "), and it has been shown that the maximum operating speed is almost 1/4 or less of the figure of merit (cutoff frequency) of the transistor.
Usually, the figure of merit of a transistor is 4 at the maximum for commercial products.
Since it is about 0 GHz and about 100 GHz for the research and development product, about 10 Gb / s for the commercial product IC and about 25 Gb / s for the research and development product IC are considered to be the limits of this kind of circuit. In fact, in the current situation, the commercial product IC is 10G
There is no retiming regeneration circuit having a maximum operating speed of b / s or higher.

An object of the present invention is to provide an ultra-high speed retiming reproducing circuit whose maximum operating speed is faster than conventional ones.

[0008]

According to the first aspect of the present invention,
The two transistors are cascode-connected to form a first series transistor group, and the two transistors different from the two transistors are cascode-connected to form a second series transistor group. A unit circuit is formed by the two series transistor groups, and a source terminal that is one end of the first series transistor group and a source terminal that is one end of the second series transistor group are grounded to form a predetermined unit circuit. The drain terminal that is one end of the first series transistor group and the drain terminal that is one end of the second series transistor group that forms a predetermined unit circuit are commonly connected, and one or more unit circuits are arranged. And each of the first gate terminals of the first series transistor group forming each unit circuit has an inductance or A first transmission line connected via a constant line and a second gate terminal of the first series transistor group forming each unit circuit are connected via an inductance or distributed constant line. The second transmission line, the third transmission line in which each of the first gate terminals of the second series transistor group forming each unit circuit is connected via an inductance or distributed constant line, and each unit circuit A fourth transmission line to which each of the second gate terminals of the second series transistor group that is configured is connected via an inductance or distributed constant line, and a drain terminal that is commonly connected to each unit circuit, respectively. A distributed amplification type retiming regeneration circuit comprising a fifth transmission line connected via an inductance or a distributed constant line, comprising: The first data signal is input to one terminal of the transmission line, and the second data signal obtained by applying a predetermined time difference to the first data signal is input to one terminal of the third transmission line, The first clock signal is input to one terminal of the second transmission line, the second clock signal obtained by inverting the first clock signal is input to one terminal of the fourth transmission line, and the fifth clock signal is input. Is a distributed amplification type retiming reproducing circuit in which one terminal of the transmission line is used as an output terminal of the retiming reproduced data signal.

According to a second aspect of the present invention, the same data signal is input to one terminal of the first transmission line and one terminal of the third transmission line, and the data in the first transmission line is input. A delay circuit for delaying a signal is provided.

[0010]

According to the present invention, the first, second, third, fourth, and fifth transmission lines are equivalent to each other when the inductance component L and the input / output capacitance C of the transistor are appropriately adjusted. Since it is possible to configure an LC transmission line having a characteristic impedance (for example, 50Ω) having a very high cut-off frequency, which is configured by the above and the inductance component of the transmission line, and the influence of the input / output capacitance C of the transistor can be eliminated, The maximum operating speed of the retiming playback circuit is faster than before.

[0011]

1 is a diagram showing a distributed amplification type retiming reproducing circuit 100 according to a first embodiment of the present invention.

In FIG. 1, a transistor Q1I (I = 1,
2, 3, 4, and so on) and the transistor Q2I are cascode-connected to form a first series transistor group, and the transistors Q3I and Q4I are cascode-connected to form a second series transistor group. I am configuring.

In FIG. 1, T1, T2, T3, T4,
T5 is a distributed constant line or inductance, and
1, G2, G3, G4 are the first, second, third, and
A fourth gate terminal, D is a drain terminal, S
Is a source terminal, and X1, X2, X3, X4, X5
Are first, second, third, fourth, and fifth transmission lines, respectively.

Further, a unit circuit is constituted by the first series transistor group and the second series transistor group,
That is, for example, the transistors Q11, Q21, Q3
1 and Q41 form one unit circuit, and, for example, transistors Q12, Q22, Q32, and Q
42 forms another unit circuit.

The source terminal of the first series transistor group and the source terminal of the second series transistor group are grounded,
The drain terminal of the first series transistor group and the drain terminal of the second series transistor group are commonly connected. That is, for example, the source terminal of the transistor Q11 that forms the first series transistor group and the source terminal of the transistor Q31 that forms the second series transistor group are grounded, and the transistor Q21 that forms the first series transistor group is grounded. And a drain terminal of a transistor Q41 forming the second series transistor group are commonly connected.

One of the unit circuits and the unit circuit adjacent thereto have a distributed constant line or inductances T1 and T.
They are connected to each other by 2, T3, T4 and T5. Then, the plurality of distributed constant lines or the inductance T1 constitutes the first transmission line X1, and the plurality of distributed constant lines or the inductance T2 forms the second transmission line X1.
Transmission line X2 is formed, and a plurality of distributed constant lines or inductances T3 form a third transmission line X3, and a plurality of distributed constant lines or inductances T4 are formed.
Constitutes a fourth transmission line X4, and the plurality of distributed constant lines or the inductance T5 constitutes a fifth transmission line X5.

Further, in FIG. 1, Din1 and Din2 are
Input terminals for the first and second data signals, CLKin1, CL
Kin2 is an input terminal for the first and second clock signals, Do
ut is an output terminal of the data signal, and Vd, Vg1,
Vg2, Vg3, and Vg4 are power supply terminals. The termination circuit and the bias circuit are mainly composed of resistors and capacitors, and when viewed from the transmission line, the termination circuit and the bias circuit together make up about 50
It is configured to have an impedance of Ω. The impedance of the termination circuit and the bias circuit as viewed from the transmission line may be set to a value other than 50Ω.

FIG. 2 is a diagram showing the relationship between each terminal of the distributed amplification type retiming reproducing circuit 100 and an external signal.

The same data signal is input to the first data signal input terminal Din1 and the second data signal input terminal Din.
2 and the first data signal input terminal Din
With respect to the signal input to 1, the signal input to the input terminal Din2 of the second data signal is given a time difference of approximately ½ of the cycle of the clock signal. The time difference of about 1/2 of the cycle of the clock signal is due to the input terminal D of the second data signal.
It is generated by the delay circuit Td connected to in2.

The input terminal CL for the first clock signal
The clock signal is input to Kin1, and the inverted clock signal is input to the input terminal CLKin2 of the second clock signal. At this time, the retiming-reproduced data signal is output from the data signal output terminal Dout.

That is, in the distributed amplification type retiming reproducing circuit 100, two transistors are cascode-connected to form a first series transistor group, and two transistors different from the above two transistors are cascode-connected to form a second series transistor. A series circuit is formed, and a unit circuit is formed by the first series transistor group and the second series transistor group, and the source terminal that is one end of the first series transistor group and the second series transistor group The source terminal, which is one end of the series transistor group, is grounded, and the drain terminal, which is one end of the first series transistor group that forms a predetermined unit circuit, and the second series transistor group that forms the predetermined unit circuit. A circuit in which one or a plurality of the above unit circuits are arranged, which are commonly connected to the drain terminal at one end. A.

The distributed amplification type retiming reproducing circuit 1
00 constitutes each unit circuit with a first transmission line to which each of the first gate terminals of the first series transistor group constituting each unit circuit is connected via an inductance or distributed constant line. A second transmission line in which each of the second gate terminals of the first series transistor group is connected via an inductance or distributed constant line, and a second series transistor group of the second series transistor group forming each unit circuit. A third transmission line in which each of the first gate terminals is connected via an inductance or a distributed constant line, and a second gate terminal of the second series transistor group forming each unit circuit has an inductance or Each of the fourth transmission line connected through the distributed constant line and the commonly connected drain terminal of each unit circuit is Chest or distributed constant line is a distributed amplification type retiming recovery circuit; and a fifth transmission line connected via a.

Further, in the distributed amplification type retiming reproducing circuit 100, the first data signal is inputted to one terminal of the first transmission line, and the first data signal is inputted to one terminal of the third transmission line. Of the second transmission line, the first clock signal is input to one terminal of the second transmission line, and the second data signal obtained by applying a predetermined time difference to the data signal of A second clock signal obtained by inverting the first clock signal is input to the terminal, and one terminal of the fifth transmission line is an output terminal of the retiming-reproduced data signal.

Next, the distributed amplification type retiming reproducing circuit 1
The operation of 00 will be described.

FIG. 3 is a diagram showing an equivalent circuit of the first transmission line section X1 in the distributed amplification type retiming reproducing circuit 100.

In FIG. 3, L is the distributed constant line or the inductance component in the inductance T1, C is the input capacitance of the transistor, and Rt is the transmission line X1.
The impedance of the bias circuit and the termination circuit seen from the above, and in this case, the impedance Rt is a pure resistance.

As is apparent from FIG. 3, the first transmission line section X1 is equivalent to the circuit in that the capacitance C component of the transistor is adjusted by appropriately adjusting the inductance component L and the input capacitance C of the transistor. And the inductance component L of the transmission line X1 makes it possible to construct an LC transmission line having a characteristic impedance of 50Ω with a very high cutoff frequency.

The equivalent circuit of the first transmission line section X1 shown in FIG. 3 is basically the transmission line section X2, X3, X.
4 and the equivalent circuit of X5. However, in each equivalent circuit of the transmission line sections X2, X3, X4, and X5, each inductance component L is an inductance component of the distributed constant line or the inductances T2, T3, T4, and T5, and each capacitance C is transmitted. Line parts X2, X3, X4
Is the input capacitance of the transistor, but is the output capacitance of the transistor in the fifth transmission line portion X5. Further, the impedance of the bias circuit and the termination circuit seen from each of the transmission lines X2 to X5 is also Rt, and in this case also, it is a pure resistance.

The second, third, fourth and fifth transmission line portions X2, X
In terms of an equivalent circuit, 3, X4, and X5 also have the capacitance component C of the transistor and the transmission line X by appropriately adjusting the inductance component L and the input / output capacitance C of the transistor.
It is possible to configure an LC transmission line having a characteristic impedance of 50Ω, which has a very high cutoff frequency and is configured by the inductance components L of 2, X3, X4, and X5.

Therefore, the input / output capacitance C of the transistor
The effect of is canceled by being taken in by this transmission line, and the effect of the input / output capacitance C of the transistor is eliminated in this way, so the input signal does not attenuate to a very high frequency and passes through the transmission line. The signal transmitted, reaching the gate terminal of each unit circuit, and emerging from the drain terminal of each unit circuit similarly reaches the output terminal Dout without being attenuated.

The signals input to the respective unit circuits have a time difference corresponding to the delay time t of the transmission line. By adjusting the delays in the respective unit circuits, the output terminal Dout outputs the signals output from the respective unit circuits. There is no time difference and a multiplexed signal is obtained.

To give a numerical example, for example, a gate length of 0.
2 micron, gate width 75 micron GaAs MES
When the FET is used as a transistor and the capacitance C is 0.1 pF, if the characteristic impedance of the transmission line is set to 50Ω for high frequency, the inductance component L becomes about 0.2 nH. The cutoff frequency is about 60 GHz.

Therefore, in the above case, a clock frequency up to about 60 GHz can be used, and N
In the RZ modulation system, the data signal is 60 GHz at 1.4.
It can be used up to double bit rate, and can be expected to operate at extremely high speed.

In the case of a distributed constant line, the inductance component L depends on the line length and the characteristic impedance.
Can be adjusted. In the case of inductance, the inductance component L can be adjusted by adjusting the number of turns.
Can be adjusted. Further, the input / output capacitance C of the transistor can be adjusted by adjusting the gate width and the gate length of the transistor.

FIG. 4 is a diagram showing input / output waveforms in the distributed amplification type retiming reproducing circuit 100.

The respective input waveforms of the first data input terminal Din1 and the second data input terminal Din2 generally have jitter because they are transmitted through a communication transmission path having a long distance. Of this jitter, the jitter in the amplitude direction is eliminated by passing it through a slicer and a limiter, but rising jitter is always present, and Fig. 4 shows an input signal containing this rising jitter. There is.

By the way, in the distributed amplification type retiming reproducing circuit 100, since the input data signal is selected by the clock signal inputted to the CLKin1 and CLKin2 terminals, the jitterless data signal is retiming reproduced and the data output terminal Dout. Is output from.

In the above description, the time difference between the data signal input to the terminal Din1 and the data signal input to the terminal Din2 is ½ of the clock cycle T, but ½ of the clock cycle T. Other time differences can be set.

Next, the reason why the time difference between the data signal input to the terminal Din1 and the data signal input to the terminal Din2 can be set to a time difference other than 1/2 of the clock cycle T is shown in FIG. To explain.

FIG. 5 is a diagram schematically showing signal waveforms at the internal terminals of the distributed amplification type retiming reproduction circuit 100.

Transistors Q11, Q21, Q31, Q
Each of the gate terminals of 41 has a first data input terminal Din1, a first clock input terminal CLKin1,
The signal waveforms of the second data input terminal Din2 and the second clock input terminal CLKin2 arrive with a delay of the transmission line delay t / 2 ((1), (2), (4) in FIG. 5).
(5)). When a high voltage is simultaneously applied to the gate terminals of the drain terminals of the transistors Q11 and Q21, a current flows through the cascode-connected transistor group, and the voltage of the drain terminals decreases.

Further, this operation is performed by the transistors Q31,
The same occurs in Q41. Therefore, now
Transistors Q11, Q21 (or transistor Q3
1 and Q41), the signal waveforms at the drain terminal are as shown in FIGS. 5 (3) and 5 (6). However, actually, the transistors Q11, Q
Since the drain terminals of 21 and Q31 and Q41 are commonly connected, a signal waveform as shown in FIG. 5 (7) is generated at the terminal O1.

Therefore, the input data signal is selected by the clock signal and retimed. In FIG. 5, the time difference between the two data signals is T / 2,
As is clear from the above description, the data input terminal Din
It is possible to set the time from 0 to the period T of the clock signal as the time difference between the two data signals depending on the time difference between the signal of 1 and the signal of the clock input terminal CLKin1.

Although each unit circuit operates in the same manner,
However, transistors Q12, Q22, Q32, Q42
Signal delayed by (1/2) t + t, transistor Q
(1/2) t + 2t for 13, Q23, Q33, and Q43
Delayed signal, transistors Q14, Q24, Q3
4, Q44 is delayed by (1/2) t + 3t,
They differ in that they are input to each gate terminal.

Therefore, the signals output from the drain terminal of each unit circuit sequentially have a time difference of t. Data output terminal D among the signals output from the drain terminal
The one that travels toward out has a delay difference of t in the transmission line between the drain terminals, so at the terminal O2, the signal from the terminal O1 and the transistors Q12, Q22,
The time difference from the signals output from the drain terminals of Q32 and Q42 is eliminated, and the waveforms of FIG. 5 (7) are overlapped as shown in FIG. 5 (8).

Here, for the sake of simplicity of explanation, it is assumed that all the signals output from each drain terminal proceed to the terminal Dout. In reality, about half the amplitude will develop.

Similar superposition occurs at the terminals O3 and O4, and signal waveforms as shown in FIGS. 5 (9) and 5 (10) are obtained. Finally, the signal waveform at the O4 terminal reaches the data output terminal Dout with a delay of t / 2, and the output signal waveform shown in FIG. 4 (5) is obtained.

Since such an operation is possible up to around the cutoff frequency of the transmission line described above, it is understood that the retiming reproducing circuit operating at a very high speed can be realized by the above embodiment.

The distributed amplification type retiming reproducing circuit 1
00 has a distributed amplification type configuration in which unit circuits are connected via an inductance or a distributed constant line, and each transmission line is constituted by a capacitance component of a transistor and an inductance component of a transmission line in an equivalent circuit and cuts. Since it becomes an LC transmission line having a characteristic impedance of 50Ω, which has a very high off-frequency, the influence of the input / output capacitance of the transistor is canceled by being incorporated in this transmission line.

Therefore, the distributed amplification type retiming reproduction circuit 100 can operate up to a signal having a very high frequency component without depending on the figure of merit of the transistor used. Further, in the distributed amplification type retiming reproducing circuit 100, the unit circuit itself has a retiming reproducing function, but compared with the configuration using the conventional DFF,
Since the number of transistors is small and the configuration is extremely simple, it is possible to reduce deterioration in operating speed due to variations in transistor performance.

Further, since the distributed amplification type retiming reproducing circuit 100 adjusts the timing of the data signal by the clock and the inverted clock, it has a large adjustment margin of the time difference of the data signal and is suitable for high speed operation.

The distributed amplification type retiming reproducing circuit 1
00, the data input terminals Din1 and Din2 are exchanged, a delay circuit is inserted in the data input terminal Din1, the clock input terminal CLKin1 and the inverted clock input terminal CLKin2 are exchanged, and the clock input terminal CL
The same operation as described above is performed even when the inverted clock is applied to Kin1.

FIG. 6 is a diagram showing a distributed amplification type retiming reproducing circuit 200 according to a second embodiment of the present invention.

The distributed amplification type retiming reproduction circuit 200 is different from the distribution amplification type retiming reproduction circuit 100 in that
The delay circuit T is provided in the distributed amplification type retiming reproduction circuit 200.
This is the point where d1, Td2, and Td3 are inserted.

The delay circuits Td1, Td2, Td3 are composed of distributed constant lines and the like. In the distributed amplification type retiming reproducing circuit 200 shown in FIG. 6, when the delay circuit Td1 is inserted into the second data input terminal Din2, when the delay circuit Td2 is inserted into the gate terminal G3,
Three cases in which the delay circuit Td3 is inserted between the transistors Q3N and Q4N (N = 1, 2, 3, 4) are shown at the same time. The second data input terminal Din2
When the delay circuit Td1 is inserted in the
1 is enough, but the delay circuit T is connected to the gate terminal G3.
When d2 is inserted, it is necessary to insert one delay circuit Td2 in one unit circuit, and the transistor Q3N
And Q4N (N = 1, 2, 3, 4) between the delay circuit Td
When inserting 3 as well, it is necessary to insert one delay circuit Td3 into one unit circuit.

Further, only one of the delay circuits Td1, Td2 and Td3 may be provided,
Also, two types of delay circuits may be provided, and further three types of delay circuits may be provided at the same time.

The distributed amplification type retiming reproducing circuit 1
Although both 00 and 200 show the case where four unit circuits are connected, the number of connected unit circuits can be set to an arbitrary number of one or more. Although the field effect transistor is used as the transistor, a bipolar transistor may be used instead. In this case, the source terminal in the above description is the emitter terminal,
The drain terminal becomes the collector terminal.

FIG. 7 is a diagram showing a method of connecting a circuit of the distributed amplification type retiming reproducing circuit 200 to an external signal.

The connection method in the distributed amplification type retiming reproduction circuit 200 is the distributed amplification type retiming reproduction circuit 10.
The difference from the connection method at 0 is that the data input terminal Din
The point is that the same data signal is input to 1 and Din2.

The distributed amplification type retiming reproducing circuit 2
00, the distributed amplification retiming reproduction circuit 100
The operation is the same as the above.

That is, in the distributed amplification type retiming reproducing circuit 200, two transistors are cascode-connected to form a first series transistor group, and two transistors different from the above two transistors are cascode-connected to form a second series transistor. A series circuit is formed, and a unit circuit is formed by the first series transistor group and the second series transistor group, and the source terminal that is one end of the first series transistor group and the second series transistor group The source terminal, which is one end of the series transistor group, is grounded, and the drain terminal, which is one end of the first series transistor group that forms a predetermined unit circuit, and the second series transistor group that forms the predetermined unit circuit. A circuit in which one or a plurality of the above unit circuits are arranged, which are commonly connected to the drain terminal at one end. A.

The distributed amplification type retiming reproducing circuit 2
00 constitutes each unit circuit with a first transmission line to which each of the first gate terminals of the first series transistor group constituting each unit circuit is connected via an inductance or a distributed constant line. A second transmission line in which each of the second gate terminals of the first series transistor group is connected via an inductance or distributed constant line, and a second series transistor group of the second series transistor group forming each unit circuit. A third transmission line in which each of the first gate terminals is connected via an inductance or a distributed constant line, and a second gate terminal of the second series transistor group forming each unit circuit has an inductance or Each of the fourth transmission line connected through the distributed constant line and the commonly connected drain terminal of each unit circuit is A retiming recovery circuit; and a fifth transmission line drawers or via the distributed constant line is connected.

Further, in the distributed amplification type retiming reproducing circuit 200, a data signal is inputted to one terminal of the first transmission line and one terminal of the third transmission line, and the second signal is inputted to the second terminal. The first clock signal is input to one terminal of the transmission line, and the second clock signal that is the inverted first clock signal is input to one terminal of the fourth transmission line. One terminal of the transmission line of
An output terminal of the retiming-reproduced data signal, a position of one terminal of the third transmission line, a position of a gate terminal of a transistor connected to the third transmission line, a second position of the second series transistor group. Of the positions between the transistor having one gate terminal and the transistor having the second gate terminal of the second series transistor group,
In the retiming reproduction circuit, a delay circuit for delaying the data signal is inserted in at least one position.

[0064]

According to the present invention, a distributed amplification type retiming reproducing circuit for retiming and reproducing an ultra-high speed data signal can be realized, so that it is possible to speed up a communication transmission device and an electrical measuring device. Has the effect of being.

[Brief description of drawings]

FIG. 1 is a diagram showing a distributed amplification type retiming reproduction circuit 100 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between each terminal of the distributed amplification type retiming reproduction circuit 100 and an external signal.

3 is a diagram showing an equivalent circuit of a first transmission line portion X1 in the distributed amplification type retiming reproduction circuit 100. FIG.

4 is a diagram showing input / output signal waveforms in the distributed amplification type retiming reproduction circuit 100. FIG.

5 is a diagram schematically showing a signal waveform at an internal terminal of the distributed amplification type retiming reproduction circuit 100. FIG.

FIG. 6 is a diagram showing a distributed amplification type retiming reproducing circuit 200 according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a method of connecting a circuit of the distributed amplification type retiming reproduction circuit 200 to an external signal.

FIG. 8 is a diagram showing a configuration of a typical conventional retiming reproduction circuit 300.

[Explanation of symbols]

100, 200 ... Distributed amplification type retiming reproducing circuit, Din1 ... First data input terminal, Din2 ... Second data input terminal, CLKin1 ... First clock input terminal, CLKin2 ... Second clock input terminal, Dout ... Data output terminal, Q1I (I = 1, 2, 3, 4) ... First transistor, Q2I (I = 1, 2, 3, 4) ... Second transistor, Q3I (I = 1, 2, 3, 4) 4) ... 3rd transistor, Q4I (I = 1, 2, 3, 4) ... 4th transistor, X1 ... 1st transmission line part, X2 ... 2nd transmission line part, X3 ... 3rd transmission Line part, X4 ... Fourth transmission line part, X5 ... Fifth transmission line part, Td, Td1, Td2, Td3 ... Delay circuit, T1, T2, T3, T4, T5 ... Distributed constant line or inductance, G1, G2, G3 G4 ... Gate terminal, D ... drain terminal, S ... source terminal, input and output capacitance of C ... transistors, L ... inductance component.

Claims (2)

[Claims] 1. Two transistors are cascode-connected to form a first series transistor group, and two transistors different from the two transistors are cascode-connected to form a second series transistor group. A unit circuit is configured by one series transistor group and the second series transistor group, and a source terminal that is one end of the first series transistor group and a source terminal that is one end of the second series transistor group. Is grounded,
The drain terminal that is one end of the first series transistor group that forms the predetermined unit circuit and the drain terminal that is one end of the second series transistor group that forms the predetermined unit circuit are commonly connected, and the unit A first transmission line in which one or a plurality of circuits are arranged, and each of the first gate terminals of the first series transistor group forming each unit circuit is connected via an inductance or a distributed constant line; ,
A second transmission line in which each of the second gate terminals of the first series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A third transmission line in which each of the first gate terminals of the second series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A fourth transmission line in which each of the second gate terminals of the second series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A distributed amplification type retiming reproducing circuit comprising: a fifth transmission line in which each commonly connected drain terminal of each unit circuit is connected via an inductance or distributed constant line; The first data signal is input to one terminal of the transmission line, and the first data signal is input to one terminal of the third transmission line.
A second data signal obtained by applying a predetermined time difference to the data signal of is input to one terminal of the second transmission line,
A first clock signal is input, and a second terminal obtained by inverting the first clock signal is input to one terminal of the fourth transmission line.
The clock signal is input, and one terminal of the fifth transmission line is an output terminal of the retiming-reproduced data signal. 2. Two transistors are cascode-connected to form a first series transistor group, and two transistors different from the two transistors are cascode-connected to form a second series transistor group. A unit circuit is configured by one series transistor group and the second series transistor group, and a source terminal that is one end of the first series transistor group and a source terminal that is one end of the second series transistor group. Is grounded,
The drain terminal that is one end of the first series transistor group that forms the predetermined unit circuit and the drain terminal that is one end of the second series transistor group that forms the predetermined unit circuit are commonly connected, and the unit A first transmission line in which one or a plurality of circuits are arranged, and each of the first gate terminals of the first series transistor group forming each unit circuit is connected via an inductance or a distributed constant line; ,
A second transmission line in which each of the second gate terminals of the first series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A third transmission line in which each of the first gate terminals of the second series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A fourth transmission line in which each of the second gate terminals of the second series transistor group forming each unit circuit is connected via an inductance or distributed constant line;
A distributed amplification type retiming reproducing circuit comprising a fifth transmission line in which each commonly connected drain terminal of each unit circuit is connected via an inductance or distributed constant line, A data signal is input to one terminal of the transmission line and one terminal of the third transmission line, and the data signal is input to the second terminal.
The first clock signal is input to one terminal of the transmission line of the second transmission line, and the second clock signal obtained by inverting the first clock signal is input to the one terminal of the fourth transmission line. One of the terminals of the transmission line 5 is an output terminal for the retiming-reproduced data signal, the position of one terminal of the third transmission line, and the position of the gate terminal of the transistor connected to the third transmission line. At least one of positions between a transistor having a first gate terminal of the second series transistor group and a transistor having a second gate terminal of the second series transistor group, A distributed amplification type retiming reproducing circuit, wherein a delay circuit for delaying a data signal is inserted.