JPH0833311A - Abnormal element detector for a plurality of self-extinguishing thyristors connected in series - Google Patents

Abnormal element detector for a plurality of self-extinguishing thyristors connected in series

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Publication number
JPH0833311A
JPH0833311A JP18784194A JP18784194A JPH0833311A JP H0833311 A JPH0833311 A JP H0833311A JP 18784194 A JP18784194 A JP 18784194A JP 18784194 A JP18784194 A JP 18784194A JP H0833311 A JPH0833311 A JP H0833311A
Authority
JP
Japan
Prior art keywords
gate
signal
circuit
failure detection
self
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18784194A
Other languages
Japanese (ja)
Inventor
Junichi Inoue
純一 井上
Masakazu Kobata
雅一 木幡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP18784194A priority Critical patent/JPH0833311A/en
Publication of JPH0833311A publication Critical patent/JPH0833311A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To detect abnormality at the lower voltage part in a gate circuit each of a plurality of self-extinguishing thyristors connected in series by comparing the output level of a gate off signal command with the level of bias voltage on the output side of a gate off switch. CONSTITUTION:A failure detection circuit 76 is connected in parallel on the switch 75 side in the gate circuit 61, 62, 63 each of a plurality of self- extinguishing thyristors 11, 12, 13 connected in series. The failure detection circuit 76 has one input receiving a gate off signal 732 and the other input receiving a gate off signal command 733 from a driver 73 upon provision of a control signal 511 during OFF interval. The failure detection circuit 76 compares the gate off signal 732 with the gate off signal command 733 and delivers a failure detection signal 760 if an abnormality is detected. Since the abnormality is detected at the low voltage part in the gate circuit 61, 62, 63 and the thyristor is stopped, high voltage division is not required.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は高圧大容量電力変換器に
おける素子の異常検知を行う複数個直列接続自己消弧形
サイリスタの素子異常検知装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element abnormality detecting device for a plurality of series-connected self-extinguishing thyristors which detects an abnormality of an element in a high voltage and large capacity power converter.

【0002】[0002]

【従来の技術】高圧大容量電力変換器においては、GT
OサイリスタやSIサイリスタである自己消弧形サイリ
スタ(以下素子と称する)の複数個を直列に接続した冗
長性の高い方式によるものが適用されている。かような
複数個直列接続された素子群にあって、素子の1個が故
障したとき、残りの素子の分担電圧が増大して過電圧が
付勢され、したがって素子が破壊することがある。この
種の故障検出装置として、図5に示すものが知られてい
る。
2. Description of the Related Art In a high voltage and large capacity power converter, a GT
A highly redundant system in which a plurality of self-extinguishing thyristors (hereinafter referred to as elements) such as O thyristors and SI thyristors are connected in series is applied. In such an element group in which a plurality of elements are connected in series, when one of the elements fails, the shared voltage of the remaining elements increases and the overvoltage is activated, and thus the elements may be destroyed. As this type of failure detection device, the one shown in FIG. 5 is known.

【0003】図5は従来例を説明するため示した高圧大
容量の電力変換器の部分構成を示し、11,12,13は3個
直列接続例の素子、2は制御回路、3は素子11,12,13
にそれぞれ配されたゲート回路である。素子11において
はAはアノード、Kはカソード、Gはゲートを示す。ま
た、41,42,43は素子11,12,13にそれぞれ並列接続さ
れた発光ダイオードである。
FIG. 5 shows a partial configuration of a high-voltage and large-capacity power converter shown for explaining a conventional example. Reference numerals 11, 12, and 13 denote three serial connection elements, 2 is a control circuit, and 3 is an element 11. , 12, 13
It is a gate circuit arranged in each. In the element 11, A is an anode, K is a cathode, and G is a gate. Reference numerals 41, 42 and 43 are light emitting diodes connected in parallel to the elements 11, 12 and 13, respectively.

【0004】すなわち、制御回路2の制御信号 211, 2
12, 213を得るゲート回路31,32,33による素子11,1
2,13による高圧大容量電力変換器については公知であ
りここでの説明は省略するが、その素子部の故障検出を
行うものは、各素子11,12,13の(A−K)間に設けら
れた各発光ダイオード(フォトカプラ)41,42,43が発
する光信号 411, 421, 431を、光ファイバを通し、制
御回路2にて電気信号に変換のうえその電気信号の状態
により、故障を監視するものとなっている。
That is, the control signals 211, 2 of the control circuit 2
Devices 11,1 by gate circuits 31,32,33 to obtain 12,213
Although the high-voltage and large-capacity power converters based on 2 and 13 are publicly known and the description thereof is omitted here, the device for detecting the failure of the element part is between the elements 11, 12, and 13 (AK). The optical signals 411, 421, 431 emitted by the respective light emitting diodes (photocouplers) 41, 42, 43 provided are passed through an optical fiber, converted into an electric signal by the control circuit 2, and then a failure occurs depending on the state of the electric signal. Is to be monitored.

【0005】[0005]

【発明が解決しようとする課題】この種の従来技術にお
いては、高電圧が印加される主回路側の素子11,12,13
の端子間に並列に発光ダイオード41,42,43を取り付け
る際、高圧回路部分に近い所あるいは少し離れた所に発
光ダイオードを取り付け、さらにそこから発光ダイオー
ドが発する光を光ファイバで検出する。そのため、素子
の端子間から発光ダイオードまでの配線にも高圧が印加
され、したがって危険を伴うものであった。また、かよ
うにして素子の周辺の配線も複雑なものとなっていた。
In this type of prior art, the elements 11, 12, 13 on the main circuit side to which a high voltage is applied are applied.
When the light emitting diodes 41, 42, 43 are mounted in parallel between the terminals of, the light emitting diode is mounted at a place near or a little away from the high voltage circuit part, and the light emitted from the light emitting diode is detected by the optical fiber. Therefore, high voltage is also applied to the wiring from the terminals of the element to the light emitting diode, which is dangerous. Moreover, the wiring around the element is also complicated in this way.

【0006】[0006]

【課題を解決するための手段】本発明は上述したような
点に鑑みなされたものであって、高圧大容量電力変換器
を構成する複数個直列接続素子の各々の(ゲートとカソ
ード)間に接続した各ゲート回路の内部に、オフ信号指
令とゲートオフスイッチ出力側との比較により格別な故
障検出信号を得るとともに、かような各ゲート回路から
制御回路に信号出力し得るように構成してなるものであ
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is provided between each (gate and cathode) of a plurality of series-connected elements that constitute a high-voltage large-capacity power converter. Inside each connected gate circuit, a special failure detection signal is obtained by comparing the OFF signal command and the output side of the gate OFF switch, and such a gate circuit can be configured to output a signal to the control circuit. It will be.

【0007】[0007]

【作用】かかる解決手段により、つぎのごとき作用効果
が得られる。すなわち、各ゲート回路において素子が正
常なオフでは素子の(ゲートとカソード)間にオフバイ
アスをかけ、ドライバ出力のオフ信号指令とゲートオフ
信号の比較により、故障であるかどうかを判断できる。
故障と判断されたとき、その故障検出信号が制御回路に
送信されるものとなる。以下に、本発明を図面に基づい
てさらに詳細説明する。
By the means for solving the problems, the following operational effects can be obtained. That is, in each gate circuit, when the element is normally off, an off bias is applied between the elements (gate and cathode), and it is possible to determine whether or not there is a failure by comparing the off signal command of the driver output and the gate off signal.
When it is determined that there is a failure, the failure detection signal is transmitted to the control circuit. Hereinafter, the present invention will be described in more detail with reference to the drawings.

【0008】[0008]

【実施例】図1は本発明の技術思想の理解を容易にする
ため図5に類して示したもので、5は制御回路、61,6
2,63はゲート回路である。ここで、制御回路5の制御
信号 511, 512, 513を得るゲート回路61,62,63のそ
れぞれが、素子11,12,13をドライブして高圧大容量電
力変換器として奏する点は、図5と同様である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is similar to FIG. 5 for facilitating the understanding of the technical idea of the present invention, and 5 is a control circuit, 61, 6
Reference numerals 2 and 63 are gate circuits. Here, each of the gate circuits 61, 62 and 63 for obtaining the control signals 511, 512 and 513 of the control circuit 5 drives the elements 11, 12 and 13 and acts as a high voltage and large capacity power converter. Is the same as.

【0009】そして、かかる各ゲート回路および制御回
路においては、各ゲート回路61,62,63の内部に故障検
出回路 611, 621, 631が配されてなり、各故障検出回
路より故障検出信号 612, 622, 632が制御回路5に出
力され、したがって制御回路5は故障を監視できるもの
である。これを、図2〜図4を参照して説明する。
In each of the gate circuits and control circuits, failure detection circuits 611, 621, 631 are arranged inside each of the gate circuits 61, 62, 63, and failure detection signals 612, 612 622 and 632 are output to the control circuit 5, so that the control circuit 5 can monitor the failure. This will be described with reference to FIGS.

【0010】図2は故障検出回路を有するゲート回路の
一例を示すもので、7は図1に示される各ゲート回路6
1,62,63に相当して効用可能なゲート回路である。ゲ
ート回路7において、71はオンバイアス電源、72はオフ
バイアス電源、73はドライバ、74,75はFETを用いた
スイッチ、76は故障検出回路である。すなわち、ゲート
回路7においては、制御回路5より出力された制御信号
511がドライバ73に入力される。そして、オン信号時に
はゲートオン指令に基づくゲートオン信号 731によりス
イッチ74をオンさせ、オンバイアス電源71の電圧を素子
11の(G−K)間に印加する。また、オフ信号時にはゲ
ートオフ信号指令 733に基づき発生されるゲートオフ信
号 732によりスイッチ75をオンさせ、オフバイアス電源
72を(G−K)間に印加し、素子11をオフ状態にする。
さらには、ゲート回路7内にスイッチ75側(FETのG
−D間)に故障検出回路76が並列に接続される。 760は
故障検出信号である。これを、図3および図4に示す。
FIG. 2 shows an example of a gate circuit having a failure detection circuit, and 7 is each gate circuit 6 shown in FIG.
It is a gate circuit that can be used for 1, 62 and 63. In the gate circuit 7, 71 is an on-bias power supply, 72 is an off-bias power supply, 73 is a driver, 74 and 75 are switches using FETs, and 76 is a failure detection circuit. That is, in the gate circuit 7, the control signal output from the control circuit 5
511 is input to the driver 73. When the signal is on, the switch 74 is turned on by the gate-on signal 731 based on the gate-on command, and the voltage of the on-bias power supply 71 is turned on.
Apply between 11 (G-K). When the signal is off, the switch 75 is turned on by the gate off signal 732 generated based on the gate off signal command 733 to turn off the off bias power supply.
72 is applied between (G-K) to turn off the element 11.
Furthermore, in the gate circuit 7, the switch 75 side (FET G
The failure detection circuit 76 is connected in parallel between (-D). Reference numeral 760 is a failure detection signal. This is shown in FIGS. 3 and 4.

【0011】図3および図4は故障検出回路の一例をお
よびその信号出力のタイミングチャートをそれぞれ示す
もので、 761はフォトカプラ、 762は比較器である。図
3は示す故障検出回路76において、フォトカプラ 761は
オフバイアスのためのスイッチ75へのゲートオフ信号 7
32を検知する。比較器 762は、ゲートオフ信号 732を一
方の入力とし、またドライバ73にて制御信号 511入力よ
りオフ時に得られるゲートオフ信号指令 733を他方の入
力とし、両者を比較のうえ、異常があった場合には故障
検出信号 760を発生する。つまり図4に示した如く、ゲ
ートオフ信号指令 733が「H」,ゲートオフ信号732が
「L」,ゲートオフ信号指令 733が「L」でゲートオフ
信号 732が「H」のときは正常とする。ゲートオフ信号
733が「L」でゲートオフ信号 732「L」のとき素子に
異常があったものとみなし、故障検出信号 760は「L」
から「H」に変わり、信号発生し得る。
FIGS. 3 and 4 show an example of a failure detection circuit and a timing chart of its signal output, where 761 is a photocoupler and 762 is a comparator. In the fault detection circuit 76 shown in FIG. 3, the photocoupler 761 outputs a gate-off signal 7 to the switch 75 for off-bias.
Detect 32. The comparator 762 receives the gate-off signal 732 as one input, and the gate-off signal command 733 obtained when the driver 73 is turned off from the control signal 511 input as the other input. Generates a fault detection signal 760. That is, as shown in FIG. 4, it is normal when the gate-off signal command 733 is "H", the gate-off signal 732 is "L", the gate-off signal command 733 is "L", and the gate-off signal 732 is "H". Gate-off signal
When the 733 is "L" and the gate-off signal is 732 "L", it is considered that there is an abnormality in the element, and the failure detection signal 760 is "L".
To "H" and a signal can be generated.

【0012】これをさらに具体的に説明すると、ゲート
回路7においては、素子11が正常でオフにて素子11の
(G−K)間にバイアスをかけ、オフバイアス電圧を供
給するスイッチ75の(G−S)間にも(+5V)程度の
ゲートオフ信号 732をドライバ73より出力させる。これ
より、素子11の故障時には(G−K)間にはバイアスが
かからなくなって、スイッチ75の(G−S)間のゲート
オフ信号 732も(OV)となり、故障検出信号 760を得
ることができる。
To explain this more concretely, in the gate circuit 7, when the element 11 is normal and is off, a bias is applied between (G-K) of the element 11 and the switch 75 ( The gate-off signal 732 of about (+5 V) is output from the driver 73 also during G-S). As a result, when the element 11 fails, no bias is applied during (G-K), and the gate-off signal 732 between (G-S) of the switch 75 also becomes (OV), and the failure detection signal 760 can be obtained. it can.

【0013】さらには、かかる実施例はつぎの如きもの
であることは論ずるまでもない。 (1) ゲート回路内の故障検出回路によりそれぞれ素
子破壊で短絡状態になったことを制御回路で得られ、装
置として残りの素子を全てオン状態にて電流を別の保護
装置によるしゃ断のうえ素子にゲートブロックをかける
ことや、それぞれの故障検出信号を受けてから残りの素
子にゲートブロックをかけて装置を停止させることな
ど、回路構成によりいかようにも容易に適用し得る。 (2) 各ゲート回路にてゲート回路を動作させる電源
が故障した場合にはスイッチの(D−S)間に信号電圧
は出力されず短絡状態となって故障検出回路にてレベル
検出し、ゲート回路を動作させる電源が喪失した場合に
は素子にゲート信号が送られず素子にはオフバイアスが
かからなくなり、残りの素子の分担電圧の増加による過
電圧から素子破壊する恐れがあることを防ぎ、装置停止
を行うことができる。 (3) 制御回路の故障あるいは制御回路からゲート回
までの配線の短絡などにより、各素子のゲート回路への
制御信号の送信不能になっても、前述したような過電圧
保護を実現できる。
Further, it goes without saying that such an embodiment is as follows. (1) The failure detection circuit in the gate circuit provides the control circuit with the fact that each of the elements has been short-circuited due to element destruction. As a device, all the remaining elements are on and the current is cut off by another protective device. Can be easily applied depending on the circuit configuration, such as applying a gate block to the device, or applying a gate block to the remaining elements after receiving the respective failure detection signals to stop the device. (2) When the power supply for operating the gate circuit in each gate circuit fails, a signal voltage is not output during (DS) of the switch, a short circuit occurs, and the level is detected by the failure detection circuit. When the power supply for operating the circuit is lost, the gate signal is not sent to the element and the element is no longer off-biased, preventing the possibility of element destruction from overvoltage due to an increase in the shared voltage of the remaining elements, The device can be stopped. (3) Even if the control signal cannot be transmitted to the gate circuit of each element due to a failure of the control circuit or a short circuit of the wiring from the control circuit to the gate circuit, the above-mentioned overvoltage protection can be realized.

【0014】[0014]

【発明の効果】以上説明したように本発明によれば、複
数個直列接続される素子の1個が破壊しても、ゲート回
路内の低圧部で異常検知し得ることで高圧分圧等も必要
なくなり、かような各素子の異常検知から残りの素子の
過電圧保護等を含めていかようにも簡単かつ容易に実施
可能にした簡便な構成の装置を提供できる。
As described above, according to the present invention, even if one of a plurality of elements connected in series is broken, an abnormality can be detected in the low voltage portion in the gate circuit, so that high voltage partial pressure and the like can be achieved. It is possible to provide a device having a simple structure that can be easily and easily implemented by eliminating the need for detecting abnormality of each element and including overvoltage protection of the remaining elements.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明の技術思想の理解を容易にするた
め示した系統図である。
FIG. 1 is a system diagram shown to facilitate understanding of a technical idea of the present invention.

【図2】図2は本発明によるゲート回路の一実施例の要
部構成を示す系統図である。
FIG. 2 is a system diagram showing a main part configuration of an embodiment of a gate circuit according to the present invention.

【図3】図3は図2の故障検出回路の一例を示す系統図
である。
FIG. 3 is a system diagram showing an example of the failure detection circuit of FIG.

【図4】図4は図3の説明のため示したタイミングチャ
ートである。
FIG. 4 is a timing chart shown for explaining FIG.

【図5】図5は従来例の電力変換器の部分構成を示す系
統図である。
FIG. 5 is a system diagram showing a partial configuration of a conventional power converter.

【符号の説明】[Explanation of symbols]

11 自己消弧形サイリスタ(素子) 12 自己消弧形サイリスタ(素子) 13 自己消弧形サイリスタ(素子) 2 制御回路 31 ゲート回路 32 ゲート回路 33 ゲート回路 41 発光ダイオード 42 発光ダイオード 43 発光ダイオード 5 制御回路 61 ゲート回路 62 ゲート回路 63 ゲート回路 611 故障検出回路 612 故障検出回路 613 故障検出回路 7 ゲート回路 71 オンバイアス電源 72 オフバイアス電源 73 ドライバ 74 スイッチ 75 スイッチ 76 故障検出回路 761 フォトカプラ 762 比較器 11 Self-extinguishing thyristor (element) 12 Self-extinguishing thyristor (element) 13 Self-extinguishing thyristor (element) 2 Control circuit 31 Gate circuit 32 Gate circuit 33 Gate circuit 41 Light emitting diode 42 Light emitting diode 43 Light emitting diode 5 Control Circuit 61 Gate circuit 62 Gate circuit 63 Gate circuit 611 Failure detection circuit 612 Failure detection circuit 613 Failure detection circuit 7 Gate circuit 71 On-bias power supply 72 Off-bias power supply 73 Driver 74 Switch 75 Switch 76 Failure detection circuit 761 Photocoupler 762 Comparator

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数個直列に接続された自己消弧形サイ
リスタからなる電力変換器において、直列接続された各
自己消弧形サイリスタのゲート回路内に、ゲートオフ信
号指令出力レベルとゲートオフスイッチ出力側のバイア
ス電圧レベルを比較する手段を設け、該比較する手段出
力を故障検出信号として得るようにしたことを特徴とす
る複数個直列接続自己消弧形サイスリタの素子異常検知
装置。
1. A power converter comprising a plurality of self-extinguishing thyristors connected in series, wherein a gate-off signal command output level and a gate-off switch output are provided in a gate circuit of each self-extinguishing thyristor connected in series. A device abnormality detecting device for a plurality of series-connected self-extinguishing type thyristors, characterized in that means for comparing the bias voltage levels on the side is provided, and the output of the comparing means is obtained as a failure detection signal.
JP18784194A 1994-07-18 1994-07-18 Abnormal element detector for a plurality of self-extinguishing thyristors connected in series Pending JPH0833311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18784194A JPH0833311A (en) 1994-07-18 1994-07-18 Abnormal element detector for a plurality of self-extinguishing thyristors connected in series

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18784194A JPH0833311A (en) 1994-07-18 1994-07-18 Abnormal element detector for a plurality of self-extinguishing thyristors connected in series

Publications (1)

Publication Number Publication Date
JPH0833311A true JPH0833311A (en) 1996-02-02

Family

ID=16213172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18784194A Pending JPH0833311A (en) 1994-07-18 1994-07-18 Abnormal element detector for a plurality of self-extinguishing thyristors connected in series

Country Status (1)

Country Link
JP (1) JPH0833311A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352233B1 (en) * 2004-06-14 2008-04-01 Otward Mueller Efficient thyristor-type power switches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7352233B1 (en) * 2004-06-14 2008-04-01 Otward Mueller Efficient thyristor-type power switches

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